Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25113

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3807

1

T3

2

T6

1

T7

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22345

1

T2

15

T3

2

T6

29

auto[1]

6575

1

T1

20

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	659	1			T6	9		T9	6		T45	1
values[0]	106	1			T272	18		T287	20		T194	29
values[1]	798	1			T3	1		T35	17		T110	1
values[2]	3209	1			T1	20		T3	1		T6	7
values[3]	771	1			T4	13		T6	1		T12	4
values[4]	630	1			T3	1		T33	5		T24	27
values[5]	582	1			T5	11		T9	4		T10	10
values[6]	749	1			T7	7		T110	2		T36	5
values[7]	643	1			T27	8		T151	1		T36	13
values[8]	643	1			T9	2		T35	17		T12	18
values[9]	866	1			T10	15		T139	2		T13	1
minimum	19264	1			T2	15		T6	22		T9	77

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	774	1			T8	17		T35	17		T139	1
values[1]	3174	1			T1	20		T3	1		T6	7
values[2]	853	1			T4	13		T6	1		T12	4
values[3]	476	1			T3	1		T5	11		T9	4
values[4]	664	1			T11	30		T110	1		T38	25
values[5]	684	1			T7	7		T110	1		T151	1
values[6]	784	1			T27	8		T36	13		T50	34
values[7]	551	1			T9	2		T10	15		T35	17
values[8]	766	1			T12	18		T13	1		T28	1
values[9]	102	1			T239	19		T177	9		T312	10
minimum	20092	1			T2	15		T3	1		T6	31

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T35	17		T110	1		T103	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T8	6		T139	1		T27	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T1	2		T6	6		T34	46
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T3	1		T105	1		T106	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T4	13		T12	4		T181	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T6	1		T24	14		T135	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T5	6		T9	4		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T10	1		T33	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T38	13		T16	10		T32	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	16		T110	1		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T110	1		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T7	1		T36	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	1		T143	1		T144	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T27	8		T36	8		T50	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T9	1		T139	1		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	1		T35	17		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T12	9		T106	14		T183	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T13	1		T28	1		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T312	10		T99	5		T317	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T239	11		T177	1		T329	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19673	1			T2	15		T3	1		T6	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T26	1		T172	1		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T172	16		T149	2		T155	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	11		T133	8		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1047	1			T1	18		T6	1		T67	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T105	14		T31	2		T32	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T181	10		T155	11		T187	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T24	13		T180	14		T15	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T5	5		T237	13		T292	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T10	9		T164	3		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T38	12		T16	6		T32	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	14		T39	3		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T221	7		T150	6		T157	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	6		T36	2		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T144	3		T148	2		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T36	5		T50	17		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T9	1		T22	4		T37	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T10	14		T14	7		T180	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T12	9		T173	1		T239	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T140	10		T180	10		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T99	3		T330	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T239	8		T177	8		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T172	8		T15	3		T228	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	568	1			T6	9		T9	6		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T177	1		T289	7		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T272	9		T194	16		T100	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T287	11		T315	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	1		T35	17		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T26	1		T133	9		T103	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	2		T6	6		T34	46
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	378	1			T3	1		T8	6		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T4	13		T12	4		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T6	1		T180	12		T15	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T37	2		T152	1		T154	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T33	5		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T5	6		T9	4		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T10	1		T11	16		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T110	1		T221	11		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	1		T110	1		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	1		T38	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T27	8		T36	8		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	1		T12	9		T22	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	17		T26	1		T50	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T139	1		T183	10		T175	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	1		T139	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19115	1			T2	15		T6	22		T9	75
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T173	1		T99	3		T331	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T177	8		T289	9		T332	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T272	9		T194	13		T100	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T287	9		T315	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T222	6		T155	4		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T133	8		T172	8		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1056	1			T1	18		T6	1		T67	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T8	11		T105	14		T31	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T181	10		T155	11		T187	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T180	14		T15	1		T229	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T237	13		T291	2		T253	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	13		T32	13		T164	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T5	5		T38	12		T16	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	9		T11	14		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T221	7		T150	6		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	6		T36	2		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T144	3		T148	2		T157	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T36	5		T144	1		T221	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T12	9		T22	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T50	17		T180	12		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T175	9		T239	12		T267	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	14		T140	10		T14	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T35	1		T110	1		T103	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T8	12		T139	1		T27	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1388	1			T1	20		T6	5		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T3	1		T105	15		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T4	1		T12	1		T181	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T24	14		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T5	6		T9	3		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	1		T10	10		T33	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T38	14		T16	8		T32	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	15		T110	1		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T110	1		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	7		T36	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T137	1		T143	1		T144	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T27	1		T36	8		T50	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	2		T139	1		T22	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	15		T35	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T12	13		T106	1		T183	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T28	1		T140	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T312	1		T99	5		T317	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T239	9		T177	9		T329	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19813	1			T2	15		T3	1		T6	31
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T26	1		T172	9		T15	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T35	16		T103	7		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T8	5		T27	11		T133	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1229	1			T6	2		T34	43		T43	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T106	16		T142	6		T32	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	12		T12	3		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T24	13		T135	8		T180	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T5	5		T9	1		T154	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T33	2		T164	3		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T38	11		T16	8		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T11	15		T39	3		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T221	10		T157	9		T237	24
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T36	2		T136	14		T243	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T144	4		T148	2		T154	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T27	7		T36	5		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T37	1		T106	13		T146	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T35	16		T14	7		T180	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	5		T106	13		T183	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T140	6		T180	13		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T312	9		T99	3		T317	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T239	10		T318	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T162	9		T222	6		T319	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T263	9		T311	5		T228	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	532	1			T6	9		T9	6		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T177	9		T289	10		T99	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T272	10		T194	14		T100	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T287	10		T315	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T35	1		T110	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T26	1		T133	9		T103	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1392	1			T1	20		T6	5		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T3	1		T8	12		T139	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T4	1		T12	1		T181	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	1		T180	15		T15	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T37	2		T152	1		T154	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	1		T33	3		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	6		T9	3		T38	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T10	10		T11	15		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T110	1		T221	8		T150	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	7		T110	1		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T151	1		T38	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T27	1		T36	8		T31	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T9	2		T12	13		T22	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T35	1		T26	1		T50	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T139	1		T183	1		T175	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	15		T139	1		T13	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19264	1			T2	15		T6	22		T9	77
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T106	13		T173	1		T99	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T289	6		T332	8		T168	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T272	8		T194	15		T171	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T287	10		T315	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	16		T103	7		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T133	8		T103	15		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1190	1			T6	2		T34	43		T43	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T8	5		T27	11		T106	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T4	12		T12	3		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T180	11		T229	11		T174	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T154	12		T237	14		T291	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	2		T24	13		T135	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	5		T9	1		T38	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T11	15		T39	3		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T221	10		T237	13		T291	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T36	2		T136	14		T15	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T144	4		T148	2		T154	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T27	7		T36	5		T243	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T12	5		T37	1		T106	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T35	16		T50	16		T180	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T183	9		T239	15		T274	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T140	6		T14	7		T180	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2