Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25757

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3163

1

T3

2

T5

11

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22684

1

T2

15

T3

2

T4

13

auto[1]

6236

1

T1

20

T3

1

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	258	1			T9	4		T106	14		T246	1
values[0]	111	1			T142	12		T239	28		T202	33
values[1]	750	1			T151	1		T37	8		T106	17
values[2]	745	1			T3	1		T10	15		T139	1
values[3]	550	1			T3	1		T35	17		T12	18
values[4]	592	1			T3	1		T10	10		T26	1
values[5]	728	1			T6	7		T33	5		T110	1
values[6]	639	1			T4	13		T6	1		T8	17
values[7]	513	1			T9	2		T103	16		T38	1
values[8]	770	1			T7	7		T11	30		T67	14
values[9]	3500	1			T1	20		T5	11		T34	46
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	741	1			T12	4		T37	2		T136	29
values[1]	734	1			T3	2		T10	15		T35	17
values[2]	462	1			T10	10		T12	18		T13	1
values[3]	632	1			T3	1		T6	7		T26	2
values[4]	751	1			T8	17		T33	5		T110	1
values[5]	658	1			T4	13		T6	1		T110	1
values[6]	2680	1			T1	20		T9	2		T34	46
values[7]	898	1			T7	7		T11	30		T67	14
values[8]	1107	1			T5	11		T9	4		T35	17
values[9]	189	1			T139	1		T106	14		T172	16
minimum	20068	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	4		T136	15		T162	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T37	2		T141	1		T15	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T35	17		T139	1		T22	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T3	2		T10	1		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T10	1		T12	9		T27	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	1		T38	13		T144	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	1		T26	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	6		T26	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	5		T110	1		T24	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T8	6		T101	1		T106	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	13		T6	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T36	3		T38	1		T142	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1538	1			T1	2		T9	1		T34	46
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T181	1		T172	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T7	1		T11	16		T67	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T39	9		T16	10		T32	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T9	4		T26	1		T103	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T5	6		T35	17		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T239	11		T288	1		T230	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T139	1		T106	14		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19706	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T151	1		T142	12		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T136	14		T164	3		T222	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T15	1		T164	13		T221	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T22	4		T180	12		T16	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T10	14		T31	2		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T10	9		T12	9		T140	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T38	12		T144	2		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T149	2		T223	4		T224	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	1		T173	8		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T24	13		T180	14		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T8	11		T147	9		T225	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T36	5		T172	8		T150	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T36	2		T38	2		T227	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T1	18		T9	1		T107	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T181	10		T172	16		T145	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T7	6		T11	14		T67	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T39	3		T16	6		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T180	10		T228	12		T220	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	5		T38	1		T229	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T239	8		T288	16		T230	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T172	15		T252	12		T233	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T15	3		T150	1		T241	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T9	4		T219	3		T333	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T106	14		T246	1		T146	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T239	16		T202	18		T236	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T142	12		T233	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T37	4		T106	17		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T151	1		T15	2		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T139	1		T12	4		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T10	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T35	17		T12	9		T27	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	1		T13	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	1		T10	1		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T26	1		T38	13		T173	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T33	5		T110	1		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T6	6		T101	1		T106	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	13		T6	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	6		T36	3		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T9	1		T103	16		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T181	1		T152	1		T235	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T7	1		T11	16		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T172	1		T16	10		T32	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1747	1			T1	2		T34	46		T86	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	364	1			T5	6		T35	17		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T188	10		T288	16		T334	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T146	10		T238	2		T218	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T239	12		T202	15		T236	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T233	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T37	4		T136	14		T164	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T15	3		T221	13		T150	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T22	4		T16	3		T222	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T10	14		T15	2		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	9		T105	14		T180	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T31	2		T144	2		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	9		T140	10		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T38	12		T173	8		T222	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T24	13		T180	14		T146	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T6	1		T147	9		T98	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T36	5		T172	8		T226	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T8	11		T36	2		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	1		T150	6		T175	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T181	10		T235	3		T320	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	6		T11	14		T67	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T172	16		T16	6		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1109	1			T1	18		T107	21		T109	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	5		T38	1		T39	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	1		T136	15		T162	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T37	2		T141	1		T15	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T35	1		T139	1		T22	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	2		T10	15		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	10		T12	13		T27	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	1		T38	14		T144	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T3	1		T26	1		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	5		T26	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T33	3		T110	1		T24	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	12		T101	1		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T4	1		T6	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	3		T38	3		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1250	1			T1	20		T9	2		T34	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T181	11		T172	17		T145	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T7	7		T11	15		T67	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	9		T16	8		T32	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T9	3		T26	1		T103	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T5	6		T35	1		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T239	9		T288	17		T230	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T139	1		T106	1		T172	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19828	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T151	1		T142	1		T15	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	3		T136	14		T162	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T15	2		T164	12		T221	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T35	16		T27	7		T180	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T144	4		T238	11		T79	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	5		T27	11		T140	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T38	11		T144	2		T148	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	3		T223	7		T224	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	2		T163	12		T98	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T33	2		T24	13		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T8	5		T106	13		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	12		T36	5		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T36	2		T142	6		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T34	43		T43	15		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T165	8		T232	8		T287	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	15		T133	8		T14	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	3		T16	8		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T9	1		T103	7		T180	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T5	5		T35	16		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T239	10		T230	12		T290	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T106	13		T252	13		T233	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T37	1		T106	16		T239	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T142	11		T241	8		T242	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T9	3		T219	1		T333	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T106	1		T246	1		T146	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T239	13		T202	16		T236	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T142	1		T233	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T37	7		T106	1		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T151	1		T15	5		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T139	1		T12	1		T22	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	1		T10	15		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T35	1		T12	13		T27	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	1		T13	1		T31	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	1		T10	10		T28	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T26	1		T38	14		T173	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T33	3		T110	1		T24	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	5		T101	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T4	1		T6	1		T110	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T8	12		T36	3		T38	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T9	2		T103	1		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T181	11		T152	1		T235	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T7	7		T11	15		T67	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T172	17		T16	8		T32	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1459	1			T1	20		T34	3		T86	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T5	6		T35	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T9	1		T219	2		T188	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T106	13		T146	8		T238	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T239	15		T202	17		T236	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T142	11		T233	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T37	1		T106	16		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T221	13		T241	8		T242	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	3		T27	7		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T15	2		T144	4		T164	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T35	16		T12	5		T27	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T144	2		T148	1		T174	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T140	6		T149	3		T223	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T38	11		T163	12		T165	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	2		T24	13		T180	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	2		T106	13		T183	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	12		T36	5		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T8	5		T36	2		T142	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T103	15		T135	4		T163	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T165	8		T232	8		T287	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	15		T133	8		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T16	8		T32	12		T138	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1397	1			T34	43		T43	15		T108	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T5	5		T35	16		T39	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2