Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25251

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3669

1

T3

2

T5

11

T6

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22937

1

T2

15

T5

11

T6

39

auto[1]

5983

1

T1

20

T3

3

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T10	10		T281	1		T138	6
values[0]	61	1			T36	5		T103	16		T241	20
values[1]	754	1			T3	1		T4	13		T35	17
values[2]	778	1			T9	4		T10	15		T33	5
values[3]	927	1			T5	11		T26	1		T140	17
values[4]	467	1			T67	14		T26	1		T105	15
values[5]	2821	1			T1	20		T3	1		T6	8
values[6]	694	1			T7	7		T9	2		T37	2
values[7]	730	1			T139	1		T26	1		T27	8
values[8]	560	1			T101	2		T38	25		T181	11
values[9]	1098	1			T3	1		T11	30		T35	17
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	634	1			T3	1		T4	13		T139	1
values[1]	812	1			T9	4		T33	5		T139	1
values[2]	930	1			T5	11		T10	15		T26	1
values[3]	2621	1			T1	20		T3	1		T6	1
values[4]	684	1			T6	7		T8	17		T22	5
values[5]	645	1			T7	7		T9	2		T139	1
values[6]	733	1			T26	1		T27	8		T38	25
values[7]	638	1			T110	1		T28	1		T101	2
values[8]	998	1			T3	1		T10	10		T11	30
values[9]	158	1			T281	1		T164	7		T261	11
minimum	20067	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	1		T4	13		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T110	1		T172	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T9	4		T33	5		T12	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T139	1		T12	9		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T26	1		T103	8		T162	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T5	6		T10	1		T140	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T1	2		T6	1		T34	46
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T3	1		T67	1		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	1		T14	9		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	6		T8	6		T22	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T153	5		T148	1		T163	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T7	1		T9	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T27	8		T141	1		T173	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T26	1		T38	13		T15	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T110	1		T145	1		T164	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T28	1		T101	2		T181	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T10	1		T35	17		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T3	1		T11	16		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T281	1		T164	4		T261	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T225	16		T291	9		T335	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19693	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T35	17		T36	3		T147	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T24	13		T133	8		T36	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T172	16		T238	11		T232	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T37	4		T180	12		T157	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	9		T180	10		T222	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T144	3		T173	1		T149	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	5		T10	14		T140	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T1	18		T107	21		T109	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T67	13		T105	14		T38	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T14	7		T15	2		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	1		T8	11		T22	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T153	12		T155	4		T241	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	6		T9	1		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T173	8		T228	10		T222	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T38	12		T15	3		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T145	13		T164	13		T148	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T181	10		T172	8		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T10	9		T136	14		T138	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T11	14		T39	3		T180	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T164	3		T285	2		T287	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T225	6		T291	2		T335	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T36	2		T147	9		T174	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T10	1		T281	1		T138	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T226	1		T336	9		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T103	16		T241	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T36	3		T234	3		T322	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	1		T4	13		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T35	17		T110	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	4		T33	5		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	1		T139	1		T12	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T26	1		T103	8		T162	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T5	6		T140	7		T106	28
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T50	17		T142	7		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T67	1		T26	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1616	1			T1	2		T6	1		T34	46
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T6	6		T8	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T246	1		T153	5		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	1		T9	1		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T27	8		T141	1		T260	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	1		T26	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T164	13		T173	2		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T101	2		T38	13		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T35	17		T110	1		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T3	1		T11	16		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T10	9		T138	3		T164	3
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T226	13		T336	12		T177	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T241	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T36	2		T234	6		T322	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T24	13		T133	8		T36	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T147	9		T174	5		T238	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T37	4		T180	12		T221	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	14		T12	9		T172	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T173	1		T149	2		T238	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	5		T140	10		T180	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T50	17		T146	7		T144	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T67	13		T105	14		T38	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	952	1			T1	18		T107	21		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T6	1		T8	11		T22	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T153	12		T241	1		T218	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T7	6		T9	1		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T222	6		T155	4		T157	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T15	3		T32	13		T150	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T164	13		T173	8		T148	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T38	12		T181	10		T172	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T136	14		T144	2		T145	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	14		T39	3		T180	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T4	1		T139	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T110	1		T172	17		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T9	3		T33	3		T12	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T139	1		T12	13		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T26	1		T103	1		T162	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T5	6		T10	15		T140	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1252	1			T1	20		T6	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	1		T67	14		T26	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T13	1		T14	9		T15	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	5		T8	12		T22	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T153	13		T148	1		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T7	7		T9	2		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T27	1		T141	1		T173	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T26	1		T38	14		T15	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T110	1		T145	14		T164	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T28	1		T101	2		T181	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T10	10		T35	1		T136	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T3	1		T11	15		T151	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T281	1		T164	4		T261	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T225	7		T291	3		T335	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19825	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T35	1		T36	3		T147	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	12		T24	13		T133	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T262	3		T232	8		T237	25
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T9	1		T33	2		T12	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	5		T106	13		T180	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T103	7		T162	9		T144	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T5	5		T140	6		T106	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1188	1			T34	43		T43	15		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T16	2		T219	2		T230	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	7		T15	2		T146	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T6	2		T8	5		T27	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T153	4		T163	6		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T243	12		T149	3		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T27	7		T260	18		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T38	11		T32	16		T154	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T164	12		T228	17		T163	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T32	12		T221	13		T261	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T35	16		T136	14		T138	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	15		T106	16		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T164	3		T261	10		T285	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T225	15		T291	8		T283	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T103	15		T241	10		T337	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T35	16		T36	2		T147	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T10	10		T281	1		T138	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T226	14		T336	13		T177	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T103	1		T241	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T36	3		T234	7		T322	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	1		T4	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T35	1		T110	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T9	3		T33	3		T110	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	15		T139	1		T12	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T26	1		T103	1		T162	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	6		T140	11		T106	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T50	18		T142	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T67	14		T26	1		T105	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1281	1			T1	20		T6	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	1		T6	5		T8	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T246	1		T153	13		T148	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T7	7		T9	2		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T27	1		T141	1		T260	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T139	1		T26	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T164	14		T173	10		T148	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T101	2		T38	14		T181	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T35	1		T110	1		T136	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T3	1		T11	15		T28	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T138	2		T164	3		T261	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T336	8		T291	8		T338	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T103	15		T241	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T36	2		T234	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	12		T24	13		T133	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	16		T147	11		T174	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T9	1		T33	2		T12	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T12	5		T263	9		T242	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T103	7		T162	9		T173	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T5	5		T140	6		T106	26
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T50	16		T142	6		T146	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T16	2		T274	8		T324	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T34	43		T43	15		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T6	2		T8	5		T27	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T153	4		T163	6		T218	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T16	8		T243	20		T221	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T27	7		T260	18		T222	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T32	16		T154	18		T274	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T164	12		T228	12		T239	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T38	11		T32	12		T221	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T35	16		T136	14		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	15		T106	16		T39	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2