Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25346

1

T1

20

T2

15

T6

39

auto[ADC_CTRL_FILTER_COND_OUT]

3574

1

T3

3

T4

13

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22831

1

T2

15

T3

3

T5

11

auto[1]

6089

1

T1

20

T4

13

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	363	1			T3	1		T140	17		T38	3
values[0]	151	1			T9	2		T173	10		T184	11
values[1]	702	1			T5	11		T139	1		T26	1
values[2]	817	1			T3	2		T35	17		T26	1
values[3]	791	1			T10	10		T67	14		T103	16
values[4]	2805	1			T1	20		T7	7		T9	4
values[5]	616	1			T11	30		T38	3		T106	17
values[6]	587	1			T105	15		T31	1		T135	5
values[7]	709	1			T6	7		T8	17		T10	15
values[8]	542	1			T4	13		T6	1		T110	1
values[9]	1073	1			T33	5		T35	17		T139	2
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	826	1			T5	11		T26	1		T151	1
values[1]	706	1			T3	2		T35	17		T26	1
values[2]	762	1			T10	10		T67	14		T103	16
values[3]	2806	1			T1	20		T7	7		T9	4
values[4]	616	1			T11	30		T38	3		T106	17
values[5]	550	1			T105	15		T135	5		T162	10
values[6]	849	1			T6	7		T8	17		T10	15
values[7]	553	1			T4	13		T6	1		T110	2
values[8]	1011	1			T33	5		T35	17		T139	2
values[9]	167	1			T3	1		T28	1		T180	23
minimum	20074	1			T2	15		T6	31		T9	85

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T151	1		T133	9		T37	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	6		T26	1		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T35	17		T31	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	2		T26	1		T38	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	1		T67	1		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T103	16		T142	7		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T1	2		T9	4		T34	46
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	1		T110	1		T27	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	16		T38	1		T106	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T180	14		T183	10		T172	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T135	5		T162	10		T16	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T105	1		T143	1		T173	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	6		T8	6		T12	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T10	1		T24	14		T103	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	1		T110	2		T12	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T4	13		T13	1		T27	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T140	7		T101	1		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T33	5		T35	17		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T28	1		T294	1		T295	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T3	1		T180	11		T239	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19673	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T9	1		T139	1		T15	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T133	8		T37	4		T226	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	5		T36	2		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T31	2		T16	3		T221	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T38	12		T136	14		T32	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	9		T67	13		T148	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T228	12		T241	1		T218	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	990	1			T1	18		T107	21		T109	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T7	6		T14	7		T166	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T11	14		T38	2		T147	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T180	10		T172	31		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T16	6		T144	3		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T105	14		T173	1		T187	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T6	1		T8	11		T12	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T10	14		T24	13		T50	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	5		T39	3		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T222	6		T155	10		T187	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T140	10		T32	13		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T38	1		T181	10		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T297	13		T298	10		T330	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T180	12		T239	12		T237	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T9	1		T15	3		T184	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T140	7		T149	4		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T3	1		T38	2		T180	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T299	9		T339	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T9	1		T173	2		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T151	1		T133	9		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T5	6		T139	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T35	17		T37	2		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T3	2		T26	1		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T10	1		T67	1		T221	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T103	16		T142	7		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T1	2		T9	4		T34	46
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T7	1		T110	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	16		T38	1		T106	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T180	14		T183	10		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	1		T135	5		T162	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T105	1		T172	1		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	6		T8	6		T12	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	1		T103	8		T106	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	1		T110	1		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T4	13		T13	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	341	1			T110	1		T12	4		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	345	1			T33	5		T35	17		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T140	10		T149	11		T248	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T38	1		T180	12		T164	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T299	4		T339	13		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T9	1		T173	8		T184	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	8		T37	4		T226	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	5		T15	5		T138	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T31	2		T16	3		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T36	2		T38	12		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	9		T67	13		T221	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T241	1		T218	4		T301	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	991	1			T1	18		T107	21		T109	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T7	6		T14	7		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	14		T38	2		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T180	10		T172	15		T285	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	6		T144	3		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T105	14		T172	16		T173	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	1		T8	11		T12	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	14		T180	14		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T39	3		T172	8		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T24	13		T50	17		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T36	5		T32	13		T164	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T181	10		T146	7		T144	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T151	1		T133	9		T37	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	6		T26	1		T36	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T35	1		T31	3		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	2		T26	1		T38	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T10	10		T67	14		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T103	1		T142	1		T256	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T1	20		T9	3		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	7		T110	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	15		T38	3		T106	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T180	11		T183	1		T172	33
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T135	1		T162	1		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T105	15		T143	1		T173	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	5		T8	12		T12	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T10	15		T24	14		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	1		T110	2		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T4	1		T13	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	317	1			T140	11		T101	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T33	3		T35	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T28	1		T294	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T3	1		T180	13		T239	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19834	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T9	2		T139	1		T15	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T133	8		T37	1		T243	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	5		T36	2		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	16		T16	2		T260	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T38	11		T136	14		T32	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T106	13		T148	3		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T103	15		T142	6		T260	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1254	1			T9	1		T34	43		T43	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T27	7		T14	7		T185	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T11	15		T106	16		T147	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T180	13		T183	9		T142	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T135	4		T162	9		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T173	1		T263	9		T242	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T6	2		T8	5		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T24	13		T103	7		T106	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T12	3		T36	5		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T4	12		T27	11		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T140	6		T135	8		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T33	2		T35	16		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T295	9		T302	12		T330	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T180	10		T239	15		T237	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T165	5		T272	8		T20	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T165	6		T340	9		T252	13

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T140	11		T149	12		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	1		T38	3		T180	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T299	5		T339	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T9	2		T173	10		T184	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T151	1		T133	9		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	6		T139	1		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	1		T37	2		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	2		T26	1		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T10	10		T67	14		T221	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T103	1		T142	1		T256	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T1	20		T9	3		T34	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	7		T110	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	15		T38	3		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T180	11		T183	1		T172	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T31	1		T135	1		T162	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T105	15		T172	17		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	5		T8	12		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T10	15		T103	1		T106	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	1		T110	1		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T4	1		T13	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T110	1		T12	1		T28	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T33	3		T35	1		T139	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T140	6		T149	3		T293	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T180	10		T164	12		T311	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T299	8		T339	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T165	6		T274	10		T341	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T133	8		T37	1		T221	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T5	5		T15	2		T138	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T35	16		T16	2		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T36	2		T38	11		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T221	10		T148	1		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T103	15		T142	6		T260	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T9	1		T34	43		T43	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T27	7		T14	7		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	15		T106	16		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T180	13		T183	9		T285	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T135	4		T162	9		T16	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T142	11		T173	1		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T6	2		T8	5		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T103	7		T106	13		T180	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T39	3		T228	12		T163	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T4	12		T24	13		T27	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T12	3		T36	5		T135	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T33	2		T35	16		T146	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2