Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T10	10		T139	1		T12	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T67	14		T106	1		T135	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	20		T4	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T38	2		T39	9		T172	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T110	1		T154	1		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	1		T246	1		T221	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T110	1		T106	2		T180	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	1		T103	1		T181	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	1		T37	7		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T26	1		T36	8		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T5	6		T11	15		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T33	3		T101	1		T136	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T26	1		T28	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T8	12		T110	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	1		T6	5		T9	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	2		T162	1		T32	20
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T7	7		T24	14		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T3	1		T10	15		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T248	6		T249	1		T250	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T22	5		T142	1		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19772	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T251	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	5		T38	11		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T106	16		T135	8		T173	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1208	1			T4	12		T34	43		T43	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	3		T16	2		T260	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T154	12		T261	10		T237	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T221	10		T185	30		T262	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T106	26		T180	10		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T35	16		T103	15		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T37	1		T15	2		T16	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T36	5		T50	16		T142	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T5	5		T11	15		T27	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T33	2		T136	14		T263	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	12		T146	7		T222	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	5		T27	11		T133	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T6	2		T9	1		T14	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T162	9		T32	22		T227	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T24	13		T36	2		T144	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T35	16		T12	3		T103	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T250	2		T254	6		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T142	11		T218	8		T234	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T251	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T244	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T137	1		T245	5		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T79	11		T244	13		T30	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T139	1		T26	1		T101	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T67	14		T39	9		T135	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1325	1			T1	20		T10	10		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T106	1		T143	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T4	1		T110	1		T180	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	1		T38	2		T172	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T110	1		T106	1		T145	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T35	1		T103	1		T50	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T37	7		T106	1		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T38	1		T31	1		T256	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T6	1		T16	8		T138	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T33	3		T26	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	6		T11	15		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T8	12		T133	9		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	1		T6	5		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	1		T9	2		T110	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T7	7		T139	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	343	1			T10	15		T35	1		T139	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T255	11		T264	8		T257	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T79	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T38	11		T157	2		T224	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T39	3		T135	8		T173	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T34	43		T43	15		T108	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T106	16		T260	12		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	12		T180	10		T183	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T16	2		T185	15		T262	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T106	13		T148	1		T187	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T35	16		T103	15		T50	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	1		T106	13		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T260	18		T221	8		T219	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T16	8		T138	2		T163	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T33	2		T27	11		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	5		T11	15		T27	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T8	5		T133	8		T135	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	2		T9	1		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T32	6		T163	6		T227	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T24	13		T36	2		T144	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T35	16		T12	3		T103	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2