Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25558

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3362

1

T3

2

T4

13

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22781

1

T2

15

T3

1

T4

13

auto[1]

6139

1

T1

20

T3

2

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	37	1			T149	6		T238	11		T265	3
values[0]	78	1			T4	13		T27	12		T156	1
values[1]	672	1			T139	1		T133	17		T37	2
values[2]	688	1			T9	2		T106	14		T180	24
values[3]	830	1			T110	1		T28	1		T103	8
values[4]	521	1			T139	1		T22	5		T101	1
values[5]	2592	1			T1	20		T6	1		T34	46
values[6]	729	1			T7	7		T8	17		T11	30
values[7]	729	1			T9	4		T35	34		T12	18
values[8]	801	1			T3	3		T10	10		T67	14
values[9]	1479	1			T5	11		T6	7		T10	15
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	855	1			T4	13		T139	1		T27	12
values[1]	760	1			T9	2		T28	1		T103	8
values[2]	698	1			T110	1		T22	5		T105	15
values[3]	2780	1			T1	20		T6	1		T34	46
values[4]	499	1			T7	7		T8	17		T110	1
values[5]	703	1			T11	30		T35	17		T12	18
values[6]	735	1			T3	1		T9	4		T35	17
values[7]	760	1			T3	2		T10	10		T110	1
values[8]	1084	1			T5	11		T10	15		T33	5
values[9]	236	1			T6	7		T151	1		T38	3
minimum	19810	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T27	12		T133	9		T37	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T4	13		T139	1		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T103	8		T106	14		T243	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T9	1		T28	1		T32	37
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T22	1		T180	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T110	1		T105	1		T172	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	2		T6	1		T34	46
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T139	1		T38	1		T243	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T8	6		T110	1		T12	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T7	1		T36	8		T163	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T11	16		T35	17		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	9		T13	1		T24	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T35	17		T67	1		T106	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	1		T9	4		T106	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	1		T110	1		T27	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	1		T10	1		T140	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T135	9		T142	12		T229	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	6		T10	1		T33	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T6	6		T151	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T153	5		T222	7		T266	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19639	1			T2	15		T6	31		T9	81
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T133	8		T181	10		T164	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T136	14		T226	13		T221	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T138	3		T267	1		T188	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T32	31		T221	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T22	4		T180	10		T222	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T105	14		T172	23		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T1	18		T107	21		T109	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T146	7		T222	13		T239	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	11		T173	1		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T7	6		T36	5		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T11	14		T180	12		T268	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	9		T24	13		T144	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T67	13		T221	13		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T15	1		T223	1		T166	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T37	4		T180	14		T172	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	9		T140	10		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T229	14		T146	10		T145	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	5		T10	14		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T6	1		T38	2		T238	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T153	12		T222	6		T238	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	2		T33	1		T67	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T238	9		T265	2		T269	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T149	4		T270	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T27	12		T156	1		T271	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T4	13		T272	9		T273	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T133	9		T37	2		T164	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	1		T141	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T106	14		T180	14		T181	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	1		T136	15		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T103	8		T141	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T110	1		T28	1		T105	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T22	1		T101	1		T137	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T139	1		T38	1		T172	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1473	1			T1	2		T6	1		T34	46
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T222	1		T98	6		T274	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T8	6		T11	16		T180	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	1		T13	1		T24	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T35	34		T26	1		T37	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T9	4		T12	9		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	1		T67	1		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	2		T10	1		T14	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T6	6		T151	1		T38	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	405	1			T5	6		T10	1		T33	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T238	2		T265	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T149	2		T270	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T272	9		T275	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T133	8		T164	3		T173	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T226	13		T221	7		T157	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T180	10		T181	10		T138	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	1		T136	14		T150	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T222	1		T150	1		T174	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T105	14		T172	15		T32	31
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T22	4		T148	2		T149	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T172	8		T146	7		T239	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	899	1			T1	18		T107	21		T109	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T222	13		T98	4		T274	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	11		T11	14		T180	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	6		T24	13		T36	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T37	4		T221	13		T165	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T12	9		T50	17		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T67	13		T180	14		T172	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T10	9		T14	7		T38	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	325	1			T6	1		T38	2		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T5	5		T10	14		T140	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T27	1		T133	9		T37	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T4	1		T139	1		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T103	1		T106	1		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T9	2		T28	1		T32	34
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T22	5		T180	11		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T110	1		T105	15		T172	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1232	1			T1	20		T6	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T139	1		T38	1		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	12		T110	1		T12	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	7		T36	8		T163	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	15		T35	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	13		T13	1		T24	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T35	1		T67	14		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	1		T9	3		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	1		T110	1		T27	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T10	10		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	340	1			T135	1		T142	1		T229	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T5	6		T10	15		T33	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T6	5		T151	1		T38	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T153	13		T222	7		T266	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19788	1			T2	15		T6	31		T9	83
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T27	11		T133	8		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T4	12		T136	14		T263	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T103	7		T106	13		T243	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T32	34		T221	8		T228	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T180	13		T174	8		T227	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T144	4		T185	3		T261	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1207	1			T34	43		T43	15		T108	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T243	8		T146	7		T260	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	5		T12	3		T173	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T36	5		T163	12		T98	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	15		T35	16		T180	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	5		T24	13		T228	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T35	16		T106	16		T221	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	1		T106	13		T162	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T27	7		T37	1		T180	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	6		T14	7		T38	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T135	8		T142	11		T229	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	5		T33	2		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T6	2		T238	8		T232	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T153	4		T222	6		T266	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T251	12		T276	10		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T238	3		T265	3		T269	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T149	3		T270	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T27	1		T156	1		T271	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T4	1		T272	10		T273	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T133	9		T37	2		T164	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T139	1		T141	1		T246	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T106	1		T180	11		T181	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	2		T136	15		T16	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T103	1		T141	1		T246	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T110	1		T28	1		T105	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T22	5		T101	1		T137	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T139	1		T38	1		T172	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T1	20		T6	1		T34	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T222	14		T98	6		T274	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T8	12		T11	15		T180	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	7		T13	1		T24	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T35	2		T26	1		T37	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	3		T12	13		T26	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T3	1		T67	14		T110	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T3	2		T10	10		T14	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	396	1			T6	5		T151	1		T38	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	439	1			T5	6		T10	15		T33	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T238	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T149	3		T270	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T27	11		T271	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T4	12		T272	8		T273	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T133	8		T164	3		T260	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T263	9		T221	10		T219	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T106	13		T180	13		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T136	14		T242	11		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T103	7		T174	8		T227	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T32	34		T144	4		T221	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T148	2		T149	3		T157	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T243	8		T146	7		T260	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1154	1			T34	43		T43	15		T108	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T98	4		T274	8		T277	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	5		T11	15		T180	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T24	13		T36	5		T106	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	32		T37	1		T221	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T9	1		T12	5		T50	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T27	7		T106	16		T180	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T14	7		T38	11		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T6	2		T135	8		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T5	5		T33	2		T140	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2