Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25201

1

T1

20

T2

15

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3719

1

T3

1

T6

8

T7

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22729

1

T2

15

T3

2

T4

13

auto[1]

6191

1

T1

20

T3

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	59	1			T164	26		T166	13		T278	10
values[0]	57	1			T5	11		T31	3		T243	13
values[1]	719	1			T6	1		T8	17		T9	2
values[2]	609	1			T3	1		T11	30		T110	1
values[3]	605	1			T139	1		T28	1		T36	13
values[4]	700	1			T10	15		T139	1		T110	1
values[5]	816	1			T4	13		T10	10		T35	17
values[6]	804	1			T3	1		T14	16		T136	29
values[7]	710	1			T110	1		T13	1		T133	17
values[8]	2936	1			T1	20		T9	4		T34	46
values[9]	1141	1			T3	1		T6	7		T7	7
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	906	1			T5	11		T6	1		T8	17
values[1]	519	1			T3	1		T35	17		T110	1
values[2]	683	1			T139	1		T36	13		T39	12
values[3]	800	1			T10	25		T110	1		T180	24
values[4]	690	1			T4	13		T35	17		T139	2
values[5]	830	1			T3	1		T13	1		T27	12
values[6]	2936	1			T1	20		T34	46		T86	3
values[7]	779	1			T3	1		T9	4		T22	5
values[8]	788	1			T6	7		T33	5		T67	14
values[9]	192	1			T7	7		T36	5		T38	3
minimum	19797	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T5	6		T8	6		T9	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T6	1		T103	8		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T3	1		T35	17		T106	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T110	1		T28	1		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T36	8		T180	12		T142	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T139	1		T39	9		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T110	1		T180	14		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T10	2		T145	1		T163	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	13		T139	2		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T35	17		T105	1		T38	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	1		T136	15		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T3	1		T27	12		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T1	2		T34	46		T86	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T133	9		T37	6		T172	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T3	1		T9	4		T22	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T24	14		T26	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	5		T67	1		T12	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T6	6		T27	8		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T36	3		T38	1		T147	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T7	1		T173	2		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19632	1			T2	15		T6	31		T9	81
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T5	5		T8	11		T9	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T38	1		T172	8		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T15	3		T146	7		T222	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T15	1		T149	2		T157	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T36	5		T180	14		T79	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T39	3		T16	6		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T180	10		T172	16		T221	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T10	23		T145	13		T227	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T229	14		T173	8		T221	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T105	14		T38	12		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T136	14		T181	10		T138	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T14	7		T15	1		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	977	1			T1	18		T107	21		T109	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T133	8		T37	4		T172	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T22	4		T140	10		T144	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T24	13		T32	26		T226	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T67	13		T16	3		T144	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	1		T180	12		T164	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T36	2		T38	2		T147	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T7	6		T173	1		T278	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	2		T33	1		T67	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T166	1		T279	1		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T164	13		T278	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T5	6		T31	1		T243	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T264	16		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T8	6		T9	1		T35	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T6	1		T103	8		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T11	16		T12	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T110	1		T106	14		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T36	8		T180	12		T146	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T139	1		T28	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T139	1		T110	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	1		T39	9		T183	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T4	13		T139	1		T180	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T10	1		T35	17		T27	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T136	15		T229	12		T281	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	1		T14	9		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T110	1		T13	1		T50	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T133	9		T37	2		T172	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T1	2		T9	4		T34	46
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T24	14		T37	4		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	1		T33	5		T67	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	371	1			T6	6		T7	1		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T166	12		T279	3		T280	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T164	13		T278	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T5	5		T31	2		T282	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T264	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	11		T9	1		T239	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T38	1		T228	10		T174	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	14		T12	9		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T172	8		T15	1		T157	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T36	5		T180	14		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T149	2		T231	11		T265	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T172	16		T221	7		T150	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T10	14		T39	3		T16	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T180	10		T173	8		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	9		T105	14		T38	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T136	14		T229	14		T138	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T14	7		T164	3		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T50	17		T181	10		T219	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T133	8		T172	15		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	980	1			T1	18		T107	21		T109	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T24	13		T37	4		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T67	13		T140	10		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T6	1		T7	6		T180	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	6		T8	12		T9	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	1		T103	1		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T3	1		T35	1		T106	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T110	1		T28	1		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T36	8		T180	15		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T139	1		T39	9		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T110	1		T180	11		T172	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T10	25		T145	14		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	1		T139	2		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T35	1		T105	15		T38	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	1		T136	15		T181	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	1		T27	1		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T1	20		T34	3		T86	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T133	9		T37	9		T172	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	1		T9	3		T22	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T24	14		T26	1		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T33	3		T67	14		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T6	5		T27	1		T135	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T36	3		T38	3		T147	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T7	7		T173	2		T238	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19783	1			T2	15		T6	31		T9	83
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T5	5		T8	5		T11	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T103	7		T228	12		T174	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	16		T106	13		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T106	13		T142	11		T149	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T36	5		T180	11		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T39	3		T183	9		T16	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T180	13		T221	8		T148	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T163	6		T227	7		T266	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	12		T229	11		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T35	16		T38	11		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T136	14		T138	2		T260	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	11		T14	7		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T34	43		T43	15		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T133	8		T37	1		T146	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T9	1		T140	6		T187	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T24	13		T32	28		T163	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T33	2		T12	3		T16	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T6	2		T27	7		T135	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T36	2		T147	11		T274	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T173	1		T283	10		T284	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T285	1		T286	12		T282	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T166	13		T279	4		T280	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T164	14		T278	10		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T5	6		T31	3		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T264	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T8	12		T9	2		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	1		T103	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	1		T11	15		T12	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T110	1		T106	1		T172	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T36	8		T180	15		T146	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T139	1		T28	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T139	1		T110	1		T172	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T10	15		T39	9		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T4	1		T139	1		T180	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	10		T35	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T136	15		T229	15		T281	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	1		T14	9		T164	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T110	1		T13	1		T50	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	9		T37	2		T172	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1303	1			T1	20		T9	3		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T24	14		T37	7		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T3	1		T33	3		T67	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T6	5		T7	7		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T164	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T5	5		T243	12		T282	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T264	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	5		T35	16		T103	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T103	7		T228	12		T174	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T11	15		T12	5		T106	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T106	13		T142	11		T157	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T36	5		T180	11		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T149	3		T231	11		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T142	11		T221	10		T79	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T39	3		T183	9		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T4	12		T180	13		T221	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T35	16		T27	11		T38	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T136	14		T229	11		T138	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	7		T164	3		T153	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T50	16		T260	12		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T133	8		T15	2		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1226	1			T9	1		T34	43		T43	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T24	13		T37	1		T32	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T33	2		T12	3		T140	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T6	2		T27	7		T135	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2