Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25245

1

T1

20

T2

15

T3

2

auto[ADC_CTRL_FILTER_COND_OUT]

3675

1

T3

1

T6

8

T7

7

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22754

1

T2

15

T3

2

T4

13

auto[1]

6166

1

T1

20

T3

1

T6

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	237	1			T26	1		T222	2		T150	2
values[0]	16	1			T243	13		T282	3		-	-
values[1]	750	1			T5	11		T6	1		T8	17
values[2]	572	1			T3	1		T11	30		T35	17
values[3]	521	1			T28	1		T36	13		T31	1
values[4]	850	1			T10	25		T139	1		T110	1
values[5]	790	1			T4	13		T35	17		T139	2
values[6]	817	1			T3	1		T13	1		T27	12
values[7]	690	1			T110	1		T133	17		T37	2
values[8]	2938	1			T1	20		T9	4		T34	46
values[9]	975	1			T3	1		T6	7		T7	7
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	700	1			T5	11		T6	1		T9	2
values[1]	572	1			T3	1		T11	30		T35	17
values[2]	668	1			T139	1		T36	13		T39	12
values[3]	789	1			T10	25		T110	1		T180	24
values[4]	643	1			T4	13		T35	17		T139	2
values[5]	851	1			T3	1		T13	1		T27	12
values[6]	3008	1			T1	20		T34	46		T86	3
values[7]	723	1			T6	7		T9	4		T22	5
values[8]	808	1			T3	1		T7	7		T33	5
values[9]	177	1			T26	1		T147	21		T150	2
minimum	19981	1			T2	15		T6	31		T8	17

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	6		T9	1		T12	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	1		T103	8		T172	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T11	16		T35	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T110	1		T28	1		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T36	8		T180	12		T142	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T139	1		T39	9		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	1		T110	1		T180	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T10	1		T145	1		T163	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T4	13		T139	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T35	17		T139	1		T105	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T13	1		T136	15		T229	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T27	12		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1566	1			T1	2		T34	46		T86	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T133	9		T37	6		T32	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	4		T22	1		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	6		T24	14		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T33	5		T67	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T7	1		T27	8		T135	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T26	1		T147	12		T274	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T150	1		T238	1		T278	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19711	1			T2	15		T6	31		T8	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T38	1		T287	11		T100	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T5	5		T9	1		T12	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T172	8		T228	10		T174	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T11	14		T15	3		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T15	1		T149	2		T157	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	5		T180	14		T79	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T39	3		T16	6		T149	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T10	14		T180	10		T172	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	9		T145	13		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T138	3		T173	8		T221	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T105	14		T38	12		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T136	14		T229	14		T274	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T14	7		T15	1		T153	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1001	1			T1	18		T107	21		T109	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T133	8		T37	4		T32	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T22	4		T140	10		T16	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T6	1		T24	13		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T67	13		T36	2		T38	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	6		T180	12		T173	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T147	9		T274	8		T288	24
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T150	1		T278	9		T284	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T8	11		T9	2		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T38	1		T287	9		T100	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T26	1		T222	1		T218	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T150	1		T223	1		T232	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T243	13		T282	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T5	6		T8	6		T9	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T6	1		T103	8		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T11	16		T35	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T110	1		T106	14		T172	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	8		T180	12		T146	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T28	1		T31	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	1		T110	1		T172	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T10	1		T139	1		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	13		T139	1		T180	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T35	17		T139	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T136	15		T229	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	1		T27	12		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T110	1		T50	17		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T133	9		T37	2		T15	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T1	2		T9	4		T34	46
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T24	14		T37	4		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T3	1		T33	5		T67	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T6	6		T7	1		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T222	1		T218	4		T166	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T150	1		T223	1		T232	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T282	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	5		T8	11		T9	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T38	1		T228	10		T174	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	14		T12	9		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T172	8		T15	1		T241	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T36	5		T180	14		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T149	2		T157	3		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	14		T172	16		T150	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	9		T39	3		T16	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T180	10		T173	8		T221	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T105	14		T38	12		T32	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T136	14		T229	14		T138	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	7		T164	3		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T50	17		T181	10		T219	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T133	8		T15	1		T32	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T1	18		T107	21		T109	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T24	13		T37	4		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T67	13		T36	2		T38	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	1		T7	6		T180	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T5	6		T9	2		T12	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T6	1		T103	1		T172	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	1		T11	15		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T110	1		T28	1		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T36	8		T180	15		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	1		T39	9		T31	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T10	15		T110	1		T180	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T10	10		T145	14		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T139	1		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T35	1		T139	1		T105	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T136	15		T229	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T27	1		T14	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T1	20		T34	3		T86	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T133	9		T37	9		T32	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T9	3		T22	5		T26	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	5		T24	14		T26	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	1		T33	3		T67	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T7	7		T27	1		T135	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T26	1		T147	10		T274	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T150	2		T238	1		T278	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19847	1			T2	15		T6	31		T8	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T38	2		T287	10		T100	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T5	5		T12	5		T103	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T103	7		T228	12		T174	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	15		T35	16		T106	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T106	13		T142	11		T149	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T36	5		T180	11		T142	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	3		T183	9		T16	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T180	13		T221	8		T148	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T163	6		T266	13		T218	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T4	12		T138	2		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T35	16		T38	11		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T136	14		T229	11		T260	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	11		T14	7		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T34	43		T43	15		T108	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T133	8		T37	1		T32	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T9	1		T140	6		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	2		T24	13		T32	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T33	2		T12	3		T36	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	7		T135	12		T180	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T147	11		T274	8		T289	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T283	10		T284	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T8	5		T142	6		T243	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T287	10		T100	2		T290	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T26	1		T222	2		T218	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T150	2		T223	2		T232	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T243	1		T282	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T5	6		T8	12		T9	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	1		T103	1		T38	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	1		T11	15		T35	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T110	1		T106	1		T172	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T36	8		T180	15		T146	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T28	1		T31	1		T246	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	15		T110	1		T172	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T10	10		T139	1		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	1		T139	1		T180	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T35	1		T139	1		T105	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	1		T136	15		T229	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	1		T27	1		T14	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T110	1		T50	18		T181	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T133	9		T37	2		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T1	20		T9	3		T34	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T24	14		T37	7		T16	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	1		T33	3		T67	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	5		T7	7		T26	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T274	8		T291	8		T289	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T232	8		T283	10		T292	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T243	12		T282	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	5		T8	5		T103	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T103	7		T228	12		T174	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T11	15		T35	16		T12	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T106	13		T142	11		T241	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T36	5		T180	11		T146	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T149	3		T157	9		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T142	11		T227	7		T241	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T39	3		T183	9		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T4	12		T180	13		T221	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T35	16		T38	11		T32	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T136	14		T229	11		T138	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T27	11		T14	7		T164	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T50	16		T260	12		T219	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T133	8		T15	2		T32	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T9	1		T34	43		T43	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T24	13		T37	1		T32	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T33	2		T12	3		T36	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T6	2		T27	7		T135	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2