Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25385

1

T1

20

T2

15

T6

39

auto[ADC_CTRL_FILTER_COND_OUT]

3535

1

T3

3

T4

13

T5

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22829

1

T2

15

T3

3

T5

11

auto[1]

6091

1

T1

20

T4

13

T6

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	17	1			T28	1		T248	9		T293	3
values[0]	139	1			T173	10		T294	1		T184	11
values[1]	728	1			T3	1		T5	11		T9	2
values[2]	811	1			T3	1		T35	17		T26	1
values[3]	704	1			T67	14		T103	16		T281	1
values[4]	2883	1			T1	20		T7	7		T9	4
values[5]	659	1			T11	30		T38	3		T106	17
values[6]	616	1			T10	15		T105	15		T106	14
values[7]	634	1			T6	7		T8	17		T12	18
values[8]	566	1			T4	13		T6	1		T110	1
values[9]	1399	1			T3	1		T33	5		T35	17
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1035	1			T5	11		T9	2		T139	1
values[1]	721	1			T3	2		T35	17		T26	1
values[2]	876	1			T10	10		T67	14		T103	16
values[3]	2745	1			T1	20		T7	7		T9	4
values[4]	577	1			T11	30		T14	16		T38	3
values[5]	675	1			T105	15		T135	5		T180	26
values[6]	679	1			T6	7		T8	17		T10	15
values[7]	622	1			T4	13		T6	1		T110	2
values[8]	974	1			T33	5		T35	17		T139	2
values[9]	218	1			T3	1		T28	1		T180	23
minimum	19798	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T151	1		T133	9		T37	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T5	6		T9	1		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T35	17		T137	1		T260	19
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	2		T26	1		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T10	1		T67	1		T106	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T103	16		T38	13		T142	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T1	2		T9	4		T34	46
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T7	1		T110	1		T27	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	16		T38	1		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T14	9		T180	14		T183	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T135	5		T162	10		T16	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T105	1		T180	12		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	6		T8	6		T12	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	1		T24	14		T103	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T110	2		T12	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T4	13		T13	1		T27	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T140	7		T101	1		T135	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T33	5		T35	17		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T28	1		T294	1		T295	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T3	1		T180	11		T239	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19622	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T138	3		T296	17		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T133	8		T37	4		T16	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	5		T9	1		T36	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T221	7		T155	4		T227	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T136	14		T229	14		T32	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T10	9		T67	13		T31	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T38	12		T228	12		T218	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	969	1			T1	18		T107	21		T109	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T7	6		T166	10		T185	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	14		T38	2		T172	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T14	7		T180	10		T172	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T16	6		T144	3		T221	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T105	14		T180	14		T173	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	1		T8	11		T12	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T10	14		T24	13		T50	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T36	5		T39	3		T172	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T222	6		T155	10		T187	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T140	10		T32	13		T164	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T38	1		T181	10		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T168	11		T297	13		T298	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T180	12		T239	12		T237	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T138	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T28	1		T248	1		T293	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T274	11		T186	3		T299	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T173	2		T294	1		T184	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T151	1		T133	9		T37	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	1		T5	6		T9	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T35	17		T37	2		T31	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T3	1		T26	1		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T67	1		T221	11		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T103	16		T281	1		T260	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1609	1			T1	2		T9	4		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T7	1		T110	1		T27	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	16		T38	1		T106	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T180	14		T183	10		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T31	1		T135	5		T172	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T10	1		T105	1		T106	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	6		T8	6		T12	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T103	8		T180	12		T246	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	1		T110	1		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	13		T13	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	381	1			T110	1		T12	4		T140	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	441	1			T3	1		T33	5		T35	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T248	8		T300	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T274	5		T186	5		T299	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T173	8		T184	10		T165	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T133	8		T37	4		T226	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T5	5		T9	1		T15	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T31	2		T16	3		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T36	2		T38	12		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T67	13		T221	7		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T241	1		T218	4		T301	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1027	1			T1	18		T10	9		T107	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T7	6		T14	7		T218	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	14		T38	2		T147	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T180	10		T172	15		T166	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T172	16		T16	6		T144	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T10	14		T105	14		T173	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T6	1		T8	11		T12	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T180	14		T187	11		T239	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T39	3		T172	8		T228	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T24	13		T50	17		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T140	10		T36	5		T32	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T38	1		T180	12		T181	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T151	1		T133	9		T37	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T5	6		T9	2		T139	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	1		T137	1		T260	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	2		T26	1		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T10	10		T67	14		T106	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T103	1		T38	14		T142	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1296	1			T1	20		T9	3		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T7	7		T110	1		T27	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	15		T38	3		T31	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T14	9		T180	11		T183	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T135	1		T162	1		T16	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T105	15		T180	15		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	5		T8	12		T12	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T10	15		T24	14		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	1		T110	2		T12	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	1		T13	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T140	11		T101	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T33	3		T35	1		T139	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T28	1		T294	1		T295	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T3	1		T180	13		T239	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19773	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T138	4		T296	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T133	8		T37	1		T16	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	5		T36	2		T15	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T35	16		T260	18		T221	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T136	14		T229	11		T32	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T106	13		T148	3		T149	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T103	15		T38	11		T142	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T9	1		T34	43		T43	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T27	7		T185	3		T273	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	15		T147	11		T174	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T14	7		T180	13		T183	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T135	4		T162	9		T16	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T180	11		T173	1		T263	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T6	2		T8	5		T12	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T24	13		T103	7		T106	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T12	3		T36	5		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	12		T27	11		T222	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T140	6		T135	8		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T33	2		T35	16		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T295	9		T168	8		T302	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T180	10		T239	15		T237	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T20	2		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T138	2		T296	16		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T28	1		T248	9		T293	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T274	6		T186	6		T299	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T173	10		T294	1		T184	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T151	1		T133	9		T37	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	1		T5	6		T9	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	1		T37	2		T31	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	1		T26	1		T36	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T67	14		T221	8		T148	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T103	1		T281	1		T260	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	20		T9	3		T10	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T7	7		T110	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	15		T38	3		T106	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T180	11		T183	1		T172	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T31	1		T135	1		T172	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	15		T105	15		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T6	5		T8	12		T12	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T103	1		T180	15		T246	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	1		T110	1		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T4	1		T13	1		T24	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T110	1		T12	1		T140	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T3	1		T33	3		T35	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T293	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T274	10		T186	2		T299	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T165	6		T303	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T133	8		T37	1		T221	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T5	5		T15	2		T138	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	16		T16	2		T243	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T36	2		T38	11		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T221	10		T148	1		T149	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T103	15		T260	12		T154	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1271	1			T9	1		T34	43		T43	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T27	7		T14	7		T218	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	15		T106	16		T147	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T180	13		T183	9		T285	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T135	4		T162	9		T16	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T106	13		T142	11		T173	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	2		T8	5		T12	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T103	7		T180	11		T239	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T39	3		T228	12		T163	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T4	12		T24	13		T27	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	295	1			T12	3		T140	6		T36	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T33	2		T35	16		T180	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2