Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23522

1

T2

15

T3

1

T6

31

auto[ADC_CTRL_FILTER_COND_OUT]

5398

1

T1

20

T3

2

T4

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22578

1

T2

15

T3

2

T4

13

auto[1]

6342

1

T1

20

T3

1

T5

11

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T304	12		T305	13		T306	1
values[0]	49	1			T16	1		T148	4		T220	1
values[1]	719	1			T110	1		T12	4		T26	1
values[2]	562	1			T3	1		T5	11		T9	4
values[3]	825	1			T3	1		T4	13		T139	1
values[4]	693	1			T33	5		T35	17		T67	14
values[5]	634	1			T7	7		T35	17		T139	1
values[6]	652	1			T3	1		T139	1		T103	8
values[7]	682	1			T6	8		T110	1		T27	8
values[8]	660	1			T10	10		T27	12		T133	17
values[9]	3653	1			T1	20		T8	17		T9	2
minimum	19764	1			T2	15		T6	31		T9	83

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	897	1			T110	1		T12	4		T22	5
values[1]	2785	1			T1	20		T3	2		T5	11
values[2]	762	1			T4	13		T13	1		T14	16
values[3]	695	1			T33	5		T35	17		T67	14
values[4]	695	1			T3	1		T7	7		T35	17
values[5]	668	1			T6	7		T139	1		T103	8
values[6]	666	1			T6	1		T10	10		T110	1
values[7]	644	1			T10	15		T27	20		T133	17
values[8]	1041	1			T9	2		T11	30		T12	18
values[9]	270	1			T8	17		T28	1		T181	11
minimum	19797	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T110	1		T12	4		T22	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T26	1		T136	15		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T9	4		T38	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1540	1			T1	2		T3	1		T5	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T14	9		T38	14		T106	31
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T4	13		T13	1		T180	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T33	5		T139	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T35	17		T67	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T35	17		T139	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	1		T7	1		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T142	12		T221	14		T148	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T6	6		T139	1		T103	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T140	7		T101	1		T106	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T6	1		T10	1		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T133	9		T36	8		T50	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	1		T27	20		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	16		T12	9		T24	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	1		T31	1		T183	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	6		T28	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T231	1		T237	15		T307	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19617	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T176	15		T18	3		T308	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T22	4		T148	2		T149	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T136	14		T164	3		T228	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T38	1		T231	4		T193	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	986	1			T1	18		T5	5		T107	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T14	7		T38	14		T16	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T180	12		T144	3		T150	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T105	14		T180	10		T172	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T67	13		T39	3		T180	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T16	3		T138	3		T164	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T7	6		T228	12		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T221	13		T148	2		T239	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	1		T15	1		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T140	10		T226	13		T227	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T10	9		T157	3		T188	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T133	8		T36	5		T50	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T10	14		T36	2		T172	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	14		T12	9		T24	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T31	2		T173	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	11		T181	10		T221	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T231	1		T237	13		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T18	1		T308	1		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T304	1		T305	1		T306	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T307	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T16	1		T148	2		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T224	2		T308	1		T309	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T110	1		T12	4		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T26	1		T152	1		T164	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T9	4		T22	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	6		T37	4		T135	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T139	1		T14	9		T38	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	1		T4	13		T180	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T33	5		T105	1		T38	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T35	17		T67	1		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T35	17		T139	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	1		T26	1		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T221	14		T239	11		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	1		T139	1		T103	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T140	7		T101	1		T106	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	7		T110	1		T27	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T133	9		T36	8		T15	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	1		T27	12		T103	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T8	6		T11	16		T12	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1710	1			T1	2		T9	1		T10	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19615	1			T2	15		T6	31		T9	81
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T304	11		T305	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T148	2		T310	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T224	3		T308	1		T93	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T149	11		T155	10		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T164	3		T174	5		T241	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T22	4		T285	1		T177	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T5	5		T37	4		T136	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	7		T38	3		T16	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T180	12		T144	3		T150	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T105	14		T38	12		T180	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T67	13		T39	3		T180	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T172	15		T16	3		T138	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T7	6		T146	10		T228	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T221	13		T239	8		T277	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T15	1		T222	1		T155	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T140	10		T226	13		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	1		T221	7		T150	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T133	8		T36	5		T15	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T10	9		T15	1		T268	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	421	1			T8	11		T11	14		T12	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1108	1			T1	18		T9	1		T10	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T110	1		T12	1		T22	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T26	1		T136	15		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T9	3		T38	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1310	1			T1	20		T3	1		T5	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T14	9		T38	17		T106	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T4	1		T13	1		T180	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T33	3		T139	1		T105	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T35	1		T67	14		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T35	1		T139	1		T110	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T7	7		T26	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T142	1		T221	14		T148	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	5		T139	1		T103	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T140	11		T101	1		T106	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T6	1		T10	10		T110	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T133	9		T36	8		T50	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	15		T27	2		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T11	15		T12	13		T24	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T9	2		T31	3		T183	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	12		T28	1		T181	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T231	2		T237	14		T307	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19776	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T176	1		T18	3		T308	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T12	3		T148	1		T163	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T136	14		T164	3		T228	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	1		T135	8		T231	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1216	1			T5	5		T34	43		T43	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T14	7		T38	11		T106	29
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	12		T180	10		T144	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T33	2		T180	13		T263	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T35	16		T39	3		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T35	16		T16	2		T243	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T142	6		T228	17		T238	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T142	11		T221	13		T148	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T6	2		T103	7		T15	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T140	6		T106	13		T311	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T103	15		T157	2		T188	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T133	8		T36	5		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T27	18		T36	2		T266	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	15		T12	5		T24	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T183	9		T142	11		T147	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T8	5		T221	8		T202	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T237	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T176	14		T18	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T304	12		T305	13		T306	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T307	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T16	1		T148	3		T220	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T224	4		T308	2		T309	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T110	1		T12	1		T31	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T26	1		T152	1		T164	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	1		T9	3		T22	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	6		T37	7		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T139	1		T14	9		T38	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	1		T4	1		T180	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T33	3		T105	15		T38	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T35	1		T67	14		T13	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T35	1		T139	1		T110	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T7	7		T26	1		T37	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T221	14		T239	9		T294	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	1		T139	1		T103	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T140	11		T101	1		T106	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	6		T110	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T133	9		T36	8		T15	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	10		T27	1		T103	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	493	1			T8	12		T11	15		T12	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1473	1			T1	20		T9	2		T10	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19764	1			T2	15		T6	31		T9	83
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T148	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T224	1		T93	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	3		T149	3		T239	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T164	3		T174	8		T176	22
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T9	1		T135	8		T163	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	5		T37	1		T135	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T14	7		T106	29		T162	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T4	12		T180	10		T243	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T33	2		T38	11		T180	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	16		T39	3		T180	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T35	16		T16	2		T243	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T146	8		T228	17		T154	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T221	13		T239	10		T277	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T103	7		T15	2		T238	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T140	6		T106	13		T142	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	2		T27	7		T221	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T133	8		T36	5		T32	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T27	11		T103	15		T266	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	342	1			T8	5		T11	15		T12	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1345	1			T34	43		T43	15		T108	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2