Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28920

1

T1

20

T2

15

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

25135

1

T1

20

T2

15

T3

1

auto[ADC_CTRL_FILTER_COND_OUT]

3785

1

T3

2

T5

11

T6

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22676

1

T2

15

T3

2

T6

29

auto[1]

6244

1

T1

20

T3

1

T4

13

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24903

1

T1

2

T2

15

T3

3

auto[1]

4017

1

T1

18

T5

5

T6

1

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	505	1			T6	9		T9	6		T45	1
values[0]	113	1			T78	1		T79	14		T272	18
values[1]	785	1			T3	1		T110	1		T26	1
values[2]	3249	1			T1	20		T3	1		T6	7
values[3]	753	1			T4	13		T6	1		T12	4
values[4]	653	1			T24	27		T37	2		T135	9
values[5]	533	1			T3	1		T5	11		T9	4
values[6]	717	1			T7	7		T110	2		T36	18
values[7]	670	1			T151	1		T38	1		T31	1
values[8]	648	1			T9	2		T35	17		T12	18
values[9]	1030	1			T10	15		T139	2		T13	1
minimum	19264	1			T2	15		T6	22		T9	77

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1076	1			T3	1		T6	7		T35	17
values[1]	3137	1			T1	20		T3	1		T8	17
values[2]	906	1			T4	13		T6	1		T67	14
values[3]	471	1			T3	1		T5	11		T10	10
values[4]	619	1			T9	4		T11	30		T110	1
values[5]	728	1			T7	7		T110	1		T151	1
values[6]	778	1			T27	8		T36	13		T50	34
values[7]	539	1			T9	2		T10	15		T35	17
values[8]	682	1			T12	18		T13	1		T28	1
values[9]	190	1			T148	1		T239	19		T177	9
minimum	19794	1			T2	15		T6	31		T9	83

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

4228

1

T4

12

T5

5

T6

2

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T6	6		T35	17		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	1		T139	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1567	1			T1	2		T3	1		T34	46
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T8	6		T105	1		T38	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T4	13		T67	1		T12	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T6	1		T24	14		T135	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T32	7		T154	13		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T3	1		T5	6		T10	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	4		T110	1		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	16		T38	13		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T110	1		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T7	1		T36	3		T38	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T137	1		T143	1		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T27	8		T36	8		T50	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T139	2		T22	1		T180	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	1		T10	1		T35	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T12	9		T13	1		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T28	1		T106	14		T180	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T239	11		T270	9		T99	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T148	1		T177	1		T312	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19625	1			T2	15		T6	31		T9	81
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T287	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	1		T172	16		T149	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T133	8		T172	8		T15	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1004	1			T1	18		T107	21		T109	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T8	11		T105	14		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T67	13		T181	10		T15	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T24	13		T180	14		T229	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T32	5		T235	3		T237	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	5		T10	9		T16	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T39	3		T153	12		T218	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	14		T38	12		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T136	14		T150	6		T313	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	6		T36	2		T38	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T148	2		T155	10		T157	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T36	5		T50	17		T144	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T22	4		T180	12		T146	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T9	1		T10	14		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T12	9		T37	4		T173	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T180	10		T79	7		T185	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T239	8		T270	9		T99	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T177	8		T314	6		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T287	9		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	501	1			T6	9		T9	6		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T231	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T272	9		T171	12		T315	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T78	1		T79	8		T287	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T110	1		T103	8		T142	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T3	1		T26	1		T133	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1593	1			T1	2		T3	1		T6	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T8	6		T139	1		T105	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	13		T12	4		T181	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T6	1		T180	12		T229	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T15	1		T256	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T24	14		T37	2		T135	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T9	4		T39	9		T32	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	1		T5	6		T10	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T110	2		T136	15		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T7	1		T36	11		T38	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T151	1		T38	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T31	1		T144	8		T221	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	9		T22	1		T37	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T35	17		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T139	2		T13	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T10	1		T28	1		T140	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19115	1			T2	15		T6	22		T9	75
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T316	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T231	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T272	9		T171	2		T315	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T79	6		T287	9		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T155	4		T218	8		T258	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T133	8		T172	8		T15	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1048	1			T1	18		T6	1		T67	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T8	11		T105	14		T38	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T181	10		T155	11		T187	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T180	14		T229	14		T174	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T15	1		T235	3		T304	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T24	13		T32	13		T164	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T39	3		T32	5		T153	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	5		T10	9		T11	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T136	14		T150	6		T313	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	6		T36	7		T38	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T148	2		T149	11		T157	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T144	4		T221	2		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	9		T22	4		T37	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	1		T50	17		T16	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T173	1		T175	9		T239	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T10	14		T140	10		T14	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T9	2		T33	1		T67	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T6	5		T35	1		T110	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T3	1		T139	1		T26	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1334	1			T1	20		T3	1		T34	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T8	12		T105	15		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T67	14		T12	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	1		T24	14		T135	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T32	6		T154	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	1		T5	6		T10	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	3		T110	1		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	15		T38	14		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T110	1		T151	1		T38	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T7	7		T36	3		T38	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	1		T143	1		T148	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T27	1		T36	8		T50	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T139	2		T22	5		T180	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T9	2		T10	15		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T12	13		T13	1		T37	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T28	1		T106	1		T180	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T239	9		T270	10		T99	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T148	1		T177	9		T312	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19766	1			T2	15		T6	31		T9	83
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T287	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	2		T35	16		T103	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T133	8		T103	15		T162	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1237	1			T34	43		T43	15		T108	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T8	5		T106	16		T142	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	12		T12	3		T135	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T24	13		T135	8		T180	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T32	6		T154	12		T237	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T5	5		T33	2		T16	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	1		T39	3		T153	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T11	15		T38	11		T15	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T136	14		T243	8		T242	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T36	2		T221	10		T148	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T148	2		T154	14		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T27	7		T36	5		T50	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T180	10		T146	8		T149	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	16		T140	6		T14	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	5		T37	1		T173	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T106	13		T180	13		T183	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T239	10		T270	8		T99	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T312	18		T317	15		T318	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T319	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T287	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	503	1			T6	9		T9	6		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T231	2		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T272	10		T171	3		T315	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T78	1		T79	7		T287	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T110	1		T103	1		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	1		T26	1		T133	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1381	1			T1	20		T3	1		T6	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T8	12		T139	1		T105	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T4	1		T12	1		T181	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	1		T180	15		T229	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T15	2		T256	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T24	14		T37	2		T135	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	3		T39	9		T32	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	1		T5	6		T10	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T110	2		T136	15		T150	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T7	7		T36	11		T38	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T151	1		T38	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T31	1		T144	8		T221	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T12	13		T22	5		T37	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T9	2		T35	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T139	2		T13	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	15		T28	1		T140	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	19264	1			T2	15		T6	22		T9	77
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T272	8		T171	11		T315	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T79	7		T287	10		T194	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T103	7		T142	11		T263	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T133	8		T103	15		T162	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T6	2		T34	43		T35	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T8	5		T106	16		T142	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	12		T12	3		T243	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T180	11		T229	11		T260	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T154	12		T237	14		T291	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T24	13		T135	8		T32	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T9	1		T39	3		T32	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T5	5		T11	15		T33	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T136	14		T242	17		T176	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T36	7		T15	2		T221	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T243	8		T148	2		T154	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T144	4		T221	8		T148	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T12	5		T37	1		T180	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T35	16		T27	7		T106	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T173	1		T239	25		T274	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T140	6		T14	7		T106	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

24692

1

T1

20

T2

15

T3

3

auto[1]

auto[0]

4228

1

T4

12

T5

5

T6

2