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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.84 99.07 96.67 100.00 100.00 98.83 98.33 91.96


Total test records in report: 919
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T303 /workspace/coverage/default/30.adc_ctrl_clock_gating.3027856056 Jul 06 06:34:51 PM PDT 24 Jul 06 06:39:46 PM PDT 24 575122496489 ps
T795 /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2761637927 Jul 06 06:32:46 PM PDT 24 Jul 06 06:33:35 PM PDT 24 24343512542 ps
T796 /workspace/coverage/default/20.adc_ctrl_filters_polled.891291924 Jul 06 06:33:14 PM PDT 24 Jul 06 06:50:55 PM PDT 24 484797174828 ps
T797 /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2858136186 Jul 06 06:32:58 PM PDT 24 Jul 06 06:34:38 PM PDT 24 326836991296 ps
T339 /workspace/coverage/default/35.adc_ctrl_clock_gating.3346995602 Jul 06 06:35:42 PM PDT 24 Jul 06 06:41:24 PM PDT 24 160113517687 ps
T798 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3861960788 Jul 06 07:03:07 PM PDT 24 Jul 06 07:03:09 PM PDT 24 347006182 ps
T57 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2123499783 Jul 06 07:02:51 PM PDT 24 Jul 06 07:02:54 PM PDT 24 536714435 ps
T799 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3694040734 Jul 06 07:02:24 PM PDT 24 Jul 06 07:02:26 PM PDT 24 391336883 ps
T54 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1703530037 Jul 06 07:02:40 PM PDT 24 Jul 06 07:02:52 PM PDT 24 4294199431 ps
T51 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2905733135 Jul 06 07:02:44 PM PDT 24 Jul 06 07:02:46 PM PDT 24 488197289 ps
T58 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3080615216 Jul 06 07:02:58 PM PDT 24 Jul 06 07:03:02 PM PDT 24 488820482 ps
T127 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.288184551 Jul 06 07:03:02 PM PDT 24 Jul 06 07:03:03 PM PDT 24 583261836 ps
T800 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.312895059 Jul 06 07:03:07 PM PDT 24 Jul 06 07:03:09 PM PDT 24 382140421 ps
T111 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1015803422 Jul 06 07:02:20 PM PDT 24 Jul 06 07:02:23 PM PDT 24 493224386 ps
T52 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.161458455 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:57 PM PDT 24 4541150259 ps
T65 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2127114522 Jul 06 07:02:44 PM PDT 24 Jul 06 07:02:46 PM PDT 24 495070842 ps
T55 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.101208362 Jul 06 07:02:45 PM PDT 24 Jul 06 07:03:05 PM PDT 24 8143095417 ps
T70 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4247522819 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:24 PM PDT 24 854452172 ps
T801 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1961761638 Jul 06 07:02:58 PM PDT 24 Jul 06 07:03:00 PM PDT 24 340610613 ps
T66 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2749607367 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:55 PM PDT 24 605058293 ps
T802 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.78646158 Jul 06 07:02:33 PM PDT 24 Jul 06 07:02:35 PM PDT 24 347674044 ps
T803 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2124948365 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:06 PM PDT 24 396217180 ps
T112 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.478081981 Jul 06 07:02:53 PM PDT 24 Jul 06 07:02:55 PM PDT 24 445689315 ps
T53 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1367240674 Jul 06 07:02:27 PM PDT 24 Jul 06 07:03:54 PM PDT 24 26582669888 ps
T128 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.184070698 Jul 06 07:02:51 PM PDT 24 Jul 06 07:03:03 PM PDT 24 2688735579 ps
T804 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2358640123 Jul 06 07:02:58 PM PDT 24 Jul 06 07:03:00 PM PDT 24 452888285 ps
T113 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.34848202 Jul 06 07:03:02 PM PDT 24 Jul 06 07:03:04 PM PDT 24 560284405 ps
T805 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1014336744 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:39 PM PDT 24 390517741 ps
T88 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.882450005 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:31 PM PDT 24 547296549 ps
T56 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2467024374 Jul 06 07:02:39 PM PDT 24 Jul 06 07:02:46 PM PDT 24 4445808638 ps
T59 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.143696964 Jul 06 07:02:57 PM PDT 24 Jul 06 07:03:18 PM PDT 24 7946878346 ps
T69 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2385668527 Jul 06 07:02:35 PM PDT 24 Jul 06 07:02:38 PM PDT 24 383883986 ps
T71 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2741755355 Jul 06 07:02:50 PM PDT 24 Jul 06 07:02:55 PM PDT 24 643341097 ps
T132 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1044178384 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:55 PM PDT 24 446397947 ps
T60 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2026672560 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:33 PM PDT 24 4661079257 ps
T72 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3152755741 Jul 06 07:02:52 PM PDT 24 Jul 06 07:03:03 PM PDT 24 7973885303 ps
T806 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4160390076 Jul 06 07:02:40 PM PDT 24 Jul 06 07:02:42 PM PDT 24 504008233 ps
T807 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.109826943 Jul 06 07:02:45 PM PDT 24 Jul 06 07:02:46 PM PDT 24 399125287 ps
T129 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1527195220 Jul 06 07:02:46 PM PDT 24 Jul 06 07:03:07 PM PDT 24 5027705036 ps
T130 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2815119949 Jul 06 07:02:29 PM PDT 24 Jul 06 07:02:38 PM PDT 24 2205664683 ps
T808 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.675837606 Jul 06 07:02:34 PM PDT 24 Jul 06 07:02:36 PM PDT 24 661715520 ps
T809 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1196170195 Jul 06 07:02:56 PM PDT 24 Jul 06 07:02:58 PM PDT 24 360117785 ps
T810 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3438926369 Jul 06 07:02:55 PM PDT 24 Jul 06 07:02:57 PM PDT 24 534689854 ps
T811 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2281549550 Jul 06 07:02:28 PM PDT 24 Jul 06 07:02:31 PM PDT 24 522957014 ps
T812 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1659700210 Jul 06 07:02:39 PM PDT 24 Jul 06 07:02:41 PM PDT 24 680283365 ps
T813 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2353316529 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:41 PM PDT 24 365710654 ps
T814 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3708720646 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:40 PM PDT 24 384161411 ps
T815 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1530086772 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:29 PM PDT 24 606775143 ps
T816 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2995743152 Jul 06 07:02:59 PM PDT 24 Jul 06 07:03:01 PM PDT 24 407348709 ps
T817 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2626586512 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:56 PM PDT 24 570024408 ps
T347 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.76170974 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:39 PM PDT 24 4470091420 ps
T818 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.419151532 Jul 06 07:02:56 PM PDT 24 Jul 06 07:02:58 PM PDT 24 339426436 ps
T819 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1358249741 Jul 06 07:02:35 PM PDT 24 Jul 06 07:02:38 PM PDT 24 512858812 ps
T114 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3019223698 Jul 06 07:02:34 PM PDT 24 Jul 06 07:02:35 PM PDT 24 580678823 ps
T131 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3258483251 Jul 06 07:03:01 PM PDT 24 Jul 06 07:03:21 PM PDT 24 4851273089 ps
T820 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2950983042 Jul 06 07:02:54 PM PDT 24 Jul 06 07:02:56 PM PDT 24 426770170 ps
T821 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3798618866 Jul 06 07:03:05 PM PDT 24 Jul 06 07:03:08 PM PDT 24 393897494 ps
T822 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1859591438 Jul 06 07:02:28 PM PDT 24 Jul 06 07:02:33 PM PDT 24 507404829 ps
T823 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1927741326 Jul 06 07:03:07 PM PDT 24 Jul 06 07:03:09 PM PDT 24 532178568 ps
T824 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4102286432 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:31 PM PDT 24 845952338 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.46895195 Jul 06 07:02:28 PM PDT 24 Jul 06 07:02:34 PM PDT 24 871080408 ps
T825 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2710496774 Jul 06 07:03:00 PM PDT 24 Jul 06 07:03:03 PM PDT 24 597796243 ps
T826 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.344909691 Jul 06 07:03:05 PM PDT 24 Jul 06 07:03:07 PM PDT 24 631112846 ps
T827 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3621114294 Jul 06 07:02:57 PM PDT 24 Jul 06 07:03:10 PM PDT 24 4567210725 ps
T116 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3993047742 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:31 PM PDT 24 1301342254 ps
T828 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4180829782 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:40 PM PDT 24 430186255 ps
T829 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1653686651 Jul 06 07:03:00 PM PDT 24 Jul 06 07:03:03 PM PDT 24 373358350 ps
T830 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1372958969 Jul 06 07:03:02 PM PDT 24 Jul 06 07:03:04 PM PDT 24 682801363 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2120853063 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:28 PM PDT 24 377756719 ps
T831 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4206227190 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:24 PM PDT 24 1187031480 ps
T832 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4001521526 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:07 PM PDT 24 414195738 ps
T833 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2303438933 Jul 06 07:02:28 PM PDT 24 Jul 06 07:02:32 PM PDT 24 554256784 ps
T834 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2680217594 Jul 06 07:02:45 PM PDT 24 Jul 06 07:02:47 PM PDT 24 580072492 ps
T835 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3941709099 Jul 06 07:02:57 PM PDT 24 Jul 06 07:03:00 PM PDT 24 417851459 ps
T836 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2337347117 Jul 06 07:02:41 PM PDT 24 Jul 06 07:02:50 PM PDT 24 2279007183 ps
T837 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2157680101 Jul 06 07:02:36 PM PDT 24 Jul 06 07:02:39 PM PDT 24 1579147536 ps
T838 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2545371277 Jul 06 07:03:00 PM PDT 24 Jul 06 07:03:02 PM PDT 24 333164625 ps
T839 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3319429340 Jul 06 07:02:51 PM PDT 24 Jul 06 07:03:11 PM PDT 24 7803420050 ps
T840 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.976254804 Jul 06 07:03:06 PM PDT 24 Jul 06 07:03:09 PM PDT 24 340965338 ps
T841 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1126129802 Jul 06 07:02:30 PM PDT 24 Jul 06 07:02:37 PM PDT 24 2189629446 ps
T842 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1455375472 Jul 06 07:02:25 PM PDT 24 Jul 06 07:02:28 PM PDT 24 602530299 ps
T843 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2697752963 Jul 06 07:02:24 PM PDT 24 Jul 06 07:02:31 PM PDT 24 4901248236 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1997582752 Jul 06 07:02:33 PM PDT 24 Jul 06 07:02:35 PM PDT 24 773307633 ps
T119 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.416258817 Jul 06 07:02:44 PM PDT 24 Jul 06 07:02:46 PM PDT 24 359020626 ps
T844 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2977328519 Jul 06 07:02:40 PM PDT 24 Jul 06 07:02:45 PM PDT 24 1960871364 ps
T120 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1593695186 Jul 06 07:02:35 PM PDT 24 Jul 06 07:02:38 PM PDT 24 468994639 ps
T845 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1473718103 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:23 PM PDT 24 487927868 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1750971871 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:28 PM PDT 24 761273083 ps
T847 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.184785848 Jul 06 07:02:43 PM PDT 24 Jul 06 07:02:46 PM PDT 24 455501737 ps
T848 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2772059993 Jul 06 07:02:51 PM PDT 24 Jul 06 07:03:14 PM PDT 24 7587324672 ps
T849 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3061297495 Jul 06 07:02:29 PM PDT 24 Jul 06 07:02:33 PM PDT 24 930259075 ps
T850 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2231101562 Jul 06 07:03:00 PM PDT 24 Jul 06 07:03:02 PM PDT 24 397365779 ps
T851 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1454746186 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:06 PM PDT 24 491968519 ps
T852 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2764966222 Jul 06 07:02:33 PM PDT 24 Jul 06 07:02:35 PM PDT 24 512496945 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2018785710 Jul 06 07:02:22 PM PDT 24 Jul 06 07:02:25 PM PDT 24 324217974 ps
T854 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1707536156 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:07 PM PDT 24 349961765 ps
T855 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2702383000 Jul 06 07:02:52 PM PDT 24 Jul 06 07:03:03 PM PDT 24 4026937258 ps
T856 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2826287549 Jul 06 07:02:37 PM PDT 24 Jul 06 07:02:38 PM PDT 24 479297838 ps
T857 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2683214062 Jul 06 07:02:51 PM PDT 24 Jul 06 07:02:54 PM PDT 24 358057147 ps
T858 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2077050732 Jul 06 07:02:58 PM PDT 24 Jul 06 07:03:00 PM PDT 24 554378967 ps
T859 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.118336232 Jul 06 07:02:56 PM PDT 24 Jul 06 07:02:59 PM PDT 24 1958362819 ps
T860 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2023329635 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:06 PM PDT 24 431431559 ps
T861 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3702917022 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:54 PM PDT 24 406015159 ps
T862 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4058546414 Jul 06 07:02:21 PM PDT 24 Jul 06 07:02:26 PM PDT 24 4888852879 ps
T863 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2926695452 Jul 06 07:02:51 PM PDT 24 Jul 06 07:02:53 PM PDT 24 387929189 ps
T121 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2203256460 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:27 PM PDT 24 417253339 ps
T864 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2378474034 Jul 06 07:03:05 PM PDT 24 Jul 06 07:03:07 PM PDT 24 425557131 ps
T122 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4240748723 Jul 06 07:02:22 PM PDT 24 Jul 06 07:04:20 PM PDT 24 49614671442 ps
T123 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2902499334 Jul 06 07:02:33 PM PDT 24 Jul 06 07:03:36 PM PDT 24 27131214064 ps
T865 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3768978163 Jul 06 07:02:59 PM PDT 24 Jul 06 07:03:11 PM PDT 24 4243750349 ps
T866 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1274887962 Jul 06 07:02:33 PM PDT 24 Jul 06 07:02:42 PM PDT 24 8687434988 ps
T867 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.574271654 Jul 06 07:02:33 PM PDT 24 Jul 06 07:02:36 PM PDT 24 2539161906 ps
T868 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3831060065 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:30 PM PDT 24 474033196 ps
T869 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2732439942 Jul 06 07:03:00 PM PDT 24 Jul 06 07:03:02 PM PDT 24 321365481 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1161114538 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:41 PM PDT 24 7860652764 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.775436288 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:30 PM PDT 24 1218905084 ps
T871 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1302497484 Jul 06 07:02:54 PM PDT 24 Jul 06 07:02:57 PM PDT 24 433206723 ps
T872 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1007845590 Jul 06 07:03:05 PM PDT 24 Jul 06 07:03:07 PM PDT 24 374124951 ps
T873 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.520325364 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:07 PM PDT 24 372694281 ps
T73 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.194156105 Jul 06 07:02:36 PM PDT 24 Jul 06 07:02:44 PM PDT 24 8577431826 ps
T125 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2704411972 Jul 06 07:02:51 PM PDT 24 Jul 06 07:02:53 PM PDT 24 399123261 ps
T874 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1732259002 Jul 06 07:02:57 PM PDT 24 Jul 06 07:03:00 PM PDT 24 543730064 ps
T875 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1071055073 Jul 06 07:02:51 PM PDT 24 Jul 06 07:02:53 PM PDT 24 526870846 ps
T74 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2613046966 Jul 06 07:02:43 PM PDT 24 Jul 06 07:02:55 PM PDT 24 8687538099 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1065624626 Jul 06 07:02:28 PM PDT 24 Jul 06 07:02:31 PM PDT 24 366022998 ps
T126 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.438461984 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:30 PM PDT 24 577229666 ps
T877 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.659495203 Jul 06 07:02:39 PM PDT 24 Jul 06 07:02:41 PM PDT 24 523275170 ps
T878 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2095573461 Jul 06 07:02:51 PM PDT 24 Jul 06 07:02:54 PM PDT 24 419133240 ps
T879 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2937817935 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:38 PM PDT 24 2750075227 ps
T880 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.119302302 Jul 06 07:03:02 PM PDT 24 Jul 06 07:03:04 PM PDT 24 496592383 ps
T881 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2924291412 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:07 PM PDT 24 491422192 ps
T882 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2369607278 Jul 06 07:02:56 PM PDT 24 Jul 06 07:02:57 PM PDT 24 353159981 ps
T883 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2843417744 Jul 06 07:02:43 PM PDT 24 Jul 06 07:02:47 PM PDT 24 544819683 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.304523147 Jul 06 07:02:46 PM PDT 24 Jul 06 07:02:52 PM PDT 24 2370026003 ps
T885 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3215644635 Jul 06 07:03:06 PM PDT 24 Jul 06 07:03:08 PM PDT 24 298159845 ps
T886 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1259938214 Jul 06 07:02:55 PM PDT 24 Jul 06 07:03:06 PM PDT 24 4501390355 ps
T887 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3859246186 Jul 06 07:02:58 PM PDT 24 Jul 06 07:03:00 PM PDT 24 559915763 ps
T888 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4038132453 Jul 06 07:02:50 PM PDT 24 Jul 06 07:02:52 PM PDT 24 492452368 ps
T889 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3644038482 Jul 06 07:02:59 PM PDT 24 Jul 06 07:03:04 PM PDT 24 1822481794 ps
T890 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1130139322 Jul 06 07:03:06 PM PDT 24 Jul 06 07:03:08 PM PDT 24 334852257 ps
T891 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2684883452 Jul 06 07:02:26 PM PDT 24 Jul 06 07:02:28 PM PDT 24 511768361 ps
T892 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3974716119 Jul 06 07:02:41 PM PDT 24 Jul 06 07:02:53 PM PDT 24 4185667966 ps
T893 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1656192764 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:40 PM PDT 24 390709872 ps
T894 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2183760269 Jul 06 07:03:04 PM PDT 24 Jul 06 07:03:06 PM PDT 24 415767847 ps
T895 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4229415637 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:42 PM PDT 24 550482759 ps
T896 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.495418814 Jul 06 07:02:40 PM PDT 24 Jul 06 07:02:42 PM PDT 24 507629511 ps
T897 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1186687262 Jul 06 07:02:27 PM PDT 24 Jul 06 07:02:29 PM PDT 24 374697886 ps
T898 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2086856928 Jul 06 07:03:07 PM PDT 24 Jul 06 07:03:09 PM PDT 24 297310408 ps
T899 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4121372149 Jul 06 07:02:59 PM PDT 24 Jul 06 07:03:01 PM PDT 24 568401344 ps
T900 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3020209456 Jul 06 07:02:53 PM PDT 24 Jul 06 07:02:55 PM PDT 24 486734512 ps
T901 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1305811924 Jul 06 07:02:24 PM PDT 24 Jul 06 07:02:28 PM PDT 24 923395558 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2690530534 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:55 PM PDT 24 509364148 ps
T903 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2733511763 Jul 06 07:02:19 PM PDT 24 Jul 06 07:02:22 PM PDT 24 376553068 ps
T904 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2356376956 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:55 PM PDT 24 2625051209 ps
T905 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1335938689 Jul 06 07:02:52 PM PDT 24 Jul 06 07:02:55 PM PDT 24 289090981 ps
T906 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.175048384 Jul 06 07:02:26 PM PDT 24 Jul 06 07:04:15 PM PDT 24 51756242689 ps
T907 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.137085914 Jul 06 07:03:03 PM PDT 24 Jul 06 07:03:06 PM PDT 24 410799466 ps
T908 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2995321501 Jul 06 07:03:06 PM PDT 24 Jul 06 07:03:08 PM PDT 24 320230475 ps
T909 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1767007245 Jul 06 07:02:51 PM PDT 24 Jul 06 07:03:04 PM PDT 24 7816125325 ps
T910 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.968827348 Jul 06 07:02:28 PM PDT 24 Jul 06 07:02:34 PM PDT 24 4345880036 ps
T911 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2739430170 Jul 06 07:02:41 PM PDT 24 Jul 06 07:02:44 PM PDT 24 353503514 ps
T912 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.793178148 Jul 06 07:02:40 PM PDT 24 Jul 06 07:02:41 PM PDT 24 496189728 ps
T913 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1171636686 Jul 06 07:02:32 PM PDT 24 Jul 06 07:02:36 PM PDT 24 553708099 ps
T914 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1902917725 Jul 06 07:02:57 PM PDT 24 Jul 06 07:02:59 PM PDT 24 757062550 ps
T915 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.352733535 Jul 06 07:03:01 PM PDT 24 Jul 06 07:03:17 PM PDT 24 3906587705 ps
T916 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2906199233 Jul 06 07:03:02 PM PDT 24 Jul 06 07:03:04 PM PDT 24 313048276 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.207135716 Jul 06 07:02:27 PM PDT 24 Jul 06 07:03:58 PM PDT 24 26456665812 ps
T918 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3173608909 Jul 06 07:02:38 PM PDT 24 Jul 06 07:02:43 PM PDT 24 2464522573 ps
T919 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2291813455 Jul 06 07:02:24 PM PDT 24 Jul 06 07:02:28 PM PDT 24 8319048113 ps

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2031314271
Short name T9
Test name
Test status
Simulation time 304296169172 ps
CPU time 240.5 seconds
Started Jul 06 06:36:52 PM PDT 24
Finished Jul 06 06:40:53 PM PDT 24
Peak memory 210508 kb
Host smart-32e90d90-88cb-4c47-985a-df6234b81eff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031314271 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2031314271
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.1833725616
Short name T35
Test name
Test status
Simulation time 356136019618 ps
CPU time 772.9 seconds
Started Jul 06 06:32:55 PM PDT 24
Finished Jul 06 06:45:49 PM PDT 24
Peak memory 201948 kb
Host smart-40edaccd-6815-48b3-8e08-d3f077415d3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833725616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.1833725616
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.990299926
Short name T16
Test name
Test status
Simulation time 733196938009 ps
CPU time 426.8 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:39:48 PM PDT 24
Peak memory 216924 kb
Host smart-c9867e6e-3929-4021-a6e8-1a62b97cce6b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990299926 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.990299926
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.1475092332
Short name T180
Test name
Test status
Simulation time 542646967629 ps
CPU time 587.9 seconds
Started Jul 06 06:32:20 PM PDT 24
Finished Jul 06 06:42:09 PM PDT 24
Peak memory 201944 kb
Host smart-c98fb5ed-0adb-4f3d-92b0-4daee174f2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475092332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.1475092332
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2865309920
Short name T173
Test name
Test status
Simulation time 562522121535 ps
CPU time 741.24 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:45:01 PM PDT 24
Peak memory 210600 kb
Host smart-24acea5b-a282-4b38-acdf-fb3d89b4b94f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865309920 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2865309920
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.91220170
Short name T10
Test name
Test status
Simulation time 339283314969 ps
CPU time 389.57 seconds
Started Jul 06 06:34:17 PM PDT 24
Finished Jul 06 06:40:47 PM PDT 24
Peak memory 201924 kb
Host smart-c19ed625-4f51-4cf8-bb0c-ea2b9483854e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91220170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.91220170
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.4065753784
Short name T221
Test name
Test status
Simulation time 494247735966 ps
CPU time 605.58 seconds
Started Jul 06 06:35:29 PM PDT 24
Finished Jul 06 06:45:35 PM PDT 24
Peak memory 201996 kb
Host smart-2abe3aab-0736-4b92-854e-c91543a3e24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065753784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.4065753784
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2796435733
Short name T142
Test name
Test status
Simulation time 592583611973 ps
CPU time 264.29 seconds
Started Jul 06 06:34:28 PM PDT 24
Finished Jul 06 06:38:53 PM PDT 24
Peak memory 201936 kb
Host smart-9a156ecc-c473-423c-975e-f62887b4ada0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796435733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2796435733
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.251231457
Short name T14
Test name
Test status
Simulation time 263574132846 ps
CPU time 326.36 seconds
Started Jul 06 06:34:11 PM PDT 24
Finished Jul 06 06:39:38 PM PDT 24
Peak memory 210592 kb
Host smart-4decceb3-c281-4022-97ed-39cf8ce61b30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251231457 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.251231457
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3632690206
Short name T157
Test name
Test status
Simulation time 587128453161 ps
CPU time 593.92 seconds
Started Jul 06 06:33:09 PM PDT 24
Finished Jul 06 06:43:03 PM PDT 24
Peak memory 201984 kb
Host smart-584e66dd-1c6d-4578-9492-bdbb52e57321
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632690206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3632690206
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.406668206
Short name T222
Test name
Test status
Simulation time 492286692925 ps
CPU time 683.03 seconds
Started Jul 06 06:32:42 PM PDT 24
Finished Jul 06 06:44:05 PM PDT 24
Peak memory 201908 kb
Host smart-c9644887-09a7-42f9-becc-2bfb51ce2d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406668206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.406668206
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2123499783
Short name T57
Test name
Test status
Simulation time 536714435 ps
CPU time 2.59 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:02:54 PM PDT 24
Peak memory 201760 kb
Host smart-29282123-09bc-4215-b53c-abb3ea7d5b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123499783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2123499783
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.3070643273
Short name T61
Test name
Test status
Simulation time 7421070593 ps
CPU time 5.48 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:32:32 PM PDT 24
Peak memory 218168 kb
Host smart-0cf89674-53e8-481e-84a2-0d0032d77a16
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070643273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.3070643273
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.3030963595
Short name T241
Test name
Test status
Simulation time 502794878607 ps
CPU time 79.01 seconds
Started Jul 06 06:34:16 PM PDT 24
Finished Jul 06 06:35:35 PM PDT 24
Peak memory 201860 kb
Host smart-193a8546-044f-4429-a076-9e1215e894b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030963595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.3030963595
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2974460312
Short name T6
Test name
Test status
Simulation time 156708893796 ps
CPU time 240.57 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:37:01 PM PDT 24
Peak memory 210616 kb
Host smart-35867c72-77d9-42fe-b40d-fe0cb8ce70ce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974460312 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2974460312
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2905733135
Short name T51
Test name
Test status
Simulation time 488197289 ps
CPU time 1.94 seconds
Started Jul 06 07:02:44 PM PDT 24
Finished Jul 06 07:02:46 PM PDT 24
Peak memory 201528 kb
Host smart-109c0b83-0eee-428c-9077-8d29393c4a9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905733135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2905733135
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3459806009
Short name T237
Test name
Test status
Simulation time 530055322897 ps
CPU time 378.75 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:38:49 PM PDT 24
Peak memory 201864 kb
Host smart-0151056a-9000-471d-a3ee-507074ff3bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459806009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3459806009
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3922797959
Short name T38
Test name
Test status
Simulation time 454263318594 ps
CPU time 349.92 seconds
Started Jul 06 06:33:26 PM PDT 24
Finished Jul 06 06:39:16 PM PDT 24
Peak memory 210544 kb
Host smart-84871523-c644-4e52-8c4c-a842ffccde4b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922797959 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3922797959
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.2248999276
Short name T136
Test name
Test status
Simulation time 166269003616 ps
CPU time 377.81 seconds
Started Jul 06 06:34:53 PM PDT 24
Finished Jul 06 06:41:12 PM PDT 24
Peak memory 200932 kb
Host smart-1fdc18f6-225c-42c1-83f8-6ec9df0bb80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248999276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.2248999276
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.724316425
Short name T149
Test name
Test status
Simulation time 490005787320 ps
CPU time 125.28 seconds
Started Jul 06 06:35:18 PM PDT 24
Finished Jul 06 06:37:24 PM PDT 24
Peak memory 201984 kb
Host smart-c9afa52d-beed-4f1c-ad5f-2eb68790949b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724316425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.724316425
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.2584075287
Short name T144
Test name
Test status
Simulation time 157094185110 ps
CPU time 89.89 seconds
Started Jul 06 06:36:02 PM PDT 24
Finished Jul 06 06:37:32 PM PDT 24
Peak memory 210308 kb
Host smart-6b006918-8053-4c7c-8edb-1318078c2f3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584075287 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.2584075287
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.2438553637
Short name T106
Test name
Test status
Simulation time 550758014062 ps
CPU time 582.06 seconds
Started Jul 06 06:33:27 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 201984 kb
Host smart-1fbd701e-edb3-4ec1-b855-29dd79f0e95c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438553637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.2438553637
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.2450759885
Short name T107
Test name
Test status
Simulation time 338812440571 ps
CPU time 376.22 seconds
Started Jul 06 06:32:44 PM PDT 24
Finished Jul 06 06:39:00 PM PDT 24
Peak memory 201924 kb
Host smart-d395939a-c6d3-4308-be29-f27ee1fe142d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450759885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.2450759885
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.2024652880
Short name T168
Test name
Test status
Simulation time 524224963696 ps
CPU time 174.39 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:35:42 PM PDT 24
Peak memory 201984 kb
Host smart-c9a42211-dc99-40b4-b16a-a8b66d57984f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024652880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.2024652880
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.3553067364
Short name T287
Test name
Test status
Simulation time 422592899850 ps
CPU time 794.33 seconds
Started Jul 06 06:33:14 PM PDT 24
Finished Jul 06 06:46:29 PM PDT 24
Peak memory 201956 kb
Host smart-bb79d8f0-b304-4d8d-bc3e-6779d68799d4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553067364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.3553067364
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3452377257
Short name T15
Test name
Test status
Simulation time 120159170741 ps
CPU time 181.27 seconds
Started Jul 06 06:33:47 PM PDT 24
Finished Jul 06 06:36:49 PM PDT 24
Peak memory 211536 kb
Host smart-331eeb2c-a6af-47ec-b72b-9bb1af340432
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452377257 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3452377257
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.41735677
Short name T291
Test name
Test status
Simulation time 535238243668 ps
CPU time 1229.42 seconds
Started Jul 06 06:36:09 PM PDT 24
Finished Jul 06 06:56:39 PM PDT 24
Peak memory 201908 kb
Host smart-606e1a7e-04a3-487c-97d8-8b33d4c7dc96
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41735677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gatin
g.41735677
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1530826405
Short name T239
Test name
Test status
Simulation time 525835263836 ps
CPU time 554.92 seconds
Started Jul 06 06:36:23 PM PDT 24
Finished Jul 06 06:45:38 PM PDT 24
Peak memory 201996 kb
Host smart-5f15d1ff-e2e5-4428-8b51-2f5c3af2611f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530826405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1530826405
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.3060181669
Short name T272
Test name
Test status
Simulation time 338599891982 ps
CPU time 760.13 seconds
Started Jul 06 06:33:56 PM PDT 24
Finished Jul 06 06:46:36 PM PDT 24
Peak memory 201900 kb
Host smart-33dc162f-1ddb-4977-8093-365c94b2a1c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060181669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.3060181669
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.1140098172
Short name T234
Test name
Test status
Simulation time 511568775355 ps
CPU time 507.65 seconds
Started Jul 06 06:37:12 PM PDT 24
Finished Jul 06 06:45:40 PM PDT 24
Peak memory 201932 kb
Host smart-402dc357-3dd6-4afd-ba55-38e2faed8c36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140098172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.1140098172
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.792802243
Short name T274
Test name
Test status
Simulation time 364615349164 ps
CPU time 830 seconds
Started Jul 06 06:37:53 PM PDT 24
Finished Jul 06 06:51:43 PM PDT 24
Peak memory 201896 kb
Host smart-773e5cbe-ae6e-454b-9ce4-e76ba0f24d4d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792802243 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gati
ng.792802243
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.294306078
Short name T68
Test name
Test status
Simulation time 505649374 ps
CPU time 0.71 seconds
Started Jul 06 06:32:25 PM PDT 24
Finished Jul 06 06:32:26 PM PDT 24
Peak memory 201676 kb
Host smart-c89a7a47-d170-4022-9d64-851ec3d976a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294306078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.294306078
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2772059993
Short name T848
Test name
Test status
Simulation time 7587324672 ps
CPU time 21.69 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:03:14 PM PDT 24
Peak memory 201860 kb
Host smart-62e1ee74-d5de-4c55-b26e-5aeaa6404a90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772059993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2772059993
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1789596568
Short name T148
Test name
Test status
Simulation time 296280160880 ps
CPU time 149.52 seconds
Started Jul 06 06:36:27 PM PDT 24
Finished Jul 06 06:38:57 PM PDT 24
Peak memory 210288 kb
Host smart-c47edbc6-627e-4191-a839-5bcd6bb2809e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789596568 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1789596568
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.928492503
Short name T244
Test name
Test status
Simulation time 333937016826 ps
CPU time 696.83 seconds
Started Jul 06 06:36:04 PM PDT 24
Finished Jul 06 06:47:41 PM PDT 24
Peak memory 201972 kb
Host smart-b1cb1ad7-3957-4d54-a731-557181095023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928492503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.928492503
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.2246403001
Short name T285
Test name
Test status
Simulation time 93905841646 ps
CPU time 50.35 seconds
Started Jul 06 06:32:27 PM PDT 24
Finished Jul 06 06:33:18 PM PDT 24
Peak memory 210216 kb
Host smart-8f38e0b8-670f-4878-a903-e473e67daa3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246403001 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.2246403001
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.3581382779
Short name T232
Test name
Test status
Simulation time 492886961396 ps
CPU time 1152.67 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:52:11 PM PDT 24
Peak memory 201900 kb
Host smart-c571aa4d-0a98-440f-ada1-f4ba50bc4412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581382779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.3581382779
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.2999419055
Short name T27
Test name
Test status
Simulation time 361861441366 ps
CPU time 883.26 seconds
Started Jul 06 06:37:25 PM PDT 24
Finished Jul 06 06:52:09 PM PDT 24
Peak memory 201936 kb
Host smart-68b508be-0a4a-45cb-a0dc-4fd4e11fe31d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999419055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.2999419055
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.679168807
Short name T308
Test name
Test status
Simulation time 490416903614 ps
CPU time 371.61 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:38:41 PM PDT 24
Peak memory 201924 kb
Host smart-4c5faefe-d062-4385-8367-d4eee5036110
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679168807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.679168807
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.129090793
Short name T219
Test name
Test status
Simulation time 331034820397 ps
CPU time 772.94 seconds
Started Jul 06 06:33:24 PM PDT 24
Finished Jul 06 06:46:17 PM PDT 24
Peak memory 201924 kb
Host smart-f745326f-cab1-4294-ad4f-37c7315f5ab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129090793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.129090793
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.1016880576
Short name T282
Test name
Test status
Simulation time 60585880051 ps
CPU time 105.13 seconds
Started Jul 06 06:32:27 PM PDT 24
Finished Jul 06 06:34:12 PM PDT 24
Peak memory 202040 kb
Host smart-07949676-3c51-479c-9da4-354c5d8d7606
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016880576 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.1016880576
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.561290326
Short name T330
Test name
Test status
Simulation time 535493950529 ps
CPU time 310.04 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:37:58 PM PDT 24
Peak memory 201940 kb
Host smart-0b4c6bc9-9bde-4a25-8df4-183061405bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561290326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.561290326
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.1047518996
Short name T248
Test name
Test status
Simulation time 327057919125 ps
CPU time 362.22 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:38:25 PM PDT 24
Peak memory 201904 kb
Host smart-13f8ee2c-4423-4e7e-9d5c-23345344b90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047518996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.1047518996
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.2628983832
Short name T164
Test name
Test status
Simulation time 327420333995 ps
CPU time 197.16 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:36:08 PM PDT 24
Peak memory 201896 kb
Host smart-7856d6aa-b1ef-4af6-90c1-14b97d7c5e9b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628983832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.2628983832
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2179109576
Short name T257
Test name
Test status
Simulation time 182600721794 ps
CPU time 105.78 seconds
Started Jul 06 06:33:03 PM PDT 24
Finished Jul 06 06:34:49 PM PDT 24
Peak memory 201916 kb
Host smart-da6d28c9-fa05-4602-b5b4-5a24169d8d36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179109576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2179109576
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1878433341
Short name T108
Test name
Test status
Simulation time 200342725420 ps
CPU time 374.25 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:39:05 PM PDT 24
Peak memory 201892 kb
Host smart-a60bafa4-74ca-4853-9670-7659f4043684
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878433341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1878433341
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.2428045021
Short name T238
Test name
Test status
Simulation time 674284048432 ps
CPU time 99.58 seconds
Started Jul 06 06:35:41 PM PDT 24
Finished Jul 06 06:37:21 PM PDT 24
Peak memory 201976 kb
Host smart-3419d603-6514-4110-9696-84fc184eae4e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428045021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.2428045021
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.458594604
Short name T202
Test name
Test status
Simulation time 243553198913 ps
CPU time 753.32 seconds
Started Jul 06 06:36:43 PM PDT 24
Finished Jul 06 06:49:17 PM PDT 24
Peak memory 202288 kb
Host smart-da1d4bcb-adbe-49c0-96f2-d66a14441661
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458594604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
458594604
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.2952854683
Short name T299
Test name
Test status
Simulation time 503769132951 ps
CPU time 258.78 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:36:59 PM PDT 24
Peak memory 201976 kb
Host smart-2daea84c-da31-461e-ae5d-96ff745adc60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952854683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.2952854683
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.657282273
Short name T304
Test name
Test status
Simulation time 333732733380 ps
CPU time 216.84 seconds
Started Jul 06 06:35:53 PM PDT 24
Finished Jul 06 06:39:30 PM PDT 24
Peak memory 201988 kb
Host smart-ea327f5b-0411-4ea9-b573-6cf98f2b8cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657282273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.657282273
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.2315201991
Short name T324
Test name
Test status
Simulation time 518266456869 ps
CPU time 491.2 seconds
Started Jul 06 06:37:24 PM PDT 24
Finished Jul 06 06:45:36 PM PDT 24
Peak memory 201912 kb
Host smart-94cf1f07-1713-4bd8-be60-268cf09821d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315201991 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.2315201991
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3922435217
Short name T251
Test name
Test status
Simulation time 516644433795 ps
CPU time 514.35 seconds
Started Jul 06 06:37:04 PM PDT 24
Finished Jul 06 06:45:39 PM PDT 24
Peak memory 201936 kb
Host smart-e6a0af0c-bee4-414e-ab36-8ce7ed07aeb4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922435217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3922435217
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.477506935
Short name T4
Test name
Test status
Simulation time 162848673584 ps
CPU time 90.25 seconds
Started Jul 06 06:32:23 PM PDT 24
Finished Jul 06 06:33:54 PM PDT 24
Peak memory 201976 kb
Host smart-bccb4f86-3f84-434d-a9f8-785246e39cde
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477506935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.477506935
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1499039101
Short name T283
Test name
Test status
Simulation time 426024879590 ps
CPU time 480.33 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:40:28 PM PDT 24
Peak memory 202016 kb
Host smart-ad4a588a-949c-4899-bb91-efbb7739f705
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499039101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1499039101
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2982647833
Short name T264
Test name
Test status
Simulation time 525430225528 ps
CPU time 1149.33 seconds
Started Jul 06 06:33:56 PM PDT 24
Finished Jul 06 06:53:06 PM PDT 24
Peak memory 201840 kb
Host smart-319fb82b-3ca2-49da-8d48-1d53791a9c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982647833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2982647833
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.2723793794
Short name T138
Test name
Test status
Simulation time 153626062301 ps
CPU time 201.62 seconds
Started Jul 06 06:35:12 PM PDT 24
Finished Jul 06 06:38:33 PM PDT 24
Peak memory 201964 kb
Host smart-479db815-7c4b-479b-916a-8326958c4b36
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723793794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.2723793794
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.2127114522
Short name T65
Test name
Test status
Simulation time 495070842 ps
CPU time 2.18 seconds
Started Jul 06 07:02:44 PM PDT 24
Finished Jul 06 07:02:46 PM PDT 24
Peak memory 201812 kb
Host smart-9f8e6a71-2f84-447f-b695-9d1e2d668c23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127114522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.2127114522
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.3058849891
Short name T280
Test name
Test status
Simulation time 498928487938 ps
CPU time 454.42 seconds
Started Jul 06 06:32:24 PM PDT 24
Finished Jul 06 06:39:59 PM PDT 24
Peak memory 201916 kb
Host smart-61b7fd0e-0d76-487a-9bd9-602656f480ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058849891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.3058849891
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.3448593227
Short name T348
Test name
Test status
Simulation time 110575636882 ps
CPU time 483.97 seconds
Started Jul 06 06:33:39 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 202236 kb
Host smart-48c11f12-8ca2-4520-9321-a7272c7a1fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448593227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.3448593227
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.186469116
Short name T231
Test name
Test status
Simulation time 521313520443 ps
CPU time 910 seconds
Started Jul 06 06:34:08 PM PDT 24
Finished Jul 06 06:49:18 PM PDT 24
Peak memory 201868 kb
Host smart-330f40c3-565d-4997-b116-d9c219a6c5fe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186469116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gati
ng.186469116
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.194156105
Short name T73
Test name
Test status
Simulation time 8577431826 ps
CPU time 7.61 seconds
Started Jul 06 07:02:36 PM PDT 24
Finished Jul 06 07:02:44 PM PDT 24
Peak memory 201832 kb
Host smart-380afacf-57e0-4a03-afe0-309c96c1a3db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194156105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.194156105
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.2877475664
Short name T211
Test name
Test status
Simulation time 89743168178 ps
CPU time 357.6 seconds
Started Jul 06 06:33:16 PM PDT 24
Finished Jul 06 06:39:14 PM PDT 24
Peak memory 202220 kb
Host smart-2ac311c1-80c1-4d79-9658-1b8124a4b761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877475664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.2877475664
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1232268044
Short name T307
Test name
Test status
Simulation time 161842724433 ps
CPU time 174.27 seconds
Started Jul 06 06:33:19 PM PDT 24
Finished Jul 06 06:36:13 PM PDT 24
Peak memory 201852 kb
Host smart-aeb73934-750c-408e-a69b-9cb3b1fe369f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232268044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1232268044
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1205511840
Short name T139
Test name
Test status
Simulation time 493874133049 ps
CPU time 296.75 seconds
Started Jul 06 06:33:33 PM PDT 24
Finished Jul 06 06:38:30 PM PDT 24
Peak memory 201928 kb
Host smart-784b6f73-6e15-4b5e-8e1d-d95f1df6f039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205511840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1205511840
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.190702466
Short name T79
Test name
Test status
Simulation time 518534559661 ps
CPU time 221.45 seconds
Started Jul 06 06:34:39 PM PDT 24
Finished Jul 06 06:38:21 PM PDT 24
Peak memory 201924 kb
Host smart-32690bec-bbd8-4c43-87f0-97b2e666d325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190702466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.190702466
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.649545092
Short name T741
Test name
Test status
Simulation time 130935126636 ps
CPU time 441.5 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:39:52 PM PDT 24
Peak memory 202288 kb
Host smart-57c4aab5-20bb-4143-b61f-bf610236fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649545092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.649545092
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3027203533
Short name T93
Test name
Test status
Simulation time 161699303460 ps
CPU time 382.27 seconds
Started Jul 06 06:35:00 PM PDT 24
Finished Jul 06 06:41:23 PM PDT 24
Peak memory 201924 kb
Host smart-45d7e08e-0289-467d-8f63-6469dcdf9096
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027203533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3027203533
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.3136224860
Short name T233
Test name
Test status
Simulation time 523280311123 ps
CPU time 1271.19 seconds
Started Jul 06 06:35:48 PM PDT 24
Finished Jul 06 06:57:00 PM PDT 24
Peak memory 201920 kb
Host smart-fe33145f-73c4-48b7-9b7e-a3e488ac0f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136224860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.3136224860
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1031420680
Short name T254
Test name
Test status
Simulation time 374023402004 ps
CPU time 116.04 seconds
Started Jul 06 06:37:53 PM PDT 24
Finished Jul 06 06:39:50 PM PDT 24
Peak memory 201864 kb
Host smart-242f0efb-c9d4-4e7f-8712-b0be2eed9d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031420680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1031420680
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2571367654
Short name T293
Test name
Test status
Simulation time 246245039777 ps
CPU time 147.78 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:35:15 PM PDT 24
Peak memory 201864 kb
Host smart-f08e7028-db46-4bb0-9bdd-97d0b5b83bb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571367654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2571367654
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.2828035440
Short name T346
Test name
Test status
Simulation time 514748119127 ps
CPU time 1063.74 seconds
Started Jul 06 06:32:46 PM PDT 24
Finished Jul 06 06:50:30 PM PDT 24
Peak memory 201920 kb
Host smart-21d5916b-4c89-47a9-89b6-0145f0cf80a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828035440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.2828035440
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3755853973
Short name T326
Test name
Test status
Simulation time 166267372540 ps
CPU time 156.56 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:35:27 PM PDT 24
Peak memory 201832 kb
Host smart-6b245cf8-844e-480e-912f-52440df0b6ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755853973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3755853973
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.1186490595
Short name T18
Test name
Test status
Simulation time 70638150340 ps
CPU time 176.26 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:35:46 PM PDT 24
Peak memory 217800 kb
Host smart-3f263416-8b42-42b1-899b-27e9a61abd85
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186490595 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.1186490595
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.3883938058
Short name T210
Test name
Test status
Simulation time 620279056230 ps
CPU time 949.93 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:48:42 PM PDT 24
Peak memory 210608 kb
Host smart-fbfcd126-13b2-4182-a381-6cb17a7a9bec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883938058 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.3883938058
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1707532315
Short name T318
Test name
Test status
Simulation time 354333472016 ps
CPU time 700.16 seconds
Started Jul 06 06:33:12 PM PDT 24
Finished Jul 06 06:44:52 PM PDT 24
Peak memory 201976 kb
Host smart-908b2ac7-59dd-4a8e-b031-d3c7e9f26c08
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707532315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1707532315
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.4258663373
Short name T150
Test name
Test status
Simulation time 330415559981 ps
CPU time 196.47 seconds
Started Jul 06 06:33:39 PM PDT 24
Finished Jul 06 06:36:56 PM PDT 24
Peak memory 201932 kb
Host smart-a5736036-8808-4a97-a146-265def93858a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258663373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.4258663373
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3951194834
Short name T316
Test name
Test status
Simulation time 159923973249 ps
CPU time 340.47 seconds
Started Jul 06 06:33:59 PM PDT 24
Finished Jul 06 06:39:39 PM PDT 24
Peak memory 201948 kb
Host smart-c93de711-63c8-4b64-89d6-2b8fe4cb7f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951194834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3951194834
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.4269110353
Short name T319
Test name
Test status
Simulation time 173717580590 ps
CPU time 394.26 seconds
Started Jul 06 06:34:38 PM PDT 24
Finished Jul 06 06:41:13 PM PDT 24
Peak memory 201948 kb
Host smart-02a9e995-cbc0-457f-874b-2f7dcdb2395d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269110353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.4269110353
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2152461017
Short name T20
Test name
Test status
Simulation time 156621389063 ps
CPU time 167.22 seconds
Started Jul 06 06:34:45 PM PDT 24
Finished Jul 06 06:37:33 PM PDT 24
Peak memory 210588 kb
Host smart-30fe1da6-b6a3-413c-b1f0-13a6f92deaed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152461017 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2152461017
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3027856056
Short name T303
Test name
Test status
Simulation time 575122496489 ps
CPU time 295.38 seconds
Started Jul 06 06:34:51 PM PDT 24
Finished Jul 06 06:39:46 PM PDT 24
Peak memory 201980 kb
Host smart-9a4c172f-cc36-4f92-af6e-372a10506031
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027856056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3027856056
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.2738679813
Short name T314
Test name
Test status
Simulation time 498424999488 ps
CPU time 1127.54 seconds
Started Jul 06 06:37:25 PM PDT 24
Finished Jul 06 06:56:13 PM PDT 24
Peak memory 201940 kb
Host smart-e6c4ef3d-1c88-422c-b27d-e52ec07b2c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738679813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.2738679813
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.3410172317
Short name T353
Test name
Test status
Simulation time 121983655817 ps
CPU time 420.51 seconds
Started Jul 06 06:32:42 PM PDT 24
Finished Jul 06 06:39:43 PM PDT 24
Peak memory 202232 kb
Host smart-1a1f9963-9718-4da6-a4e0-050992a186d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410172317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.3410172317
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2150544671
Short name T37
Test name
Test status
Simulation time 162072198149 ps
CPU time 42.15 seconds
Started Jul 06 06:32:39 PM PDT 24
Finished Jul 06 06:33:22 PM PDT 24
Peak memory 210292 kb
Host smart-8ea6790a-443b-4147-b144-a15e1baf9354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150544671 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2150544671
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1015803422
Short name T111
Test name
Test status
Simulation time 493224386 ps
CPU time 2.59 seconds
Started Jul 06 07:02:20 PM PDT 24
Finished Jul 06 07:02:23 PM PDT 24
Peak memory 201732 kb
Host smart-5486b549-cf03-42b4-b1bc-876f563ea391
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015803422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1015803422
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.4240748723
Short name T122
Test name
Test status
Simulation time 49614671442 ps
CPU time 117.42 seconds
Started Jul 06 07:02:22 PM PDT 24
Finished Jul 06 07:04:20 PM PDT 24
Peak memory 201808 kb
Host smart-5566d663-9cdf-4d06-a432-96dd9ba304c7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240748723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.4240748723
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.1305811924
Short name T901
Test name
Test status
Simulation time 923395558 ps
CPU time 2.98 seconds
Started Jul 06 07:02:24 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 201476 kb
Host smart-43a5b173-b8f3-482b-8491-f04fbd88770a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305811924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.1305811924
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.1473718103
Short name T845
Test name
Test status
Simulation time 487927868 ps
CPU time 1.51 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:23 PM PDT 24
Peak memory 211328 kb
Host smart-22072891-0357-476e-bdd3-ecfa04e580a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473718103 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.1473718103
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2203256460
Short name T121
Test name
Test status
Simulation time 417253339 ps
CPU time 1.03 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:27 PM PDT 24
Peak memory 201524 kb
Host smart-20a6ce9d-eb37-4493-a7e3-7f0bdb690e97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203256460 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2203256460
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.2733511763
Short name T903
Test name
Test status
Simulation time 376553068 ps
CPU time 1.54 seconds
Started Jul 06 07:02:19 PM PDT 24
Finished Jul 06 07:02:22 PM PDT 24
Peak memory 201464 kb
Host smart-ec683c87-db35-4012-9bc4-27fd02f5aee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733511763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.2733511763
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2697752963
Short name T843
Test name
Test status
Simulation time 4901248236 ps
CPU time 6.9 seconds
Started Jul 06 07:02:24 PM PDT 24
Finished Jul 06 07:02:31 PM PDT 24
Peak memory 201768 kb
Host smart-029af74a-4f0d-4077-b900-2e168c1f872c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697752963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2697752963
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2018785710
Short name T853
Test name
Test status
Simulation time 324217974 ps
CPU time 2.09 seconds
Started Jul 06 07:02:22 PM PDT 24
Finished Jul 06 07:02:25 PM PDT 24
Peak memory 201792 kb
Host smart-e93efe6b-8eb2-49ae-aca5-52f2d8c5631a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018785710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2018785710
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.4058546414
Short name T862
Test name
Test status
Simulation time 4888852879 ps
CPU time 3.66 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:26 PM PDT 24
Peak memory 201832 kb
Host smart-68811b04-7c01-46bc-9c11-3f8c81a7fbac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058546414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_in
tg_err.4058546414
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.3061297495
Short name T849
Test name
Test status
Simulation time 930259075 ps
CPU time 3.38 seconds
Started Jul 06 07:02:29 PM PDT 24
Finished Jul 06 07:02:33 PM PDT 24
Peak memory 201628 kb
Host smart-2503af18-6c89-45f7-aba6-336905857984
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061297495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.3061297495
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.1367240674
Short name T53
Test name
Test status
Simulation time 26582669888 ps
CPU time 84.43 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:03:54 PM PDT 24
Peak memory 201796 kb
Host smart-d60095c7-2938-4555-9c05-3c28ab1a87a2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367240674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.1367240674
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.4206227190
Short name T831
Test name
Test status
Simulation time 1187031480 ps
CPU time 1.69 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:24 PM PDT 24
Peak memory 201484 kb
Host smart-d3b705d0-b1f0-4760-a846-6c827df72bbd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206227190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.4206227190
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.3831060065
Short name T868
Test name
Test status
Simulation time 474033196 ps
CPU time 1.34 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:30 PM PDT 24
Peak memory 209920 kb
Host smart-7eb6a9bd-0d06-4d95-9d0e-6a8aa9b5ab4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831060065 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.3831060065
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2684883452
Short name T891
Test name
Test status
Simulation time 511768361 ps
CPU time 2.03 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 201524 kb
Host smart-b8588fae-bf63-4071-a469-f3e044fbc95b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684883452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2684883452
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.3694040734
Short name T799
Test name
Test status
Simulation time 391336883 ps
CPU time 1.49 seconds
Started Jul 06 07:02:24 PM PDT 24
Finished Jul 06 07:02:26 PM PDT 24
Peak memory 201396 kb
Host smart-d1d04c75-7dfc-4f88-8db1-120672b945ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694040734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.3694040734
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.968827348
Short name T910
Test name
Test status
Simulation time 4345880036 ps
CPU time 4.4 seconds
Started Jul 06 07:02:28 PM PDT 24
Finished Jul 06 07:02:34 PM PDT 24
Peak memory 201888 kb
Host smart-23d8b80b-5af1-4dea-a166-fef14841edc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968827348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ct
rl_same_csr_outstanding.968827348
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.4247522819
Short name T70
Test name
Test status
Simulation time 854452172 ps
CPU time 2.5 seconds
Started Jul 06 07:02:21 PM PDT 24
Finished Jul 06 07:02:24 PM PDT 24
Peak memory 201784 kb
Host smart-eb975f76-55be-41ef-97ca-34cc73ce4068
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247522819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.4247522819
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2291813455
Short name T919
Test name
Test status
Simulation time 8319048113 ps
CPU time 3.71 seconds
Started Jul 06 07:02:24 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 201884 kb
Host smart-9bed1800-4ddd-4a15-85ec-7f73d7a5f286
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291813455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2291813455
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.184785848
Short name T847
Test name
Test status
Simulation time 455501737 ps
CPU time 1.84 seconds
Started Jul 06 07:02:43 PM PDT 24
Finished Jul 06 07:02:46 PM PDT 24
Peak memory 201556 kb
Host smart-be1eaf3a-882d-493c-a6fe-3e62763056b5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184785848 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.184785848
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.1335938689
Short name T905
Test name
Test status
Simulation time 289090981 ps
CPU time 1.35 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201440 kb
Host smart-e10f120d-9c8a-4e98-af65-47ad63c7141d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335938689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.1335938689
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.304523147
Short name T884
Test name
Test status
Simulation time 2370026003 ps
CPU time 5.11 seconds
Started Jul 06 07:02:46 PM PDT 24
Finished Jul 06 07:02:52 PM PDT 24
Peak memory 201624 kb
Host smart-0fd96c57-99e1-40f4-90e5-9b15d845b854
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304523147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_c
trl_same_csr_outstanding.304523147
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2843417744
Short name T883
Test name
Test status
Simulation time 544819683 ps
CPU time 3.69 seconds
Started Jul 06 07:02:43 PM PDT 24
Finished Jul 06 07:02:47 PM PDT 24
Peak memory 217636 kb
Host smart-ade20e60-e8a0-43dc-8bac-a667513d6c6b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843417744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2843417744
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.101208362
Short name T55
Test name
Test status
Simulation time 8143095417 ps
CPU time 18.89 seconds
Started Jul 06 07:02:45 PM PDT 24
Finished Jul 06 07:03:05 PM PDT 24
Peak memory 201908 kb
Host smart-26802a58-f182-457e-b833-23405ffae21d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101208362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_in
tg_err.101208362
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.2680217594
Short name T834
Test name
Test status
Simulation time 580072492 ps
CPU time 1.44 seconds
Started Jul 06 07:02:45 PM PDT 24
Finished Jul 06 07:02:47 PM PDT 24
Peak memory 201520 kb
Host smart-73c56653-b347-45b7-890e-52235f7743f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680217594 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.2680217594
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.416258817
Short name T119
Test name
Test status
Simulation time 359020626 ps
CPU time 1.7 seconds
Started Jul 06 07:02:44 PM PDT 24
Finished Jul 06 07:02:46 PM PDT 24
Peak memory 201436 kb
Host smart-7a30d5fa-bd43-4f9d-a6aa-fa7ac96b6097
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416258817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.416258817
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.109826943
Short name T807
Test name
Test status
Simulation time 399125287 ps
CPU time 0.93 seconds
Started Jul 06 07:02:45 PM PDT 24
Finished Jul 06 07:02:46 PM PDT 24
Peak memory 201428 kb
Host smart-b8dc6510-2f78-4f61-9fff-2386e80afa1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109826943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.109826943
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1527195220
Short name T129
Test name
Test status
Simulation time 5027705036 ps
CPU time 20.28 seconds
Started Jul 06 07:02:46 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201840 kb
Host smart-1733fad1-e74c-42d6-9634-8ac9425144b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527195220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1527195220
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.2613046966
Short name T74
Test name
Test status
Simulation time 8687538099 ps
CPU time 11.41 seconds
Started Jul 06 07:02:43 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201836 kb
Host smart-77b3c587-b9b8-41fc-acd5-defbb1582a2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613046966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.2613046966
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4038132453
Short name T888
Test name
Test status
Simulation time 492452368 ps
CPU time 2.03 seconds
Started Jul 06 07:02:50 PM PDT 24
Finished Jul 06 07:02:52 PM PDT 24
Peak memory 201556 kb
Host smart-8749a98e-14b8-4689-998f-95e8041f3b50
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038132453 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4038132453
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2704411972
Short name T125
Test name
Test status
Simulation time 399123261 ps
CPU time 1.16 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:02:53 PM PDT 24
Peak memory 201480 kb
Host smart-7d5ad177-5477-4f81-967c-07e189041432
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704411972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2704411972
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.1302497484
Short name T871
Test name
Test status
Simulation time 433206723 ps
CPU time 1.69 seconds
Started Jul 06 07:02:54 PM PDT 24
Finished Jul 06 07:02:57 PM PDT 24
Peak memory 201408 kb
Host smart-d283e506-73ef-46d6-8e71-7a33491fe5ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302497484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.1302497484
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.184070698
Short name T128
Test name
Test status
Simulation time 2688735579 ps
CPU time 10.85 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:03:03 PM PDT 24
Peak memory 201604 kb
Host smart-379d5381-07a0-4c90-97dc-7d5148408f45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184070698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.184070698
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2626586512
Short name T817
Test name
Test status
Simulation time 570024408 ps
CPU time 2.76 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:56 PM PDT 24
Peak memory 201744 kb
Host smart-61579777-1900-46d7-9585-b47e31c03eb4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626586512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2626586512
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.1767007245
Short name T909
Test name
Test status
Simulation time 7816125325 ps
CPU time 11.01 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:03:04 PM PDT 24
Peak memory 201848 kb
Host smart-bb226594-f187-4258-a213-183c03e94513
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767007245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.1767007245
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1071055073
Short name T875
Test name
Test status
Simulation time 526870846 ps
CPU time 1.93 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:02:53 PM PDT 24
Peak memory 201608 kb
Host smart-38381a35-17a1-4c5c-bdf9-56ba22474dc8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071055073 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1071055073
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1044178384
Short name T132
Test name
Test status
Simulation time 446397947 ps
CPU time 1 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201524 kb
Host smart-ba6614b3-eb5a-4ad0-b11f-086b00975469
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044178384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1044178384
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2950983042
Short name T820
Test name
Test status
Simulation time 426770170 ps
CPU time 1 seconds
Started Jul 06 07:02:54 PM PDT 24
Finished Jul 06 07:02:56 PM PDT 24
Peak memory 201412 kb
Host smart-995d7c50-73b5-49ae-aab2-6780e6f8018e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950983042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2950983042
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.1259938214
Short name T886
Test name
Test status
Simulation time 4501390355 ps
CPU time 10.44 seconds
Started Jul 06 07:02:55 PM PDT 24
Finished Jul 06 07:03:06 PM PDT 24
Peak memory 201784 kb
Host smart-d7fba12c-059d-4ffd-84aa-14429cead56a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259938214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.1259938214
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3319429340
Short name T839
Test name
Test status
Simulation time 7803420050 ps
CPU time 19.49 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:03:11 PM PDT 24
Peak memory 201840 kb
Host smart-aa150104-a3ed-4cd9-b4f1-3130e60246cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319429340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3319429340
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3020209456
Short name T900
Test name
Test status
Simulation time 486734512 ps
CPU time 1.39 seconds
Started Jul 06 07:02:53 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201616 kb
Host smart-6d9bc93b-459d-4893-a534-fb3965b008a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020209456 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3020209456
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.478081981
Short name T112
Test name
Test status
Simulation time 445689315 ps
CPU time 1.29 seconds
Started Jul 06 07:02:53 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201540 kb
Host smart-fc31bbac-a114-4ef6-bec4-d19d75e185f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478081981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.478081981
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.3438926369
Short name T810
Test name
Test status
Simulation time 534689854 ps
CPU time 1.23 seconds
Started Jul 06 07:02:55 PM PDT 24
Finished Jul 06 07:02:57 PM PDT 24
Peak memory 201360 kb
Host smart-aba608ad-ee7a-4901-aeb2-998a7266bf34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438926369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.3438926369
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.161458455
Short name T52
Test name
Test status
Simulation time 4541150259 ps
CPU time 3.58 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:57 PM PDT 24
Peak memory 201900 kb
Host smart-dfed1611-3200-44e6-818a-0a7ae154257d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161458455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.161458455
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2683214062
Short name T857
Test name
Test status
Simulation time 358057147 ps
CPU time 2.29 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:02:54 PM PDT 24
Peak memory 209980 kb
Host smart-0ab3e4ff-ff8a-4475-a6c1-f417bff93889
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683214062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2683214062
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.2690530534
Short name T902
Test name
Test status
Simulation time 509364148 ps
CPU time 1.96 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201572 kb
Host smart-69744045-00ac-4724-b6f3-e623159a7c9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690530534 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.2690530534
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2095573461
Short name T878
Test name
Test status
Simulation time 419133240 ps
CPU time 1.55 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:02:54 PM PDT 24
Peak memory 201460 kb
Host smart-56696d70-b878-4dcc-b11a-65b786dea459
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095573461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2095573461
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2926695452
Short name T863
Test name
Test status
Simulation time 387929189 ps
CPU time 0.88 seconds
Started Jul 06 07:02:51 PM PDT 24
Finished Jul 06 07:02:53 PM PDT 24
Peak memory 201452 kb
Host smart-91e86f0d-b104-42ec-bd96-c64b7f5bcef8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926695452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2926695452
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.2356376956
Short name T904
Test name
Test status
Simulation time 2625051209 ps
CPU time 1.6 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 201588 kb
Host smart-ba6aa02d-3793-40c7-b38d-f2936324ebea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2356376956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.2356376956
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.2749607367
Short name T66
Test name
Test status
Simulation time 605058293 ps
CPU time 2.04 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 217628 kb
Host smart-f3dc5864-6d69-492d-b8dd-9b57ee54f37d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749607367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.2749607367
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3152755741
Short name T72
Test name
Test status
Simulation time 7973885303 ps
CPU time 9.87 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:03:03 PM PDT 24
Peak memory 201872 kb
Host smart-37f2811e-45b8-4710-b883-5d25a94ee9f5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152755741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3152755741
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2710496774
Short name T825
Test name
Test status
Simulation time 597796243 ps
CPU time 2.07 seconds
Started Jul 06 07:03:00 PM PDT 24
Finished Jul 06 07:03:03 PM PDT 24
Peak memory 201588 kb
Host smart-8fc9a438-0fe4-4bcc-9c56-be0199b564fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710496774 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2710496774
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3702917022
Short name T861
Test name
Test status
Simulation time 406015159 ps
CPU time 1 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:02:54 PM PDT 24
Peak memory 201480 kb
Host smart-26fe0107-c8a5-40ee-a258-eb4afa9d7535
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702917022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3702917022
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1196170195
Short name T809
Test name
Test status
Simulation time 360117785 ps
CPU time 1.08 seconds
Started Jul 06 07:02:56 PM PDT 24
Finished Jul 06 07:02:58 PM PDT 24
Peak memory 201448 kb
Host smart-57c94657-d424-4acc-89ec-f2b9c476551c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196170195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1196170195
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.118336232
Short name T859
Test name
Test status
Simulation time 1958362819 ps
CPU time 2.79 seconds
Started Jul 06 07:02:56 PM PDT 24
Finished Jul 06 07:02:59 PM PDT 24
Peak memory 201488 kb
Host smart-08e7b02b-93d7-4d28-8e0f-826c64d86cec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118336232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_c
trl_same_csr_outstanding.118336232
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.2741755355
Short name T71
Test name
Test status
Simulation time 643341097 ps
CPU time 4.07 seconds
Started Jul 06 07:02:50 PM PDT 24
Finished Jul 06 07:02:55 PM PDT 24
Peak memory 210004 kb
Host smart-ad57e60c-566b-4ac1-a6d5-0b53109605bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741755355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.2741755355
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2702383000
Short name T855
Test name
Test status
Simulation time 4026937258 ps
CPU time 9.75 seconds
Started Jul 06 07:02:52 PM PDT 24
Finished Jul 06 07:03:03 PM PDT 24
Peak memory 201784 kb
Host smart-45eedc66-fe1d-4e3d-89c5-a0021432c45a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702383000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2702383000
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3941709099
Short name T835
Test name
Test status
Simulation time 417851459 ps
CPU time 1.73 seconds
Started Jul 06 07:02:57 PM PDT 24
Finished Jul 06 07:03:00 PM PDT 24
Peak memory 201620 kb
Host smart-34f4e8c8-c8f6-4e6d-97a2-d3ccf2904e71
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941709099 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3941709099
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.288184551
Short name T127
Test name
Test status
Simulation time 583261836 ps
CPU time 0.84 seconds
Started Jul 06 07:03:02 PM PDT 24
Finished Jul 06 07:03:03 PM PDT 24
Peak memory 200860 kb
Host smart-50da12f3-9c9b-48aa-8083-fb275fbab6e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288184551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.288184551
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.419151532
Short name T818
Test name
Test status
Simulation time 339426436 ps
CPU time 1.36 seconds
Started Jul 06 07:02:56 PM PDT 24
Finished Jul 06 07:02:58 PM PDT 24
Peak memory 201480 kb
Host smart-3c5587d8-09f1-4e30-a978-e4ca7273f23a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419151532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.419151532
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.352733535
Short name T915
Test name
Test status
Simulation time 3906587705 ps
CPU time 15.23 seconds
Started Jul 06 07:03:01 PM PDT 24
Finished Jul 06 07:03:17 PM PDT 24
Peak memory 201776 kb
Host smart-70d3e971-058c-4e09-b855-899da677fce7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352733535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_c
trl_same_csr_outstanding.352733535
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3080615216
Short name T58
Test name
Test status
Simulation time 488820482 ps
CPU time 2.71 seconds
Started Jul 06 07:02:58 PM PDT 24
Finished Jul 06 07:03:02 PM PDT 24
Peak memory 217760 kb
Host smart-07e370ab-3362-4a91-ade1-b4c9c84fe520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080615216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3080615216
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.3621114294
Short name T827
Test name
Test status
Simulation time 4567210725 ps
CPU time 11.61 seconds
Started Jul 06 07:02:57 PM PDT 24
Finished Jul 06 07:03:10 PM PDT 24
Peak memory 201884 kb
Host smart-8ce8687d-3f52-44da-b4d0-cd47a3f42089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621114294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.3621114294
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1902917725
Short name T914
Test name
Test status
Simulation time 757062550 ps
CPU time 0.97 seconds
Started Jul 06 07:02:57 PM PDT 24
Finished Jul 06 07:02:59 PM PDT 24
Peak memory 201576 kb
Host smart-1ab61cf6-ebda-4262-ba5d-4d7aa67ff644
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902917725 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1902917725
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.34848202
Short name T113
Test name
Test status
Simulation time 560284405 ps
CPU time 1.32 seconds
Started Jul 06 07:03:02 PM PDT 24
Finished Jul 06 07:03:04 PM PDT 24
Peak memory 201524 kb
Host smart-fe3c5d0c-4372-4171-a783-e7631faef96e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34848202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.34848202
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.3859246186
Short name T887
Test name
Test status
Simulation time 559915763 ps
CPU time 0.95 seconds
Started Jul 06 07:02:58 PM PDT 24
Finished Jul 06 07:03:00 PM PDT 24
Peak memory 201420 kb
Host smart-becad967-6467-4f8a-8be3-c0c92d81bdb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859246186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.3859246186
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.3258483251
Short name T131
Test name
Test status
Simulation time 4851273089 ps
CPU time 19.08 seconds
Started Jul 06 07:03:01 PM PDT 24
Finished Jul 06 07:03:21 PM PDT 24
Peak memory 201744 kb
Host smart-305a6530-0cf4-4dfa-8a70-bba1aa788b44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258483251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.3258483251
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1372958969
Short name T830
Test name
Test status
Simulation time 682801363 ps
CPU time 1.78 seconds
Started Jul 06 07:03:02 PM PDT 24
Finished Jul 06 07:03:04 PM PDT 24
Peak memory 201160 kb
Host smart-278be8ba-5eb5-4654-87dd-25d3c289be07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372958969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1372958969
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.143696964
Short name T59
Test name
Test status
Simulation time 7946878346 ps
CPU time 19.95 seconds
Started Jul 06 07:02:57 PM PDT 24
Finished Jul 06 07:03:18 PM PDT 24
Peak memory 201820 kb
Host smart-c41fa032-c5f9-4086-962a-1937d25495f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143696964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.143696964
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2077050732
Short name T858
Test name
Test status
Simulation time 554378967 ps
CPU time 1.39 seconds
Started Jul 06 07:02:58 PM PDT 24
Finished Jul 06 07:03:00 PM PDT 24
Peak memory 201556 kb
Host smart-e342f67c-436d-4c06-b5c0-3c00897b4eda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077050732 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2077050732
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.4121372149
Short name T899
Test name
Test status
Simulation time 568401344 ps
CPU time 1.1 seconds
Started Jul 06 07:02:59 PM PDT 24
Finished Jul 06 07:03:01 PM PDT 24
Peak memory 201476 kb
Host smart-810e596c-9ba3-4a95-b40b-ea12e09553cb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121372149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.4121372149
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2732439942
Short name T869
Test name
Test status
Simulation time 321365481 ps
CPU time 0.86 seconds
Started Jul 06 07:03:00 PM PDT 24
Finished Jul 06 07:03:02 PM PDT 24
Peak memory 201444 kb
Host smart-178dc900-ee90-4e4e-8067-69b69ccaba4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732439942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2732439942
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3644038482
Short name T889
Test name
Test status
Simulation time 1822481794 ps
CPU time 4.2 seconds
Started Jul 06 07:02:59 PM PDT 24
Finished Jul 06 07:03:04 PM PDT 24
Peak memory 201516 kb
Host smart-ffff8ff2-4866-4216-ac0c-27d831f33e89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644038482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3644038482
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1653686651
Short name T829
Test name
Test status
Simulation time 373358350 ps
CPU time 2.54 seconds
Started Jul 06 07:03:00 PM PDT 24
Finished Jul 06 07:03:03 PM PDT 24
Peak memory 201708 kb
Host smart-73e82aa1-c1e8-49a9-8cb2-1de59cf6a92e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653686651 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1653686651
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3768978163
Short name T865
Test name
Test status
Simulation time 4243750349 ps
CPU time 11.9 seconds
Started Jul 06 07:02:59 PM PDT 24
Finished Jul 06 07:03:11 PM PDT 24
Peak memory 201828 kb
Host smart-5472bac0-0d4f-478d-9ce2-b55508d1b862
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768978163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3768978163
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.46895195
Short name T115
Test name
Test status
Simulation time 871080408 ps
CPU time 4.56 seconds
Started Jul 06 07:02:28 PM PDT 24
Finished Jul 06 07:02:34 PM PDT 24
Peak memory 201616 kb
Host smart-d020eaf2-537d-4bfd-a407-d5fe6ec8dc7f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46895195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_aliasi
ng.46895195
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.207135716
Short name T917
Test name
Test status
Simulation time 26456665812 ps
CPU time 89.56 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:03:58 PM PDT 24
Peak memory 201800 kb
Host smart-c38e27f2-9258-4d4e-9954-11abff559afa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207135716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_b
ash.207135716
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1750971871
Short name T846
Test name
Test status
Simulation time 761273083 ps
CPU time 1.1 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 201516 kb
Host smart-61f210a0-7bc6-4ea8-ad98-c34667f9b6fc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750971871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1750971871
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1530086772
Short name T815
Test name
Test status
Simulation time 606775143 ps
CPU time 1.45 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:29 PM PDT 24
Peak memory 201596 kb
Host smart-9b2c8975-2284-48de-9f95-695650f24857
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530086772 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1530086772
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.2120853063
Short name T117
Test name
Test status
Simulation time 377756719 ps
CPU time 1.11 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 201536 kb
Host smart-954c80a3-6a20-4423-a86f-d2908ddf45b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120853063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.2120853063
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1065624626
Short name T876
Test name
Test status
Simulation time 366022998 ps
CPU time 1.44 seconds
Started Jul 06 07:02:28 PM PDT 24
Finished Jul 06 07:02:31 PM PDT 24
Peak memory 201696 kb
Host smart-773ffedc-ba39-40fa-8c2d-e1ff63334bd5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065624626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1065624626
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2815119949
Short name T130
Test name
Test status
Simulation time 2205664683 ps
CPU time 8.61 seconds
Started Jul 06 07:02:29 PM PDT 24
Finished Jul 06 07:02:38 PM PDT 24
Peak memory 201544 kb
Host smart-6e074dc7-4d56-4fd1-af56-3be5847614b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815119949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2815119949
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1859591438
Short name T822
Test name
Test status
Simulation time 507404829 ps
CPU time 3.77 seconds
Started Jul 06 07:02:28 PM PDT 24
Finished Jul 06 07:02:33 PM PDT 24
Peak memory 211276 kb
Host smart-d9662cfd-ceef-4802-a1b4-bf9de976d103
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859591438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1859591438
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.1161114538
Short name T870
Test name
Test status
Simulation time 7860652764 ps
CPU time 12.16 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:41 PM PDT 24
Peak memory 201856 kb
Host smart-e65d02ba-b7c5-42c3-9383-e6d000bdc3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161114538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.1161114538
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.119302302
Short name T880
Test name
Test status
Simulation time 496592383 ps
CPU time 1.2 seconds
Started Jul 06 07:03:02 PM PDT 24
Finished Jul 06 07:03:04 PM PDT 24
Peak memory 201424 kb
Host smart-55c63235-a976-41ce-8638-d86ec2ec5e35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119302302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.119302302
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.2358640123
Short name T804
Test name
Test status
Simulation time 452888285 ps
CPU time 0.9 seconds
Started Jul 06 07:02:58 PM PDT 24
Finished Jul 06 07:03:00 PM PDT 24
Peak memory 201440 kb
Host smart-bb11d05d-598b-4573-a319-2d95d5401184
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358640123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.2358640123
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.2545371277
Short name T838
Test name
Test status
Simulation time 333164625 ps
CPU time 1.41 seconds
Started Jul 06 07:03:00 PM PDT 24
Finished Jul 06 07:03:02 PM PDT 24
Peak memory 201436 kb
Host smart-a655c9d1-7fb1-40e6-afdc-1d50d3d9a58b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545371277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.2545371277
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2995743152
Short name T816
Test name
Test status
Simulation time 407348709 ps
CPU time 1.13 seconds
Started Jul 06 07:02:59 PM PDT 24
Finished Jul 06 07:03:01 PM PDT 24
Peak memory 201392 kb
Host smart-9c76d2e8-69ae-40f8-b604-7b5222b132d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995743152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2995743152
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.1732259002
Short name T874
Test name
Test status
Simulation time 543730064 ps
CPU time 0.94 seconds
Started Jul 06 07:02:57 PM PDT 24
Finished Jul 06 07:03:00 PM PDT 24
Peak memory 201468 kb
Host smart-3bb34539-e89f-4587-b159-31ed1a196cd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732259002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.1732259002
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1961761638
Short name T801
Test name
Test status
Simulation time 340610613 ps
CPU time 1.04 seconds
Started Jul 06 07:02:58 PM PDT 24
Finished Jul 06 07:03:00 PM PDT 24
Peak memory 201416 kb
Host smart-4c4aeccb-b0b3-4a2a-98d1-3298557e627b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961761638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1961761638
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2906199233
Short name T916
Test name
Test status
Simulation time 313048276 ps
CPU time 1.41 seconds
Started Jul 06 07:03:02 PM PDT 24
Finished Jul 06 07:03:04 PM PDT 24
Peak memory 201452 kb
Host smart-dcbc5cb7-ca63-4b8e-96ed-8d7b8d2f2eca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906199233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2906199233
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2369607278
Short name T882
Test name
Test status
Simulation time 353159981 ps
CPU time 0.9 seconds
Started Jul 06 07:02:56 PM PDT 24
Finished Jul 06 07:02:57 PM PDT 24
Peak memory 201456 kb
Host smart-9cd1572e-4b93-4d4c-9c71-f6fdf308248b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369607278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2369607278
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2231101562
Short name T850
Test name
Test status
Simulation time 397365779 ps
CPU time 1.12 seconds
Started Jul 06 07:03:00 PM PDT 24
Finished Jul 06 07:03:02 PM PDT 24
Peak memory 201448 kb
Host smart-ca4f2bb3-0d84-45aa-a661-90f4f940a078
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231101562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2231101562
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1454746186
Short name T851
Test name
Test status
Simulation time 491968519 ps
CPU time 0.95 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:06 PM PDT 24
Peak memory 201444 kb
Host smart-c7901b57-ed4f-4869-9ed9-1d556bb82d59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454746186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1454746186
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4102286432
Short name T824
Test name
Test status
Simulation time 845952338 ps
CPU time 1.86 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:31 PM PDT 24
Peak memory 201976 kb
Host smart-b5d37fd7-df38-4518-84b5-6e0ea79d495a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102286432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4102286432
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.175048384
Short name T906
Test name
Test status
Simulation time 51756242689 ps
CPU time 108.17 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:04:15 PM PDT 24
Peak memory 201812 kb
Host smart-9895b493-8c20-4d42-8e36-e0d6fdffafd9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175048384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_b
ash.175048384
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.775436288
Short name T124
Test name
Test status
Simulation time 1218905084 ps
CPU time 2.08 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:30 PM PDT 24
Peak memory 201456 kb
Host smart-7e297555-c894-4157-85f0-06d130378d00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775436288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.775436288
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.882450005
Short name T88
Test name
Test status
Simulation time 547296549 ps
CPU time 2.1 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:31 PM PDT 24
Peak memory 201604 kb
Host smart-877ae1c4-b259-4c89-a9ce-eea90918136b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882450005 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.882450005
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.438461984
Short name T126
Test name
Test status
Simulation time 577229666 ps
CPU time 1.55 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:30 PM PDT 24
Peak memory 201448 kb
Host smart-2db9ab59-5a74-471b-b7f0-3c1a073af42b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438461984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.438461984
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.2281549550
Short name T811
Test name
Test status
Simulation time 522957014 ps
CPU time 1.81 seconds
Started Jul 06 07:02:28 PM PDT 24
Finished Jul 06 07:02:31 PM PDT 24
Peak memory 201424 kb
Host smart-c3b2ecf0-0b9c-4438-bf12-62c3e670499c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281549550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.2281549550
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.2937817935
Short name T879
Test name
Test status
Simulation time 2750075227 ps
CPU time 9.05 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:38 PM PDT 24
Peak memory 201596 kb
Host smart-ebb9a96f-eaeb-4a3f-b058-a6aae1951cfa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937817935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.2937817935
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.1455375472
Short name T842
Test name
Test status
Simulation time 602530299 ps
CPU time 2.65 seconds
Started Jul 06 07:02:25 PM PDT 24
Finished Jul 06 07:02:28 PM PDT 24
Peak memory 201788 kb
Host smart-c066f988-10d1-4bc1-be01-8a2150c25d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455375472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.1455375472
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.76170974
Short name T347
Test name
Test status
Simulation time 4470091420 ps
CPU time 12.47 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:39 PM PDT 24
Peak memory 201724 kb
Host smart-f23f8a58-66f0-4a46-bcc4-b9249ab4f059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76170974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_intg
_err.76170974
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1007845590
Short name T872
Test name
Test status
Simulation time 374124951 ps
CPU time 1.31 seconds
Started Jul 06 07:03:05 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201456 kb
Host smart-d4d24cbf-83db-4e83-bd31-2cd4980534b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007845590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1007845590
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3798618866
Short name T821
Test name
Test status
Simulation time 393897494 ps
CPU time 1.46 seconds
Started Jul 06 07:03:05 PM PDT 24
Finished Jul 06 07:03:08 PM PDT 24
Peak memory 201416 kb
Host smart-4406b7be-b523-4944-aeb8-ad5aec72c957
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798618866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3798618866
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.2023329635
Short name T860
Test name
Test status
Simulation time 431431559 ps
CPU time 0.9 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:06 PM PDT 24
Peak memory 201436 kb
Host smart-1e968a7c-4a09-4c3a-9b33-b2442d5db42f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023329635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.2023329635
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.4001521526
Short name T832
Test name
Test status
Simulation time 414195738 ps
CPU time 1.51 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201420 kb
Host smart-2bcfaeba-fe29-4558-9e2e-52032cec8d86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001521526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.4001521526
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.2378474034
Short name T864
Test name
Test status
Simulation time 425557131 ps
CPU time 1.13 seconds
Started Jul 06 07:03:05 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201480 kb
Host smart-f5f9c6a7-28f1-403b-98bf-16a02baed667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378474034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.2378474034
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3861960788
Short name T798
Test name
Test status
Simulation time 347006182 ps
CPU time 0.8 seconds
Started Jul 06 07:03:07 PM PDT 24
Finished Jul 06 07:03:09 PM PDT 24
Peak memory 201388 kb
Host smart-6ccdbbbf-8ad6-402b-af20-62f288e1ab5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861960788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3861960788
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2183760269
Short name T894
Test name
Test status
Simulation time 415767847 ps
CPU time 1.16 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:06 PM PDT 24
Peak memory 201440 kb
Host smart-6c6f3a06-ca73-4f48-92d4-3d6244d24d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183760269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2183760269
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.3215644635
Short name T885
Test name
Test status
Simulation time 298159845 ps
CPU time 1.3 seconds
Started Jul 06 07:03:06 PM PDT 24
Finished Jul 06 07:03:08 PM PDT 24
Peak memory 201440 kb
Host smart-af6188b9-d5e8-47a4-bd41-71ecc71d9bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215644635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.3215644635
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.344909691
Short name T826
Test name
Test status
Simulation time 631112846 ps
CPU time 0.75 seconds
Started Jul 06 07:03:05 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201472 kb
Host smart-a3f0ee27-cea1-41e4-9fe9-bb4c7dedd432
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344909691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.344909691
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.2086856928
Short name T898
Test name
Test status
Simulation time 297310408 ps
CPU time 1.34 seconds
Started Jul 06 07:03:07 PM PDT 24
Finished Jul 06 07:03:09 PM PDT 24
Peak memory 201388 kb
Host smart-f5d021a3-5f78-4098-bcf8-15267e26f059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086856928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.2086856928
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.1997582752
Short name T118
Test name
Test status
Simulation time 773307633 ps
CPU time 1.78 seconds
Started Jul 06 07:02:33 PM PDT 24
Finished Jul 06 07:02:35 PM PDT 24
Peak memory 201712 kb
Host smart-df628a12-de2b-441d-a423-83aee044b640
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997582752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.1997582752
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2902499334
Short name T123
Test name
Test status
Simulation time 27131214064 ps
CPU time 61.51 seconds
Started Jul 06 07:02:33 PM PDT 24
Finished Jul 06 07:03:36 PM PDT 24
Peak memory 201784 kb
Host smart-4cde46b9-bbad-4c44-ac63-a731da57ebb6
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902499334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2902499334
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3993047742
Short name T116
Test name
Test status
Simulation time 1301342254 ps
CPU time 3.46 seconds
Started Jul 06 07:02:26 PM PDT 24
Finished Jul 06 07:02:31 PM PDT 24
Peak memory 201512 kb
Host smart-234b5678-8341-4ed2-98a7-d4da5c9497b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993047742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3993047742
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2764966222
Short name T852
Test name
Test status
Simulation time 512496945 ps
CPU time 1.16 seconds
Started Jul 06 07:02:33 PM PDT 24
Finished Jul 06 07:02:35 PM PDT 24
Peak memory 201600 kb
Host smart-caab5581-7242-4be3-a692-8d4c96fb1a2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764966222 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2764966222
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.3019223698
Short name T114
Test name
Test status
Simulation time 580678823 ps
CPU time 1.12 seconds
Started Jul 06 07:02:34 PM PDT 24
Finished Jul 06 07:02:35 PM PDT 24
Peak memory 201508 kb
Host smart-1bcacded-88f8-4b19-9def-4b529c0e6df7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019223698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.3019223698
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1186687262
Short name T897
Test name
Test status
Simulation time 374697886 ps
CPU time 0.88 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:29 PM PDT 24
Peak memory 201456 kb
Host smart-e0bf7495-27a9-4f46-b68a-618aa7ff00a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186687262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1186687262
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2157680101
Short name T837
Test name
Test status
Simulation time 1579147536 ps
CPU time 2.72 seconds
Started Jul 06 07:02:36 PM PDT 24
Finished Jul 06 07:02:39 PM PDT 24
Peak memory 201488 kb
Host smart-02f9b4a1-9bcf-4102-a74e-176cc3603eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157680101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2157680101
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2303438933
Short name T833
Test name
Test status
Simulation time 554256784 ps
CPU time 2.62 seconds
Started Jul 06 07:02:28 PM PDT 24
Finished Jul 06 07:02:32 PM PDT 24
Peak memory 202072 kb
Host smart-22023625-86ee-4c7c-a0a5-a921f3c46d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303438933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2303438933
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.2026672560
Short name T60
Test name
Test status
Simulation time 4661079257 ps
CPU time 4.12 seconds
Started Jul 06 07:02:27 PM PDT 24
Finished Jul 06 07:02:33 PM PDT 24
Peak memory 201904 kb
Host smart-919badb3-f6a3-419a-a5c2-8ec154e3fee1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026672560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.2026672560
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.2995321501
Short name T908
Test name
Test status
Simulation time 320230475 ps
CPU time 1.32 seconds
Started Jul 06 07:03:06 PM PDT 24
Finished Jul 06 07:03:08 PM PDT 24
Peak memory 201396 kb
Host smart-bd552ef7-a5bb-4a1b-9339-0f0252ba7db7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995321501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.2995321501
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.520325364
Short name T873
Test name
Test status
Simulation time 372694281 ps
CPU time 1.38 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201372 kb
Host smart-a0c361db-509a-4802-aa16-5bdf8a1ceee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520325364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.520325364
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2924291412
Short name T881
Test name
Test status
Simulation time 491422192 ps
CPU time 1.09 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201360 kb
Host smart-3b48da79-4692-4c58-8d66-1cd5a6428d58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924291412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2924291412
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.1130139322
Short name T890
Test name
Test status
Simulation time 334852257 ps
CPU time 0.83 seconds
Started Jul 06 07:03:06 PM PDT 24
Finished Jul 06 07:03:08 PM PDT 24
Peak memory 201448 kb
Host smart-716075f2-ab7e-4b24-a098-27eb243e7ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130139322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.1130139322
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.137085914
Short name T907
Test name
Test status
Simulation time 410799466 ps
CPU time 1.56 seconds
Started Jul 06 07:03:03 PM PDT 24
Finished Jul 06 07:03:06 PM PDT 24
Peak memory 201428 kb
Host smart-6d87cd6f-84d8-4954-a087-de0c700d5c1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137085914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.137085914
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.2124948365
Short name T803
Test name
Test status
Simulation time 396217180 ps
CPU time 1.52 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:06 PM PDT 24
Peak memory 201408 kb
Host smart-d4145c3a-bd0b-4b30-91c8-e63db46680a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124948365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.2124948365
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.1927741326
Short name T823
Test name
Test status
Simulation time 532178568 ps
CPU time 1.26 seconds
Started Jul 06 07:03:07 PM PDT 24
Finished Jul 06 07:03:09 PM PDT 24
Peak memory 201448 kb
Host smart-715e7aae-fd6b-464b-9b24-95429c21e301
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927741326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.1927741326
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.976254804
Short name T840
Test name
Test status
Simulation time 340965338 ps
CPU time 1.42 seconds
Started Jul 06 07:03:06 PM PDT 24
Finished Jul 06 07:03:09 PM PDT 24
Peak memory 201440 kb
Host smart-a3e954b9-d3b9-4308-b134-574f0c449c22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976254804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.976254804
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.1707536156
Short name T854
Test name
Test status
Simulation time 349961765 ps
CPU time 1.4 seconds
Started Jul 06 07:03:04 PM PDT 24
Finished Jul 06 07:03:07 PM PDT 24
Peak memory 201460 kb
Host smart-42c4e548-2e39-4edc-8687-8218faf71060
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707536156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.1707536156
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.312895059
Short name T800
Test name
Test status
Simulation time 382140421 ps
CPU time 1.07 seconds
Started Jul 06 07:03:07 PM PDT 24
Finished Jul 06 07:03:09 PM PDT 24
Peak memory 201392 kb
Host smart-3a5d5b7a-f150-4878-9eea-6ba4bb3d5c3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312895059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.312895059
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.675837606
Short name T808
Test name
Test status
Simulation time 661715520 ps
CPU time 1.3 seconds
Started Jul 06 07:02:34 PM PDT 24
Finished Jul 06 07:02:36 PM PDT 24
Peak memory 201580 kb
Host smart-57732808-9d35-47d6-9999-295cea4283f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675837606 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.675837606
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1593695186
Short name T120
Test name
Test status
Simulation time 468994639 ps
CPU time 1.89 seconds
Started Jul 06 07:02:35 PM PDT 24
Finished Jul 06 07:02:38 PM PDT 24
Peak memory 201540 kb
Host smart-9192d514-2731-4b72-93ee-7e131e984494
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593695186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1593695186
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.78646158
Short name T802
Test name
Test status
Simulation time 347674044 ps
CPU time 0.82 seconds
Started Jul 06 07:02:33 PM PDT 24
Finished Jul 06 07:02:35 PM PDT 24
Peak memory 201408 kb
Host smart-eebd0344-dad4-4f49-b616-30bc0fd5c76c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78646158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.78646158
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1126129802
Short name T841
Test name
Test status
Simulation time 2189629446 ps
CPU time 7.24 seconds
Started Jul 06 07:02:30 PM PDT 24
Finished Jul 06 07:02:37 PM PDT 24
Peak memory 201644 kb
Host smart-392a6bd3-99a5-46c9-a5e0-8d5bc515c5b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126129802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1126129802
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.2385668527
Short name T69
Test name
Test status
Simulation time 383883986 ps
CPU time 2.42 seconds
Started Jul 06 07:02:35 PM PDT 24
Finished Jul 06 07:02:38 PM PDT 24
Peak memory 201816 kb
Host smart-a663d33e-d51f-482a-9158-c5e16f5e234d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385668527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.2385668527
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1274887962
Short name T866
Test name
Test status
Simulation time 8687434988 ps
CPU time 8 seconds
Started Jul 06 07:02:33 PM PDT 24
Finished Jul 06 07:02:42 PM PDT 24
Peak memory 201884 kb
Host smart-5b5bd929-05c4-4fb9-bd17-4d50ec1df5af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274887962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1274887962
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2353316529
Short name T813
Test name
Test status
Simulation time 365710654 ps
CPU time 1.71 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:41 PM PDT 24
Peak memory 201604 kb
Host smart-ed1d057d-9fbf-473b-827c-a44466cf6ef6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353316529 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2353316529
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1358249741
Short name T819
Test name
Test status
Simulation time 512858812 ps
CPU time 1.98 seconds
Started Jul 06 07:02:35 PM PDT 24
Finished Jul 06 07:02:38 PM PDT 24
Peak memory 201472 kb
Host smart-dfff9fce-cfb8-4850-aca6-40afbf58003c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358249741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1358249741
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.574271654
Short name T867
Test name
Test status
Simulation time 2539161906 ps
CPU time 3.15 seconds
Started Jul 06 07:02:33 PM PDT 24
Finished Jul 06 07:02:36 PM PDT 24
Peak memory 201688 kb
Host smart-46b62229-3f77-408e-8255-de5cf6b329c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574271654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ct
rl_same_csr_outstanding.574271654
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1171636686
Short name T913
Test name
Test status
Simulation time 553708099 ps
CPU time 3.75 seconds
Started Jul 06 07:02:32 PM PDT 24
Finished Jul 06 07:02:36 PM PDT 24
Peak memory 201808 kb
Host smart-697af6fe-24aa-4315-9cbf-bc674c4d7ccc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171636686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1171636686
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.3708720646
Short name T814
Test name
Test status
Simulation time 384161411 ps
CPU time 1.26 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:40 PM PDT 24
Peak memory 201548 kb
Host smart-3882f47f-bead-4553-be3f-43dc92c49d64
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708720646 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.3708720646
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2826287549
Short name T856
Test name
Test status
Simulation time 479297838 ps
CPU time 0.81 seconds
Started Jul 06 07:02:37 PM PDT 24
Finished Jul 06 07:02:38 PM PDT 24
Peak memory 201512 kb
Host smart-279f2678-53b3-4b70-99e0-bdd8ca9c576f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826287549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2826287549
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.1014336744
Short name T805
Test name
Test status
Simulation time 390517741 ps
CPU time 0.82 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:39 PM PDT 24
Peak memory 201424 kb
Host smart-b11c87a4-9746-488d-acbd-775efd8fc49f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014336744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.1014336744
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3173608909
Short name T918
Test name
Test status
Simulation time 2464522573 ps
CPU time 4.01 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:43 PM PDT 24
Peak memory 201604 kb
Host smart-43532649-59d1-4d85-b3dd-a2e719bfb3bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173608909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3173608909
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.4229415637
Short name T895
Test name
Test status
Simulation time 550482759 ps
CPU time 3.35 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:42 PM PDT 24
Peak memory 201820 kb
Host smart-43ee5416-102f-412b-885d-8edbd6f7ebba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229415637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.4229415637
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.2467024374
Short name T56
Test name
Test status
Simulation time 4445808638 ps
CPU time 6.6 seconds
Started Jul 06 07:02:39 PM PDT 24
Finished Jul 06 07:02:46 PM PDT 24
Peak memory 201872 kb
Host smart-b7f7be80-6f0b-4367-93e9-b315ed2b2acf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467024374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.2467024374
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1659700210
Short name T812
Test name
Test status
Simulation time 680283365 ps
CPU time 1.73 seconds
Started Jul 06 07:02:39 PM PDT 24
Finished Jul 06 07:02:41 PM PDT 24
Peak memory 201620 kb
Host smart-114856b9-2606-463e-9a11-487f2f39430a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659700210 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1659700210
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.793178148
Short name T912
Test name
Test status
Simulation time 496189728 ps
CPU time 0.85 seconds
Started Jul 06 07:02:40 PM PDT 24
Finished Jul 06 07:02:41 PM PDT 24
Peak memory 201504 kb
Host smart-547f0e6a-d8e3-4602-bd71-c416bb5c5ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793178148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.793178148
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.4180829782
Short name T828
Test name
Test status
Simulation time 430186255 ps
CPU time 0.9 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:40 PM PDT 24
Peak memory 201476 kb
Host smart-7f5a995b-3b05-49b3-9bae-5f903112963d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180829782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.4180829782
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2977328519
Short name T844
Test name
Test status
Simulation time 1960871364 ps
CPU time 4.27 seconds
Started Jul 06 07:02:40 PM PDT 24
Finished Jul 06 07:02:45 PM PDT 24
Peak memory 201472 kb
Host smart-7a311461-34e7-45f2-ab47-e47453702622
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977328519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2977328519
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2739430170
Short name T911
Test name
Test status
Simulation time 353503514 ps
CPU time 2.88 seconds
Started Jul 06 07:02:41 PM PDT 24
Finished Jul 06 07:02:44 PM PDT 24
Peak memory 217732 kb
Host smart-4ccf0f5d-b862-446f-86bd-f8ea44cebd0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739430170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2739430170
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.1703530037
Short name T54
Test name
Test status
Simulation time 4294199431 ps
CPU time 11.61 seconds
Started Jul 06 07:02:40 PM PDT 24
Finished Jul 06 07:02:52 PM PDT 24
Peak memory 201856 kb
Host smart-6ae77680-f522-4cf5-8eca-34cde3a45aa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703530037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.1703530037
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.4160390076
Short name T806
Test name
Test status
Simulation time 504008233 ps
CPU time 1.34 seconds
Started Jul 06 07:02:40 PM PDT 24
Finished Jul 06 07:02:42 PM PDT 24
Peak memory 201584 kb
Host smart-277257ad-d9f6-4ac4-8e15-1306a965c690
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160390076 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.4160390076
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1656192764
Short name T893
Test name
Test status
Simulation time 390709872 ps
CPU time 1.56 seconds
Started Jul 06 07:02:38 PM PDT 24
Finished Jul 06 07:02:40 PM PDT 24
Peak memory 201500 kb
Host smart-bf96f06f-3166-4493-96fd-954ccf7d20a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656192764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1656192764
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.495418814
Short name T896
Test name
Test status
Simulation time 507629511 ps
CPU time 1.79 seconds
Started Jul 06 07:02:40 PM PDT 24
Finished Jul 06 07:02:42 PM PDT 24
Peak memory 201448 kb
Host smart-80495bb9-80b5-4b50-86ce-d35b7de4313c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495418814 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.495418814
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2337347117
Short name T836
Test name
Test status
Simulation time 2279007183 ps
CPU time 8.88 seconds
Started Jul 06 07:02:41 PM PDT 24
Finished Jul 06 07:02:50 PM PDT 24
Peak memory 201632 kb
Host smart-00a33b65-1b84-4254-ad8c-313ec98e9b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337347117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2337347117
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.659495203
Short name T877
Test name
Test status
Simulation time 523275170 ps
CPU time 1.49 seconds
Started Jul 06 07:02:39 PM PDT 24
Finished Jul 06 07:02:41 PM PDT 24
Peak memory 201752 kb
Host smart-52a0e210-45a5-4101-8a1b-02e50a36b728
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659495203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.659495203
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3974716119
Short name T892
Test name
Test status
Simulation time 4185667966 ps
CPU time 11.07 seconds
Started Jul 06 07:02:41 PM PDT 24
Finished Jul 06 07:02:53 PM PDT 24
Peak memory 201836 kb
Host smart-2115774c-b893-41b6-b3c1-1d5db91af69d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974716119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3974716119
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.1928994987
Short name T344
Test name
Test status
Simulation time 354045222784 ps
CPU time 673.16 seconds
Started Jul 06 06:32:23 PM PDT 24
Finished Jul 06 06:43:36 PM PDT 24
Peak memory 201900 kb
Host smart-8eae9e33-68e4-4488-a299-da973eb1b474
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928994987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.1928994987
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.3303044890
Short name T415
Test name
Test status
Simulation time 491626252404 ps
CPU time 280.62 seconds
Started Jul 06 06:32:21 PM PDT 24
Finished Jul 06 06:37:02 PM PDT 24
Peak memory 201912 kb
Host smart-1421dad8-5355-4643-8cdb-959de4cd5713
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303044890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.3303044890
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2912944406
Short name T591
Test name
Test status
Simulation time 333078774698 ps
CPU time 383.03 seconds
Started Jul 06 06:32:20 PM PDT 24
Finished Jul 06 06:38:43 PM PDT 24
Peak memory 201876 kb
Host smart-682e7ead-ede7-4f0e-9731-45db16a96d0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912944406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2912944406
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.838411381
Short name T94
Test name
Test status
Simulation time 166322926779 ps
CPU time 89.47 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:33:56 PM PDT 24
Peak memory 201920 kb
Host smart-27fc140f-f9a4-497c-9738-9337d612032c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=838411381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.838411381
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.414891688
Short name T592
Test name
Test status
Simulation time 197515398260 ps
CPU time 468.4 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:40:11 PM PDT 24
Peak memory 201900 kb
Host smart-4a04a26a-2588-49b2-9961-48b652bcabb4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414891688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.a
dc_ctrl_filters_wakeup_fixed.414891688
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.1153452384
Short name T215
Test name
Test status
Simulation time 103187975274 ps
CPU time 569.68 seconds
Started Jul 06 06:32:20 PM PDT 24
Finished Jul 06 06:41:50 PM PDT 24
Peak memory 202244 kb
Host smart-751d6f01-e113-41b6-a928-2dedeab193df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153452384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.1153452384
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.2943980383
Short name T417
Test name
Test status
Simulation time 26377265271 ps
CPU time 16.16 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:32:39 PM PDT 24
Peak memory 201704 kb
Host smart-6ac049bc-3a13-441f-8a3f-6e542992459e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2943980383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.2943980383
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3840387549
Short name T379
Test name
Test status
Simulation time 5116011595 ps
CPU time 5.98 seconds
Started Jul 06 06:32:22 PM PDT 24
Finished Jul 06 06:32:29 PM PDT 24
Peak memory 201652 kb
Host smart-3f71bc6e-f459-4868-8758-b56c3e405cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840387549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3840387549
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3898940953
Short name T451
Test name
Test status
Simulation time 6040474450 ps
CPU time 3.93 seconds
Started Jul 06 06:32:24 PM PDT 24
Finished Jul 06 06:32:28 PM PDT 24
Peak memory 201724 kb
Host smart-1c772867-eb7d-403d-84fa-86c9b4e6ee50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898940953 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3898940953
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.2752844778
Short name T432
Test name
Test status
Simulation time 172405346763 ps
CPU time 963.85 seconds
Started Jul 06 06:32:21 PM PDT 24
Finished Jul 06 06:48:25 PM PDT 24
Peak memory 210416 kb
Host smart-624bbf34-a261-4594-97b4-67afd3428a5a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752844778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
2752844778
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.4155027467
Short name T240
Test name
Test status
Simulation time 443159867710 ps
CPU time 334.21 seconds
Started Jul 06 06:32:21 PM PDT 24
Finished Jul 06 06:37:56 PM PDT 24
Peak memory 217740 kb
Host smart-374451f5-3c5a-43f1-8bef-f90f8898a7e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155027467 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.4155027467
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.417895792
Short name T744
Test name
Test status
Simulation time 498942586 ps
CPU time 0.91 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:32:30 PM PDT 24
Peak memory 201632 kb
Host smart-e341e208-eb79-44e1-a000-94853f9b5f2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417895792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.417895792
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2604147387
Short name T698
Test name
Test status
Simulation time 161097251600 ps
CPU time 346.5 seconds
Started Jul 06 06:32:24 PM PDT 24
Finished Jul 06 06:38:11 PM PDT 24
Peak memory 201932 kb
Host smart-0bec72d3-fb0b-4130-a0c6-901ed7b14f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604147387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2604147387
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2743289919
Short name T413
Test name
Test status
Simulation time 161670329861 ps
CPU time 374.15 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:38:41 PM PDT 24
Peak memory 201844 kb
Host smart-c6b6aabb-8bac-4bf5-8efd-3b027548cb64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743289919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2743289919
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1162631210
Short name T137
Test name
Test status
Simulation time 493050130368 ps
CPU time 290.99 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:37:17 PM PDT 24
Peak memory 201880 kb
Host smart-dc6bdb74-914a-480a-b42c-bf422b010e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162631210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1162631210
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.3780498119
Short name T360
Test name
Test status
Simulation time 493497092937 ps
CPU time 1087.27 seconds
Started Jul 06 06:32:24 PM PDT 24
Finished Jul 06 06:50:32 PM PDT 24
Peak memory 201920 kb
Host smart-8edd6d7b-ce91-49dd-a700-3760f81fdf42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780498119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.3780498119
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3742215115
Short name T794
Test name
Test status
Simulation time 187938524528 ps
CPU time 434.72 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:39:41 PM PDT 24
Peak memory 201864 kb
Host smart-fc38fcde-e19c-4934-9543-4cb3839493ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742215115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3742215115
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.2610786317
Short name T634
Test name
Test status
Simulation time 196086071065 ps
CPU time 417.69 seconds
Started Jul 06 06:32:24 PM PDT 24
Finished Jul 06 06:39:23 PM PDT 24
Peak memory 201884 kb
Host smart-2e31df0f-c9ad-4f5f-90e0-b689f0bdcb87
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610786317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.2610786317
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.39385011
Short name T418
Test name
Test status
Simulation time 84298675945 ps
CPU time 350.18 seconds
Started Jul 06 06:32:23 PM PDT 24
Finished Jul 06 06:38:14 PM PDT 24
Peak memory 202152 kb
Host smart-456b6a60-3aa5-48ad-bbb2-d246294ffbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39385011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.39385011
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3175706556
Short name T77
Test name
Test status
Simulation time 31982787131 ps
CPU time 17.75 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:32:45 PM PDT 24
Peak memory 201708 kb
Host smart-ee9051a1-9fb2-49ec-9596-15c04a768e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175706556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3175706556
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.1326073709
Short name T739
Test name
Test status
Simulation time 3268589085 ps
CPU time 2.79 seconds
Started Jul 06 06:32:25 PM PDT 24
Finished Jul 06 06:32:29 PM PDT 24
Peak memory 201700 kb
Host smart-b0af6cd1-8aec-4a6c-af47-606e5fe13bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326073709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.1326073709
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.3796661639
Short name T63
Test name
Test status
Simulation time 4412703760 ps
CPU time 3.1 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:32:31 PM PDT 24
Peak memory 217180 kb
Host smart-55a47606-2f85-461b-ad8e-6ffd49fb3a05
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796661639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.3796661639
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.1720732059
Short name T510
Test name
Test status
Simulation time 6100670908 ps
CPU time 5.9 seconds
Started Jul 06 06:32:27 PM PDT 24
Finished Jul 06 06:32:33 PM PDT 24
Peak memory 201676 kb
Host smart-ebe9c012-7370-4c89-a32d-6efcc8039d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720732059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.1720732059
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.1775683521
Short name T351
Test name
Test status
Simulation time 277086245321 ps
CPU time 360.05 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:38:30 PM PDT 24
Peak memory 212484 kb
Host smart-bc7f9ef1-70ff-4cbb-b8fb-21d387dede05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775683521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
1775683521
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2085744927
Short name T784
Test name
Test status
Simulation time 330559481 ps
CPU time 1.27 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:32:49 PM PDT 24
Peak memory 201608 kb
Host smart-72b7ba67-61ea-4822-b5b2-eb56702eee13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085744927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2085744927
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3001148247
Short name T491
Test name
Test status
Simulation time 335757425638 ps
CPU time 678.96 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:44:18 PM PDT 24
Peak memory 201860 kb
Host smart-7c2429b4-f5f7-487a-b610-b15a05528d31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001148247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3001148247
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.316126205
Short name T289
Test name
Test status
Simulation time 330921608704 ps
CPU time 393.95 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:39:22 PM PDT 24
Peak memory 201864 kb
Host smart-ca240b81-95a3-45e6-99b2-15bbb3e8e5ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316126205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.316126205
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.1809989064
Short name T172
Test name
Test status
Simulation time 488462180162 ps
CPU time 311.87 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:37:53 PM PDT 24
Peak memory 201872 kb
Host smart-276ce02e-4a5e-4192-bc26-d979541d35f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809989064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.1809989064
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.871816284
Short name T249
Test name
Test status
Simulation time 332799242555 ps
CPU time 347.82 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:38:29 PM PDT 24
Peak memory 201880 kb
Host smart-b8bb2b38-25b3-4aa6-929e-8e228c11d034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871816284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.871816284
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3653972301
Short name T161
Test name
Test status
Simulation time 489303154146 ps
CPU time 259.74 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:37:01 PM PDT 24
Peak memory 201916 kb
Host smart-7a3c6356-8d4a-49c8-bcd9-58bb5c934957
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653972301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3653972301
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3469435181
Short name T701
Test name
Test status
Simulation time 403005714716 ps
CPU time 975.17 seconds
Started Jul 06 06:33:00 PM PDT 24
Finished Jul 06 06:49:16 PM PDT 24
Peak memory 201900 kb
Host smart-ae77510a-53de-4b99-92f5-04f6fe099fb5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469435181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3469435181
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3227742318
Short name T447
Test name
Test status
Simulation time 76941081926 ps
CPU time 323.87 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:38:04 PM PDT 24
Peak memory 202544 kb
Host smart-e9f0eed2-4934-4fa9-9a2b-7befa770d59b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227742318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3227742318
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.2764819601
Short name T718
Test name
Test status
Simulation time 44389581408 ps
CPU time 94.01 seconds
Started Jul 06 06:32:39 PM PDT 24
Finished Jul 06 06:34:14 PM PDT 24
Peak memory 201972 kb
Host smart-cbe3f7df-9a38-402d-a836-fcca105f32fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764819601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.2764819601
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.4201483158
Short name T593
Test name
Test status
Simulation time 3014258933 ps
CPU time 3.76 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:32:44 PM PDT 24
Peak memory 201732 kb
Host smart-2edead86-b3f5-41c2-a571-9fe0f613f3f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201483158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.4201483158
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.93119386
Short name T677
Test name
Test status
Simulation time 5947984396 ps
CPU time 4.09 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:32:53 PM PDT 24
Peak memory 201688 kb
Host smart-15ddec9f-c9d9-4450-a786-057e89f94ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93119386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.93119386
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1481341403
Short name T300
Test name
Test status
Simulation time 457100358648 ps
CPU time 765.24 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:45:45 PM PDT 24
Peak memory 210416 kb
Host smart-3ff9d9db-61ca-44a6-9a64-ddcc9ee0a417
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481341403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1481341403
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.3401530103
Short name T380
Test name
Test status
Simulation time 364428514 ps
CPU time 0.87 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:32:49 PM PDT 24
Peak memory 201628 kb
Host smart-ca989116-bd77-4486-ae27-75b2c9ba7a7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401530103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.3401530103
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.929403083
Short name T761
Test name
Test status
Simulation time 168096459965 ps
CPU time 105.65 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:34:33 PM PDT 24
Peak memory 201988 kb
Host smart-eacc6892-6423-4c20-a30f-3688a43dbbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929403083 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.929403083
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1598655452
Short name T7
Test name
Test status
Simulation time 168126833297 ps
CPU time 110.47 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:34:35 PM PDT 24
Peak memory 201912 kb
Host smart-a06f2176-5e39-4f47-8a61-3fc2f2fe8b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598655452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1598655452
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.1849344643
Short name T654
Test name
Test status
Simulation time 165036979204 ps
CPU time 372.02 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:39:01 PM PDT 24
Peak memory 201884 kb
Host smart-da5d85af-f78e-42d4-9808-5c8913020b5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849344643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.1849344643
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3790187687
Short name T178
Test name
Test status
Simulation time 490612710192 ps
CPU time 74.3 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:34:01 PM PDT 24
Peak memory 201960 kb
Host smart-aa538e17-762c-4702-8183-895b7b2fd74b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790187687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3790187687
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.1756111714
Short name T508
Test name
Test status
Simulation time 165331217781 ps
CPU time 113.28 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:34:41 PM PDT 24
Peak memory 201980 kb
Host smart-e37de8fa-efcf-485c-bd5c-352d8935d50e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756111714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.1756111714
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.2862384443
Short name T296
Test name
Test status
Simulation time 377039375754 ps
CPU time 198.43 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:36:18 PM PDT 24
Peak memory 201916 kb
Host smart-35bff62c-bf1f-4d21-a55e-09d454cb953e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862384443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.2862384443
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.2096311408
Short name T213
Test name
Test status
Simulation time 104666440372 ps
CPU time 545.53 seconds
Started Jul 06 06:32:46 PM PDT 24
Finished Jul 06 06:41:52 PM PDT 24
Peak memory 202176 kb
Host smart-cc582e5c-351a-4787-80e6-61be53b1413d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096311408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.2096311408
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.443134852
Short name T574
Test name
Test status
Simulation time 40858640194 ps
CPU time 5.73 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:32:51 PM PDT 24
Peak memory 201728 kb
Host smart-162af4b6-3e50-43da-a651-895908d31ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443134852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.443134852
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.1022780142
Short name T624
Test name
Test status
Simulation time 4375211981 ps
CPU time 3.38 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:33:03 PM PDT 24
Peak memory 201660 kb
Host smart-9d6b6a45-837f-4855-937f-03a3518ea446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1022780142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.1022780142
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2816697656
Short name T436
Test name
Test status
Simulation time 5998876810 ps
CPU time 4.37 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:32:46 PM PDT 24
Peak memory 201716 kb
Host smart-03236a84-c53e-4d5c-abe3-5c5c6df80d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816697656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2816697656
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.3318409720
Short name T372
Test name
Test status
Simulation time 9405576184 ps
CPU time 11.19 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:33:01 PM PDT 24
Peak memory 201728 kb
Host smart-8b561c52-26a6-4035-a9e9-87be1bcda1c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318409720 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.3318409720
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.143850634
Short name T345
Test name
Test status
Simulation time 135062125455 ps
CPU time 120.5 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:34:46 PM PDT 24
Peak memory 210492 kb
Host smart-f9b41ce6-feba-44c1-9605-93656cd74e6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143850634 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.143850634
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.153964209
Short name T561
Test name
Test status
Simulation time 345896605 ps
CPU time 0.8 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:32:48 PM PDT 24
Peak memory 201684 kb
Host smart-ba23ed86-782f-4ff6-b860-c42ccfa5e022
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153964209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.153964209
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1328784789
Short name T155
Test name
Test status
Simulation time 485585755171 ps
CPU time 259.56 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:37:11 PM PDT 24
Peak memory 201988 kb
Host smart-9cddd6ec-da31-429a-ae49-ddfb1848f396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328784789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1328784789
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1565808028
Short name T434
Test name
Test status
Simulation time 323875621509 ps
CPU time 487.5 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:40:54 PM PDT 24
Peak memory 201900 kb
Host smart-4bbd0bd4-e7fb-46f8-9e5e-46276da250cb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565808028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1565808028
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.4149133098
Short name T3
Test name
Test status
Simulation time 497870362172 ps
CPU time 575.85 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:42:22 PM PDT 24
Peak memory 201888 kb
Host smart-ffa09732-faa0-452e-b3ac-0f68ee0e1f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4149133098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.4149133098
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1705213976
Short name T196
Test name
Test status
Simulation time 159336015526 ps
CPU time 365.56 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:38:51 PM PDT 24
Peak memory 201908 kb
Host smart-cd77ac94-40f6-4164-b1b9-e24690069ec7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705213976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1705213976
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.3786958271
Short name T135
Test name
Test status
Simulation time 377006114402 ps
CPU time 107.55 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:34:37 PM PDT 24
Peak memory 201896 kb
Host smart-05b70663-5560-4ef8-96c8-31923d91e7e6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786958271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.3786958271
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.699054380
Short name T420
Test name
Test status
Simulation time 613376036058 ps
CPU time 289.72 seconds
Started Jul 06 06:32:46 PM PDT 24
Finished Jul 06 06:37:36 PM PDT 24
Peak memory 201868 kb
Host smart-a2587407-951b-4de2-bae2-33699d541396
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699054380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.699054380
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.205109956
Short name T562
Test name
Test status
Simulation time 71446703675 ps
CPU time 301.95 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:37:47 PM PDT 24
Peak memory 202160 kb
Host smart-a15847c2-ba16-4416-bdc7-9924c44577e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205109956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.205109956
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2761637927
Short name T795
Test name
Test status
Simulation time 24343512542 ps
CPU time 48.79 seconds
Started Jul 06 06:32:46 PM PDT 24
Finished Jul 06 06:33:35 PM PDT 24
Peak memory 201652 kb
Host smart-86ddf361-8979-44bd-8ec2-bc9e2048186a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761637927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2761637927
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.764127595
Short name T82
Test name
Test status
Simulation time 3949805985 ps
CPU time 9.12 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:33:01 PM PDT 24
Peak memory 201732 kb
Host smart-a4f2af30-82dc-4b1e-a156-a96a638937d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764127595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.764127595
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.940434976
Short name T554
Test name
Test status
Simulation time 6061065761 ps
CPU time 15.38 seconds
Started Jul 06 06:32:46 PM PDT 24
Finished Jul 06 06:33:01 PM PDT 24
Peak memory 201736 kb
Host smart-bf000d10-0516-4c74-8fdc-0c65060533ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940434976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.940434976
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2405643163
Short name T325
Test name
Test status
Simulation time 166940132024 ps
CPU time 367.09 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:38:54 PM PDT 24
Peak memory 201868 kb
Host smart-f7535c75-22ac-448e-8a1a-cccdf491366b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405643163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2405643163
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1363663311
Short name T258
Test name
Test status
Simulation time 229576862681 ps
CPU time 276.63 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:37:25 PM PDT 24
Peak memory 218236 kb
Host smart-59c110cc-e3b7-4377-a4ee-bde8fdada50a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363663311 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1363663311
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2451346252
Short name T42
Test name
Test status
Simulation time 367990873 ps
CPU time 0.84 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:32:51 PM PDT 24
Peak memory 201680 kb
Host smart-2dafa1e3-5450-47ad-94ac-9d1600b444fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2451346252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2451346252
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.798641236
Short name T185
Test name
Test status
Simulation time 492415417523 ps
CPU time 281.82 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:37:34 PM PDT 24
Peak memory 201904 kb
Host smart-55154302-2401-493b-bbea-5420ce4ddb04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798641236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.798641236
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3097820105
Short name T551
Test name
Test status
Simulation time 162419454909 ps
CPU time 355.97 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:38:45 PM PDT 24
Peak memory 201904 kb
Host smart-ef0bceb2-69ad-4728-b3a8-f68e14d7cd84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097820105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3097820105
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1303322913
Short name T745
Test name
Test status
Simulation time 484148719153 ps
CPU time 1084.49 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:50:55 PM PDT 24
Peak memory 201912 kb
Host smart-a6c00016-46ce-4f68-b0ad-e9911868933a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303322913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1303322913
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3323784586
Short name T28
Test name
Test status
Simulation time 172749226252 ps
CPU time 102.35 seconds
Started Jul 06 06:32:45 PM PDT 24
Finished Jul 06 06:34:28 PM PDT 24
Peak memory 201960 kb
Host smart-c52d061e-dc0e-4a4e-8e0c-2fad0d9686c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323784586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3323784586
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.2701899177
Short name T370
Test name
Test status
Simulation time 163640501783 ps
CPU time 347.79 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:38:35 PM PDT 24
Peak memory 201948 kb
Host smart-73ab32c8-306b-4a16-acd8-148d72097477
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701899177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.2701899177
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3605634415
Short name T621
Test name
Test status
Simulation time 533214845810 ps
CPU time 636.81 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:43:29 PM PDT 24
Peak memory 201868 kb
Host smart-168a8598-5555-4d4f-b871-d1c6ce55b500
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605634415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3605634415
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.289921330
Short name T34
Test name
Test status
Simulation time 584716289128 ps
CPU time 1314.7 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:54:45 PM PDT 24
Peak memory 201932 kb
Host smart-37492457-ad51-44e1-a34c-8f3cb8cc757a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289921330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.289921330
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3512624721
Short name T48
Test name
Test status
Simulation time 71625719724 ps
CPU time 259.89 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:37:10 PM PDT 24
Peak memory 202208 kb
Host smart-34af9e6b-29f7-4c3f-b4d5-12b681dd5ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512624721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3512624721
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.611479118
Short name T462
Test name
Test status
Simulation time 34735127107 ps
CPU time 16.45 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:33:09 PM PDT 24
Peak memory 201724 kb
Host smart-72c53279-aa6f-46fa-babb-94f15f33d2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611479118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.611479118
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.1574502725
Short name T511
Test name
Test status
Simulation time 5064977548 ps
CPU time 13.25 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:33:05 PM PDT 24
Peak memory 201696 kb
Host smart-249f2368-a8b4-4c97-ae81-663269f5c1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574502725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.1574502725
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.2058839684
Short name T680
Test name
Test status
Simulation time 5790699416 ps
CPU time 12.99 seconds
Started Jul 06 06:32:47 PM PDT 24
Finished Jul 06 06:33:01 PM PDT 24
Peak memory 201708 kb
Host smart-5f91ba17-9095-46ca-968c-38831407b253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058839684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.2058839684
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1912625608
Short name T448
Test name
Test status
Simulation time 36141433216 ps
CPU time 24.29 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:33:14 PM PDT 24
Peak memory 201724 kb
Host smart-fe35acb0-fe01-4bd4-8bc0-c1e88d3a7072
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912625608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1912625608
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.1713455053
Short name T645
Test name
Test status
Simulation time 560832697 ps
CPU time 0.91 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:32:50 PM PDT 24
Peak memory 201652 kb
Host smart-3bc5005e-51c3-4a23-bce9-0c6225127880
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713455053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.1713455053
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.2628689654
Short name T24
Test name
Test status
Simulation time 163981204219 ps
CPU time 109.84 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:34:40 PM PDT 24
Peak memory 201932 kb
Host smart-feb8ee14-af2c-4cdf-a785-88bdc835a9f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628689654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.2628689654
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.393226396
Short name T714
Test name
Test status
Simulation time 359523959495 ps
CPU time 198.49 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:36:10 PM PDT 24
Peak memory 201852 kb
Host smart-a2beeca5-f320-440c-a565-307ce1609ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393226396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.393226396
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.3648684967
Short name T22
Test name
Test status
Simulation time 165711794603 ps
CPU time 364.32 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:38:53 PM PDT 24
Peak memory 201984 kb
Host smart-b072418a-9a7c-4ced-b055-1f2bc4135e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648684967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.3648684967
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.276162541
Short name T782
Test name
Test status
Simulation time 491028210399 ps
CPU time 1156.79 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:52:08 PM PDT 24
Peak memory 201892 kb
Host smart-bc2c0ab6-66fc-4e7b-b76d-141b7a838834
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=276162541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.276162541
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.266639415
Short name T246
Test name
Test status
Simulation time 490895780346 ps
CPU time 1055.2 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:50:25 PM PDT 24
Peak memory 202000 kb
Host smart-3abcd33b-2345-4008-809b-ba1a19a002fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266639415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.266639415
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.373847311
Short name T423
Test name
Test status
Simulation time 165087388346 ps
CPU time 361.19 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:38:52 PM PDT 24
Peak memory 201908 kb
Host smart-536b2e92-f906-4248-b075-069d0cb03771
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=373847311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.373847311
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.2226531464
Short name T473
Test name
Test status
Simulation time 173211503628 ps
CPU time 348.23 seconds
Started Jul 06 06:32:53 PM PDT 24
Finished Jul 06 06:38:41 PM PDT 24
Peak memory 201932 kb
Host smart-587295d4-ae17-4657-97ad-8db46e000d80
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226531464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.2226531464
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.3056155387
Short name T43
Test name
Test status
Simulation time 202601631517 ps
CPU time 138.92 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:35:10 PM PDT 24
Peak memory 201948 kb
Host smart-5b7d4c91-ed24-41c6-88c4-816b46edc587
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056155387 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.3056155387
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.2503560870
Short name T783
Test name
Test status
Simulation time 63826059663 ps
CPU time 268.84 seconds
Started Jul 06 06:32:51 PM PDT 24
Finished Jul 06 06:37:20 PM PDT 24
Peak memory 202200 kb
Host smart-6e1b2d34-5175-4d3b-b9b8-1dd6fba584fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503560870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.2503560870
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.494208677
Short name T696
Test name
Test status
Simulation time 40452734681 ps
CPU time 95.08 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:34:27 PM PDT 24
Peak memory 201720 kb
Host smart-382d4671-02c5-4842-b43e-16ef6bf77c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494208677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.494208677
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3770263043
Short name T387
Test name
Test status
Simulation time 4762831398 ps
CPU time 3.23 seconds
Started Jul 06 06:33:01 PM PDT 24
Finished Jul 06 06:33:04 PM PDT 24
Peak memory 201656 kb
Host smart-c79cdfdb-0428-4e1a-b8f7-4ddffe9165c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770263043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3770263043
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1880684402
Short name T89
Test name
Test status
Simulation time 5613226522 ps
CPU time 6.89 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:32:59 PM PDT 24
Peak memory 201692 kb
Host smart-4213f704-4dc1-4f4d-8eb9-228f3c726f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880684402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1880684402
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.2903004722
Short name T223
Test name
Test status
Simulation time 453436600885 ps
CPU time 517.01 seconds
Started Jul 06 06:32:49 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 210420 kb
Host smart-984b5d8b-eddb-4150-ac26-2ed6cbdfbced
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903004722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.2903004722
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.1399835662
Short name T644
Test name
Test status
Simulation time 389375789 ps
CPU time 1.49 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:33:00 PM PDT 24
Peak memory 201668 kb
Host smart-1da6b582-05a5-4bca-b915-fd207a95fe4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399835662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.1399835662
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.2662598001
Short name T516
Test name
Test status
Simulation time 168517095694 ps
CPU time 398.33 seconds
Started Jul 06 06:32:54 PM PDT 24
Finished Jul 06 06:39:32 PM PDT 24
Peak memory 201896 kb
Host smart-5f5ec770-eb65-4ad8-844c-5a6ab590817e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662598001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.2662598001
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.3706308498
Short name T259
Test name
Test status
Simulation time 168005523028 ps
CPU time 117.39 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:34:55 PM PDT 24
Peak memory 201840 kb
Host smart-74619a18-9eec-4258-8aff-6f6abdf47264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706308498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.3706308498
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1163927394
Short name T527
Test name
Test status
Simulation time 327671349982 ps
CPU time 710.33 seconds
Started Jul 06 06:32:53 PM PDT 24
Finished Jul 06 06:44:43 PM PDT 24
Peak memory 201880 kb
Host smart-6fe6d62e-a034-48d5-ac57-0d503ed88d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163927394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1163927394
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2341974000
Short name T499
Test name
Test status
Simulation time 493008427198 ps
CPU time 1186.09 seconds
Started Jul 06 06:32:55 PM PDT 24
Finished Jul 06 06:52:42 PM PDT 24
Peak memory 201876 kb
Host smart-dba6a3c1-1033-4ee9-b68a-f77d85b9b030
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341974000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2341974000
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.3290792048
Short name T152
Test name
Test status
Simulation time 496603158724 ps
CPU time 1084.75 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:51:03 PM PDT 24
Peak memory 201872 kb
Host smart-b0a04482-9d51-41dc-900d-3edeb550d02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290792048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.3290792048
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.594342602
Short name T503
Test name
Test status
Simulation time 158975796765 ps
CPU time 86.64 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:34:24 PM PDT 24
Peak memory 201876 kb
Host smart-1ebb68da-65fe-4e98-abdb-0f2e52eedf44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=594342602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.594342602
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3323485077
Short name T255
Test name
Test status
Simulation time 590082008602 ps
CPU time 655.54 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:43:48 PM PDT 24
Peak memory 201916 kb
Host smart-9c038294-e66b-4572-9cde-d5e7046ee4db
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323485077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3323485077
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4178325894
Short name T570
Test name
Test status
Simulation time 203725822645 ps
CPU time 468.64 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:40:47 PM PDT 24
Peak memory 201840 kb
Host smart-359f5909-424f-45ec-9ece-e78ed7cc1c97
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178325894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4178325894
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.4099937571
Short name T458
Test name
Test status
Simulation time 101177637945 ps
CPU time 503.39 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:41:21 PM PDT 24
Peak memory 202168 kb
Host smart-c4922826-189b-44ef-985c-d846eae26cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099937571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.4099937571
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1402488949
Short name T595
Test name
Test status
Simulation time 40388795415 ps
CPU time 22.95 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:33:21 PM PDT 24
Peak memory 201708 kb
Host smart-3d14a7fb-7ec7-4b11-84b9-6a7fc7a64b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402488949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1402488949
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2507325809
Short name T87
Test name
Test status
Simulation time 3867381781 ps
CPU time 9.13 seconds
Started Jul 06 06:32:53 PM PDT 24
Finished Jul 06 06:33:03 PM PDT 24
Peak memory 201692 kb
Host smart-3a6d5d78-e6eb-4a1c-8661-ecfdb3dfbd70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507325809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2507325809
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.4104258616
Short name T25
Test name
Test status
Simulation time 5837727786 ps
CPU time 7.78 seconds
Started Jul 06 06:32:54 PM PDT 24
Finished Jul 06 06:33:02 PM PDT 24
Peak memory 201724 kb
Host smart-111e1dd9-987a-4fa6-b13f-c2a9826c3cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104258616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.4104258616
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1076588110
Short name T67
Test name
Test status
Simulation time 163065930865 ps
CPU time 80.83 seconds
Started Jul 06 06:32:55 PM PDT 24
Finished Jul 06 06:34:16 PM PDT 24
Peak memory 201912 kb
Host smart-5ff9e53e-080c-4ed2-b3e3-4deb48fee3ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076588110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1076588110
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.862021278
Short name T269
Test name
Test status
Simulation time 108958655725 ps
CPU time 134.64 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:35:13 PM PDT 24
Peak memory 210764 kb
Host smart-38eb22c4-b69b-4fc3-ab30-f89175d1511a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862021278 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.862021278
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.598109963
Short name T407
Test name
Test status
Simulation time 445484630 ps
CPU time 1.6 seconds
Started Jul 06 06:32:56 PM PDT 24
Finished Jul 06 06:32:58 PM PDT 24
Peak memory 201660 kb
Host smart-ae46ce2b-7b8e-400b-a1eb-c1717a3c165e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598109963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.598109963
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.931136756
Short name T323
Test name
Test status
Simulation time 338058703429 ps
CPU time 84.96 seconds
Started Jul 06 06:32:54 PM PDT 24
Finished Jul 06 06:34:19 PM PDT 24
Peak memory 201956 kb
Host smart-b7e4941c-8157-4f35-9b2f-bb93ccb402e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931136756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gati
ng.931136756
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.2097777360
Short name T268
Test name
Test status
Simulation time 327538714766 ps
CPU time 762.72 seconds
Started Jul 06 06:32:56 PM PDT 24
Finished Jul 06 06:45:39 PM PDT 24
Peak memory 201976 kb
Host smart-7238bdc2-6e69-4080-bad4-f0cff2cb480c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097777360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.2097777360
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.3294918465
Short name T385
Test name
Test status
Simulation time 166354289522 ps
CPU time 190.29 seconds
Started Jul 06 06:32:56 PM PDT 24
Finished Jul 06 06:36:07 PM PDT 24
Peak memory 201848 kb
Host smart-c95824b0-649d-449d-a479-7c251d4b94dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294918465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.3294918465
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.1407383798
Short name T294
Test name
Test status
Simulation time 485524519099 ps
CPU time 709.35 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:44:47 PM PDT 24
Peak memory 201868 kb
Host smart-59459e2e-ab57-4c35-a355-973991622fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407383798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.1407383798
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1853577382
Short name T356
Test name
Test status
Simulation time 330025469770 ps
CPU time 720.43 seconds
Started Jul 06 06:32:53 PM PDT 24
Finished Jul 06 06:44:54 PM PDT 24
Peak memory 201968 kb
Host smart-21de86c7-7fcc-4927-bc66-98457d86ccf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853577382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1853577382
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1298942662
Short name T600
Test name
Test status
Simulation time 200907000693 ps
CPU time 419.45 seconds
Started Jul 06 06:32:54 PM PDT 24
Finished Jul 06 06:39:54 PM PDT 24
Peak memory 201880 kb
Host smart-e7b824ff-7012-4766-a05b-4d02d8c3e488
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298942662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1298942662
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1535390922
Short name T675
Test name
Test status
Simulation time 120612678166 ps
CPU time 435.89 seconds
Started Jul 06 06:32:55 PM PDT 24
Finished Jul 06 06:40:11 PM PDT 24
Peak memory 202248 kb
Host smart-6afe7aa0-ec23-499a-b738-ed52af7b97f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535390922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1535390922
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.3992771532
Short name T497
Test name
Test status
Simulation time 25286697732 ps
CPU time 27.1 seconds
Started Jul 06 06:32:56 PM PDT 24
Finished Jul 06 06:33:23 PM PDT 24
Peak memory 201728 kb
Host smart-9e1611b9-59f5-4d13-b09c-976aeaf1dc11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992771532 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.3992771532
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3647231402
Short name T536
Test name
Test status
Simulation time 4246467425 ps
CPU time 1.92 seconds
Started Jul 06 06:32:52 PM PDT 24
Finished Jul 06 06:32:54 PM PDT 24
Peak memory 201732 kb
Host smart-2c19afd5-ca36-40ab-a66e-ffc8ed0b3523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647231402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3647231402
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.3092116307
Short name T463
Test name
Test status
Simulation time 5783149204 ps
CPU time 4.27 seconds
Started Jul 06 06:32:55 PM PDT 24
Finished Jul 06 06:33:00 PM PDT 24
Peak memory 201752 kb
Host smart-f0ed7f95-74fc-4b25-85dc-cb55de3d521d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092116307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.3092116307
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.1419436093
Short name T604
Test name
Test status
Simulation time 434645152240 ps
CPU time 1302.31 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:54:41 PM PDT 24
Peak memory 210400 kb
Host smart-185d1fa4-5f07-4a35-b278-4c6f28352fce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419436093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.1419436093
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.4093792269
Short name T774
Test name
Test status
Simulation time 232184609313 ps
CPU time 137.63 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:35:14 PM PDT 24
Peak memory 210536 kb
Host smart-4a9e0183-45bf-46fd-b2c2-55da16326fa3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093792269 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.4093792269
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.2385996384
Short name T638
Test name
Test status
Simulation time 358890085 ps
CPU time 1 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:32:59 PM PDT 24
Peak memory 201688 kb
Host smart-42317263-0eaf-4c82-8151-8f90bd8dc64d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385996384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.2385996384
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1187608344
Short name T133
Test name
Test status
Simulation time 182813347933 ps
CPU time 394.06 seconds
Started Jul 06 06:33:00 PM PDT 24
Finished Jul 06 06:39:34 PM PDT 24
Peak memory 201976 kb
Host smart-46b4daaf-daa9-4c43-9a2a-5ad4c55c4bad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187608344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1187608344
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1079996910
Short name T660
Test name
Test status
Simulation time 361425247570 ps
CPU time 823.39 seconds
Started Jul 06 06:33:01 PM PDT 24
Finished Jul 06 06:46:45 PM PDT 24
Peak memory 201872 kb
Host smart-9c9b0a8d-2657-4613-93b2-12e91e51e06c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079996910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1079996910
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2608705060
Short name T313
Test name
Test status
Simulation time 162765256305 ps
CPU time 75.67 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:34:14 PM PDT 24
Peak memory 201908 kb
Host smart-f6ceaeb7-6ef8-44ec-98c7-6e2bf1a03eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608705060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2608705060
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2452935224
Short name T382
Test name
Test status
Simulation time 326142160092 ps
CPU time 204.1 seconds
Started Jul 06 06:32:54 PM PDT 24
Finished Jul 06 06:36:19 PM PDT 24
Peak memory 201904 kb
Host smart-af121596-63b4-4732-b705-0452cf4297d9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452935224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2452935224
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3669596566
Short name T637
Test name
Test status
Simulation time 160137937176 ps
CPU time 174.49 seconds
Started Jul 06 06:32:56 PM PDT 24
Finished Jul 06 06:35:51 PM PDT 24
Peak memory 201988 kb
Host smart-9ab8c6b8-67ac-45c2-9b64-0ae2f8c1edab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669596566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3669596566
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.2866098136
Short name T86
Test name
Test status
Simulation time 491792278354 ps
CPU time 279.37 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:37:38 PM PDT 24
Peak memory 201900 kb
Host smart-d8809538-4685-4fef-9949-1366c35fcc9b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866098136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.2866098136
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2005133658
Short name T271
Test name
Test status
Simulation time 523033184115 ps
CPU time 169.39 seconds
Started Jul 06 06:32:55 PM PDT 24
Finished Jul 06 06:35:45 PM PDT 24
Peak memory 201988 kb
Host smart-afcf443f-c176-4dbc-9609-9c83919fc2ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005133658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2005133658
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2885834226
Short name T467
Test name
Test status
Simulation time 197856424511 ps
CPU time 152.28 seconds
Started Jul 06 06:33:00 PM PDT 24
Finished Jul 06 06:35:33 PM PDT 24
Peak memory 201896 kb
Host smart-6f430272-9d68-43f0-ac30-71513935eeae
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885834226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2885834226
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1569995567
Short name T205
Test name
Test status
Simulation time 81333632217 ps
CPU time 284.41 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:37:44 PM PDT 24
Peak memory 202208 kb
Host smart-0244af1d-5cfa-4103-8058-00639ed32378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569995567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1569995567
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.70913573
Short name T563
Test name
Test status
Simulation time 37691659067 ps
CPU time 22.69 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:33:21 PM PDT 24
Peak memory 201716 kb
Host smart-9a43397c-5c55-4796-839a-091e229a5502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70913573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.70913573
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2225227270
Short name T465
Test name
Test status
Simulation time 5090400404 ps
CPU time 3.8 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:33:03 PM PDT 24
Peak memory 201728 kb
Host smart-fb0e9737-2cb3-48e5-a6be-728be6de43ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225227270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2225227270
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.3652297980
Short name T23
Test name
Test status
Simulation time 6122389747 ps
CPU time 5.2 seconds
Started Jul 06 06:32:53 PM PDT 24
Finished Jul 06 06:32:59 PM PDT 24
Peak memory 201740 kb
Host smart-59f27a8f-6888-427a-aca8-4f2d9c633798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652297980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.3652297980
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.4220173203
Short name T566
Test name
Test status
Simulation time 534997590470 ps
CPU time 485.5 seconds
Started Jul 06 06:33:00 PM PDT 24
Finished Jul 06 06:41:06 PM PDT 24
Peak memory 201920 kb
Host smart-d953cfeb-cbea-4386-a9ec-6e00bb67a3a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220173203 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.4220173203
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1589855339
Short name T537
Test name
Test status
Simulation time 579123929335 ps
CPU time 400.51 seconds
Started Jul 06 06:32:57 PM PDT 24
Finished Jul 06 06:39:38 PM PDT 24
Peak memory 210580 kb
Host smart-c08ef6dd-8e44-4111-b099-8f399176998a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589855339 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1589855339
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.999007253
Short name T712
Test name
Test status
Simulation time 506057517 ps
CPU time 0.72 seconds
Started Jul 06 06:33:05 PM PDT 24
Finished Jul 06 06:33:06 PM PDT 24
Peak memory 201668 kb
Host smart-8fbfee20-ffc9-4549-9a41-611e44e7804d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999007253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.999007253
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4231353361
Short name T295
Test name
Test status
Simulation time 515722887236 ps
CPU time 939.94 seconds
Started Jul 06 06:33:05 PM PDT 24
Finished Jul 06 06:48:45 PM PDT 24
Peak memory 201920 kb
Host smart-4d79e9cd-d5e6-4e0e-a89e-6f839bb2a000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231353361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4231353361
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2304016424
Short name T279
Test name
Test status
Simulation time 332385854528 ps
CPU time 129.76 seconds
Started Jul 06 06:33:03 PM PDT 24
Finished Jul 06 06:35:13 PM PDT 24
Peak memory 201928 kb
Host smart-12396a5f-0fb1-4add-8c94-2ce5d4e85551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304016424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2304016424
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1907033615
Short name T90
Test name
Test status
Simulation time 498440332194 ps
CPU time 263.37 seconds
Started Jul 06 06:33:03 PM PDT 24
Finished Jul 06 06:37:26 PM PDT 24
Peak memory 201864 kb
Host smart-3c554ea5-55c4-483d-a1a3-b5974d2e6997
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907033615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1907033615
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.3436504405
Short name T375
Test name
Test status
Simulation time 170798930510 ps
CPU time 34.38 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:33:34 PM PDT 24
Peak memory 201968 kb
Host smart-4d64605c-2a60-4dce-a9e7-5b6401f14d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436504405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.3436504405
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2858136186
Short name T797
Test name
Test status
Simulation time 326836991296 ps
CPU time 99.6 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:34:38 PM PDT 24
Peak memory 201920 kb
Host smart-3cc46b70-5b94-45ee-8325-bd32928b4d19
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858136186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2858136186
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.947723529
Short name T768
Test name
Test status
Simulation time 173882142383 ps
CPU time 408.26 seconds
Started Jul 06 06:33:01 PM PDT 24
Finished Jul 06 06:39:49 PM PDT 24
Peak memory 201988 kb
Host smart-4af4df7b-9be0-4431-b155-6ebc5a9b2cd7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947723529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.947723529
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.1608057694
Short name T464
Test name
Test status
Simulation time 588855204334 ps
CPU time 168.05 seconds
Started Jul 06 06:33:00 PM PDT 24
Finished Jul 06 06:35:49 PM PDT 24
Peak memory 201888 kb
Host smart-c789f08a-e09d-4d05-bea1-79129fe3e349
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608057694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.1608057694
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.700539204
Short name T765
Test name
Test status
Simulation time 122830348822 ps
CPU time 381.41 seconds
Started Jul 06 06:33:03 PM PDT 24
Finished Jul 06 06:39:24 PM PDT 24
Peak memory 202152 kb
Host smart-e65d05ae-59e5-4e0a-9bee-faebcc8f1887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700539204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.700539204
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.773273324
Short name T450
Test name
Test status
Simulation time 41247337366 ps
CPU time 90.44 seconds
Started Jul 06 06:33:03 PM PDT 24
Finished Jul 06 06:34:34 PM PDT 24
Peak memory 201716 kb
Host smart-2c0f19e0-68c7-4e81-a3d6-d09694ae0563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773273324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.773273324
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.538185903
Short name T388
Test name
Test status
Simulation time 4731725164 ps
CPU time 6.54 seconds
Started Jul 06 06:33:03 PM PDT 24
Finished Jul 06 06:33:10 PM PDT 24
Peak memory 201720 kb
Host smart-703066db-a19e-47c1-aae3-03bc4a4e254e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538185903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.538185903
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.3734484554
Short name T557
Test name
Test status
Simulation time 5979515028 ps
CPU time 14.09 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:33:13 PM PDT 24
Peak memory 201720 kb
Host smart-44d6c385-ad4c-4730-abe2-225bbacf0601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734484554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.3734484554
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4180286292
Short name T309
Test name
Test status
Simulation time 660438287427 ps
CPU time 1642.76 seconds
Started Jul 06 06:33:08 PM PDT 24
Finished Jul 06 07:00:31 PM PDT 24
Peak memory 201908 kb
Host smart-32346a68-fbdf-4c0a-be38-59bf023915e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180286292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4180286292
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1580476211
Short name T36
Test name
Test status
Simulation time 152916738422 ps
CPU time 34.65 seconds
Started Jul 06 06:33:08 PM PDT 24
Finished Jul 06 06:33:43 PM PDT 24
Peak memory 210288 kb
Host smart-3cf7dd2a-884d-495e-8f10-9d8220d4828e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580476211 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1580476211
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.1274190378
Short name T702
Test name
Test status
Simulation time 319223404 ps
CPU time 1.35 seconds
Started Jul 06 06:33:15 PM PDT 24
Finished Jul 06 06:33:17 PM PDT 24
Peak memory 201640 kb
Host smart-f59ecb24-33f3-4378-982a-b13779d935db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274190378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.1274190378
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1437092446
Short name T341
Test name
Test status
Simulation time 166149813725 ps
CPU time 93.56 seconds
Started Jul 06 06:33:10 PM PDT 24
Finished Jul 06 06:34:44 PM PDT 24
Peak memory 201916 kb
Host smart-3e4cc0ab-b79d-436b-a61e-e57878835136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437092446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1437092446
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.2561082265
Short name T184
Test name
Test status
Simulation time 321789527265 ps
CPU time 199.09 seconds
Started Jul 06 06:33:07 PM PDT 24
Finished Jul 06 06:36:26 PM PDT 24
Peak memory 201936 kb
Host smart-70f4c3a5-7d4d-4c34-9534-b05fbace626f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561082265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.2561082265
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3398631184
Short name T742
Test name
Test status
Simulation time 325652674898 ps
CPU time 195.7 seconds
Started Jul 06 06:33:10 PM PDT 24
Finished Jul 06 06:36:25 PM PDT 24
Peak memory 201832 kb
Host smart-2d50b401-85e2-454f-a01e-cf01f0aaf833
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398631184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3398631184
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1081078368
Short name T728
Test name
Test status
Simulation time 165901037489 ps
CPU time 145.05 seconds
Started Jul 06 06:33:07 PM PDT 24
Finished Jul 06 06:35:33 PM PDT 24
Peak memory 201924 kb
Host smart-3aae1c42-5705-48c3-ae5b-bb427ab792c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081078368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1081078368
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.27910394
Short name T433
Test name
Test status
Simulation time 489499312904 ps
CPU time 190.41 seconds
Started Jul 06 06:33:07 PM PDT 24
Finished Jul 06 06:36:18 PM PDT 24
Peak memory 201948 kb
Host smart-70093cb0-efd2-49f8-8eaf-7c815ba0caeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=27910394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixed
.27910394
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.218731954
Short name T406
Test name
Test status
Simulation time 608696304241 ps
CPU time 201.99 seconds
Started Jul 06 06:33:10 PM PDT 24
Finished Jul 06 06:36:32 PM PDT 24
Peak memory 201864 kb
Host smart-4c213e91-50b8-4ffe-886f-bb860e2948a2
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218731954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.
adc_ctrl_filters_wakeup_fixed.218731954
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2173723285
Short name T377
Test name
Test status
Simulation time 22278831648 ps
CPU time 6.79 seconds
Started Jul 06 06:33:09 PM PDT 24
Finished Jul 06 06:33:16 PM PDT 24
Peak memory 201732 kb
Host smart-e5e42859-484f-4c6b-a082-c0bc8be3ca71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173723285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2173723285
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.387230579
Short name T636
Test name
Test status
Simulation time 3732121900 ps
CPU time 2.66 seconds
Started Jul 06 06:33:11 PM PDT 24
Finished Jul 06 06:33:14 PM PDT 24
Peak memory 201728 kb
Host smart-8b38ead0-0021-4f7f-964f-af6a5779b957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387230579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.387230579
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.1340889092
Short name T397
Test name
Test status
Simulation time 5530102914 ps
CPU time 14.25 seconds
Started Jul 06 06:33:07 PM PDT 24
Finished Jul 06 06:33:21 PM PDT 24
Peak memory 201748 kb
Host smart-4a7a07a8-c669-4686-b3b2-5c9c81f69b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340889092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.1340889092
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.36665846
Short name T719
Test name
Test status
Simulation time 426731518332 ps
CPU time 823.38 seconds
Started Jul 06 06:33:14 PM PDT 24
Finished Jul 06 06:46:58 PM PDT 24
Peak memory 201904 kb
Host smart-81a95d1b-1d2f-4398-b2cc-b8c4c8819992
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36665846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.36665846
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.777362170
Short name T214
Test name
Test status
Simulation time 127003537421 ps
CPU time 296.77 seconds
Started Jul 06 06:33:15 PM PDT 24
Finished Jul 06 06:38:12 PM PDT 24
Peak memory 210504 kb
Host smart-18adf4c0-cfa1-456c-a9a9-a04647be1e26
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777362170 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.777362170
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.2841054486
Short name T560
Test name
Test status
Simulation time 378344512 ps
CPU time 0.83 seconds
Started Jul 06 06:32:30 PM PDT 24
Finished Jul 06 06:32:32 PM PDT 24
Peak memory 201688 kb
Host smart-cefde406-aca5-481d-baca-ec0869087198
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841054486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.2841054486
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1156594740
Short name T270
Test name
Test status
Simulation time 410730290298 ps
CPU time 458.61 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:40:05 PM PDT 24
Peak memory 201908 kb
Host smart-ea24e5a1-2cbd-4473-b4d1-ba26e227a94c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156594740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1156594740
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.3884391454
Short name T230
Test name
Test status
Simulation time 390621792606 ps
CPU time 900.63 seconds
Started Jul 06 06:32:25 PM PDT 24
Finished Jul 06 06:47:26 PM PDT 24
Peak memory 201996 kb
Host smart-1980b734-5a73-40f4-bfc5-8ff0b101c859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884391454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.3884391454
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.3929153076
Short name T331
Test name
Test status
Simulation time 498487443815 ps
CPU time 1235.14 seconds
Started Jul 06 06:32:25 PM PDT 24
Finished Jul 06 06:53:01 PM PDT 24
Peak memory 201908 kb
Host smart-b52283ad-10f4-4559-b2ce-22bf7337b732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929153076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.3929153076
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.3406034295
Short name T629
Test name
Test status
Simulation time 322039355913 ps
CPU time 395.55 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:39:02 PM PDT 24
Peak memory 201852 kb
Host smart-0c792137-bf86-4601-8ad6-42ea237d6621
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406034295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.3406034295
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.734641057
Short name T26
Test name
Test status
Simulation time 484780906702 ps
CPU time 629.86 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 201940 kb
Host smart-8da969e8-606d-4e96-b999-363855eaf871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734641057 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.734641057
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.4115874148
Short name T692
Test name
Test status
Simulation time 324404839449 ps
CPU time 86.62 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:33:53 PM PDT 24
Peak memory 201864 kb
Host smart-1d350f4f-ae7a-46a7-aae2-822a24b85ead
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115874148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.4115874148
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.2501534420
Short name T386
Test name
Test status
Simulation time 394108617854 ps
CPU time 940.36 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:48:07 PM PDT 24
Peak memory 201900 kb
Host smart-f916397c-4da6-4f8c-a4c8-b86eb4039463
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501534420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.2501534420
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.2221418805
Short name T349
Test name
Test status
Simulation time 116937059389 ps
CPU time 667.84 seconds
Started Jul 06 06:32:25 PM PDT 24
Finished Jul 06 06:43:33 PM PDT 24
Peak memory 202212 kb
Host smart-707a9374-ba12-4fbf-8b97-eb81307a5934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221418805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.2221418805
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.981052831
Short name T678
Test name
Test status
Simulation time 40488204709 ps
CPU time 84.96 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:33:51 PM PDT 24
Peak memory 201708 kb
Host smart-211676ba-9f0e-4a32-8d95-819d883b72d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981052831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.981052831
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.1949760599
Short name T683
Test name
Test status
Simulation time 5287621814 ps
CPU time 6.77 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:32:35 PM PDT 24
Peak memory 201752 kb
Host smart-e0e9a787-2494-4f2c-94de-6a6e9309f0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949760599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.1949760599
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.1944252604
Short name T76
Test name
Test status
Simulation time 4171275052 ps
CPU time 6.9 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:32:35 PM PDT 24
Peak memory 217288 kb
Host smart-05dec24c-e223-4e8a-b6dc-9e8b7751a7d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944252604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.1944252604
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.149773421
Short name T547
Test name
Test status
Simulation time 5895574605 ps
CPU time 14.13 seconds
Started Jul 06 06:32:27 PM PDT 24
Finished Jul 06 06:32:41 PM PDT 24
Peak memory 201732 kb
Host smart-a98abf9c-d093-491d-a1d8-f1ccf8021ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149773421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.149773421
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.3089642160
Short name T32
Test name
Test status
Simulation time 531580561416 ps
CPU time 325.38 seconds
Started Jul 06 06:32:30 PM PDT 24
Finished Jul 06 06:37:56 PM PDT 24
Peak memory 202004 kb
Host smart-b64cb6fe-2152-48c3-adb6-0353ac450324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089642160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
3089642160
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.763836102
Short name T469
Test name
Test status
Simulation time 443084149 ps
CPU time 1.21 seconds
Started Jul 06 06:33:19 PM PDT 24
Finished Jul 06 06:33:21 PM PDT 24
Peak memory 201708 kb
Host smart-6bd6e951-db23-4deb-8acc-f953e952e10e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763836102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.763836102
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.2618948395
Short name T775
Test name
Test status
Simulation time 179752725436 ps
CPU time 425.37 seconds
Started Jul 06 06:33:18 PM PDT 24
Finished Jul 06 06:40:23 PM PDT 24
Peak memory 201912 kb
Host smart-f998ec9c-8fc0-4f87-b898-e898b6213f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618948395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.2618948395
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2793860830
Short name T431
Test name
Test status
Simulation time 165612352136 ps
CPU time 389.35 seconds
Started Jul 06 06:33:14 PM PDT 24
Finished Jul 06 06:39:44 PM PDT 24
Peak memory 201904 kb
Host smart-82f6312b-b28e-42e9-b042-38ee6837ec65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793860830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2793860830
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2375587750
Short name T362
Test name
Test status
Simulation time 485992922022 ps
CPU time 580.23 seconds
Started Jul 06 06:33:16 PM PDT 24
Finished Jul 06 06:42:56 PM PDT 24
Peak memory 201884 kb
Host smart-417342b1-ef70-43ad-9127-197328081b1e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375587750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2375587750
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.891291924
Short name T796
Test name
Test status
Simulation time 484797174828 ps
CPU time 1060.37 seconds
Started Jul 06 06:33:14 PM PDT 24
Finished Jul 06 06:50:55 PM PDT 24
Peak memory 202012 kb
Host smart-98f5f72a-f4f7-40f2-8a31-e138aaccebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891291924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.891291924
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3572127325
Short name T594
Test name
Test status
Simulation time 165103418015 ps
CPU time 189.32 seconds
Started Jul 06 06:33:15 PM PDT 24
Finished Jul 06 06:36:24 PM PDT 24
Peak memory 201908 kb
Host smart-3300f03a-ba36-4e67-90e2-50dd0dc41ba8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572127325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3572127325
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3060333126
Short name T242
Test name
Test status
Simulation time 346498109350 ps
CPU time 309.94 seconds
Started Jul 06 06:33:16 PM PDT 24
Finished Jul 06 06:38:26 PM PDT 24
Peak memory 201996 kb
Host smart-0012fe96-7997-4adf-a805-cee23ee32927
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060333126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3060333126
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.2198450537
Short name T648
Test name
Test status
Simulation time 597606113302 ps
CPU time 1265.86 seconds
Started Jul 06 06:33:16 PM PDT 24
Finished Jul 06 06:54:22 PM PDT 24
Peak memory 201908 kb
Host smart-ccf1587e-844d-4bdf-bab6-c615d4b4a12a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198450537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.2198450537
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.2148664180
Short name T504
Test name
Test status
Simulation time 70687999117 ps
CPU time 242.46 seconds
Started Jul 06 06:33:19 PM PDT 24
Finished Jul 06 06:37:22 PM PDT 24
Peak memory 202208 kb
Host smart-fd1eef7c-7239-4028-aebc-8fdc397f94b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148664180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.2148664180
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1433627816
Short name T531
Test name
Test status
Simulation time 30856001617 ps
CPU time 33.12 seconds
Started Jul 06 06:33:17 PM PDT 24
Finished Jul 06 06:33:50 PM PDT 24
Peak memory 201720 kb
Host smart-87cf0019-e377-447f-8e1b-86b264fad0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433627816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1433627816
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.2886958452
Short name T754
Test name
Test status
Simulation time 3800767922 ps
CPU time 8.82 seconds
Started Jul 06 06:33:16 PM PDT 24
Finished Jul 06 06:33:25 PM PDT 24
Peak memory 201680 kb
Host smart-a93a7ed8-2b85-420c-903f-84137ead627e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886958452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.2886958452
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.2577860082
Short name T475
Test name
Test status
Simulation time 6057581155 ps
CPU time 1.88 seconds
Started Jul 06 06:33:18 PM PDT 24
Finished Jul 06 06:33:20 PM PDT 24
Peak memory 201748 kb
Host smart-346e2493-1208-4eba-9252-56dd5494a738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577860082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.2577860082
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.937882021
Short name T581
Test name
Test status
Simulation time 164475254829 ps
CPU time 352.91 seconds
Started Jul 06 06:33:18 PM PDT 24
Finished Jul 06 06:39:12 PM PDT 24
Peak memory 201900 kb
Host smart-3fb3cdb9-1c1d-4cfc-adaf-2e4c1dd7eedb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937882021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
937882021
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.1828800134
Short name T98
Test name
Test status
Simulation time 228851366475 ps
CPU time 308.44 seconds
Started Jul 06 06:33:20 PM PDT 24
Finished Jul 06 06:38:28 PM PDT 24
Peak memory 210532 kb
Host smart-12e23aa0-8f7a-4ec2-b610-f26c3619822d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828800134 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.1828800134
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3152104124
Short name T541
Test name
Test status
Simulation time 586966156 ps
CPU time 0.67 seconds
Started Jul 06 06:33:27 PM PDT 24
Finished Jul 06 06:33:27 PM PDT 24
Peak memory 201600 kb
Host smart-0e65b977-3f32-4935-904a-2166e03bf24b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152104124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3152104124
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1828192446
Short name T174
Test name
Test status
Simulation time 180584683534 ps
CPU time 101.51 seconds
Started Jul 06 06:33:22 PM PDT 24
Finished Jul 06 06:35:04 PM PDT 24
Peak memory 201948 kb
Host smart-c36a9e83-ef09-4bc6-9e7a-40b767dd44cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828192446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1828192446
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.3802466278
Short name T328
Test name
Test status
Simulation time 493337101773 ps
CPU time 1135.46 seconds
Started Jul 06 06:33:29 PM PDT 24
Finished Jul 06 06:52:25 PM PDT 24
Peak memory 201980 kb
Host smart-ef0c9d1b-7b43-4e01-9dfc-70dca34b4c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802466278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.3802466278
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2525688499
Short name T1
Test name
Test status
Simulation time 334505049448 ps
CPU time 195.34 seconds
Started Jul 06 06:33:22 PM PDT 24
Finished Jul 06 06:36:38 PM PDT 24
Peak memory 201908 kb
Host smart-fca18f01-24ce-4218-868e-d098db9a3944
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525688499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2525688499
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.2285902985
Short name T158
Test name
Test status
Simulation time 322932759110 ps
CPU time 152.82 seconds
Started Jul 06 06:33:18 PM PDT 24
Finished Jul 06 06:35:51 PM PDT 24
Peak memory 201900 kb
Host smart-43d1a867-6f89-4de9-bf05-0c469ef5d28b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285902985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.2285902985
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.2788639768
Short name T302
Test name
Test status
Simulation time 184960591797 ps
CPU time 41.68 seconds
Started Jul 06 06:33:26 PM PDT 24
Finished Jul 06 06:34:08 PM PDT 24
Peak memory 201912 kb
Host smart-65e116fd-1999-4c18-8190-cc6bfadc366b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788639768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.2788639768
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.111512726
Short name T443
Test name
Test status
Simulation time 602514216493 ps
CPU time 316.67 seconds
Started Jul 06 06:33:23 PM PDT 24
Finished Jul 06 06:38:40 PM PDT 24
Peak memory 201936 kb
Host smart-88961cf2-1e09-4b95-855a-1d189292db2f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111512726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.
adc_ctrl_filters_wakeup_fixed.111512726
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1101199132
Short name T472
Test name
Test status
Simulation time 124339976903 ps
CPU time 414.62 seconds
Started Jul 06 06:33:25 PM PDT 24
Finished Jul 06 06:40:20 PM PDT 24
Peak memory 202240 kb
Host smart-50c75436-d15a-4be8-bbe2-614ec8cbe086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101199132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1101199132
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.607523233
Short name T502
Test name
Test status
Simulation time 26191374321 ps
CPU time 15.9 seconds
Started Jul 06 06:33:24 PM PDT 24
Finished Jul 06 06:33:40 PM PDT 24
Peak memory 201736 kb
Host smart-730481ce-fee1-434c-9c6a-f6144a4162d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607523233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.607523233
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1265105161
Short name T777
Test name
Test status
Simulation time 4491043798 ps
CPU time 10.99 seconds
Started Jul 06 06:33:28 PM PDT 24
Finished Jul 06 06:33:39 PM PDT 24
Peak memory 201656 kb
Host smart-b4fc0b62-d035-45e0-91db-d326302261a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265105161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1265105161
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.2642248559
Short name T478
Test name
Test status
Simulation time 6005220009 ps
CPU time 4.22 seconds
Started Jul 06 06:33:18 PM PDT 24
Finished Jul 06 06:33:22 PM PDT 24
Peak memory 201676 kb
Host smart-6f36e427-d1fb-4e7b-9188-9ee2eba7b616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642248559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.2642248559
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3238861028
Short name T671
Test name
Test status
Simulation time 178573112271 ps
CPU time 378.47 seconds
Started Jul 06 06:33:27 PM PDT 24
Finished Jul 06 06:39:46 PM PDT 24
Peak memory 201956 kb
Host smart-940ece71-6571-47ba-89dd-9653753ce72a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238861028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3238861028
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.484093106
Short name T430
Test name
Test status
Simulation time 348741087 ps
CPU time 1.36 seconds
Started Jul 06 06:33:35 PM PDT 24
Finished Jul 06 06:33:36 PM PDT 24
Peak memory 201628 kb
Host smart-a64a6b38-635d-486a-8933-100862561b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484093106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.484093106
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1491798424
Short name T416
Test name
Test status
Simulation time 166782981143 ps
CPU time 56.55 seconds
Started Jul 06 06:33:28 PM PDT 24
Finished Jul 06 06:34:24 PM PDT 24
Peak memory 201924 kb
Host smart-343fd9d1-0535-41a5-84a8-6059cf185106
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491798424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1491798424
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3933665600
Short name T179
Test name
Test status
Simulation time 357611002353 ps
CPU time 224.91 seconds
Started Jul 06 06:33:28 PM PDT 24
Finished Jul 06 06:37:13 PM PDT 24
Peak memory 201872 kb
Host smart-8beef30f-3691-478e-93e5-c14090399c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933665600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3933665600
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.2478328477
Short name T310
Test name
Test status
Simulation time 318816124509 ps
CPU time 674.37 seconds
Started Jul 06 06:33:27 PM PDT 24
Finished Jul 06 06:44:41 PM PDT 24
Peak memory 201928 kb
Host smart-da58a240-c57b-4298-9053-83a699784664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478328477 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.2478328477
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.3716139131
Short name T685
Test name
Test status
Simulation time 494796012673 ps
CPU time 298.66 seconds
Started Jul 06 06:33:28 PM PDT 24
Finished Jul 06 06:38:26 PM PDT 24
Peak memory 201884 kb
Host smart-11000b1c-fd9c-4166-ac6d-62008add4d7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716139131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.3716139131
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.3453696281
Short name T169
Test name
Test status
Simulation time 330129008954 ps
CPU time 737.32 seconds
Started Jul 06 06:33:29 PM PDT 24
Finished Jul 06 06:45:46 PM PDT 24
Peak memory 201980 kb
Host smart-38604baf-0ca3-4bae-b3dc-7e776ffabaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453696281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.3453696281
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1088688301
Short name T672
Test name
Test status
Simulation time 328184045792 ps
CPU time 798.96 seconds
Started Jul 06 06:33:24 PM PDT 24
Finished Jul 06 06:46:44 PM PDT 24
Peak memory 201956 kb
Host smart-d25a96bc-6786-4d83-b7c8-f6dfca89396a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088688301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1088688301
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.3776010750
Short name T646
Test name
Test status
Simulation time 410175159533 ps
CPU time 948.31 seconds
Started Jul 06 06:33:26 PM PDT 24
Finished Jul 06 06:49:14 PM PDT 24
Peak memory 201944 kb
Host smart-1d3e4439-d8bd-4abe-bdc5-e860b3b13fd3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776010750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.3776010750
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.2875697226
Short name T449
Test name
Test status
Simulation time 65468539448 ps
CPU time 360.97 seconds
Started Jul 06 06:33:30 PM PDT 24
Finished Jul 06 06:39:31 PM PDT 24
Peak memory 202276 kb
Host smart-39d284a4-0fcb-4625-a410-25cc305810f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875697226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.2875697226
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3096739253
Short name T521
Test name
Test status
Simulation time 43030453099 ps
CPU time 46.78 seconds
Started Jul 06 06:33:30 PM PDT 24
Finished Jul 06 06:34:18 PM PDT 24
Peak memory 201712 kb
Host smart-8ebb98d8-ee22-4e31-afc1-53e9346edd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096739253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3096739253
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.1820001888
Short name T392
Test name
Test status
Simulation time 2833983305 ps
CPU time 4.05 seconds
Started Jul 06 06:33:30 PM PDT 24
Finished Jul 06 06:33:34 PM PDT 24
Peak memory 201732 kb
Host smart-c7c75456-8303-4d73-a13c-e54e1bb09b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820001888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.1820001888
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.196776187
Short name T476
Test name
Test status
Simulation time 5507282245 ps
CPU time 12.13 seconds
Started Jul 06 06:33:26 PM PDT 24
Finished Jul 06 06:33:38 PM PDT 24
Peak memory 201736 kb
Host smart-0a5ffbdd-a540-4312-b39b-79f7b95da9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196776187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.196776187
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2225903484
Short name T153
Test name
Test status
Simulation time 442933707994 ps
CPU time 504.36 seconds
Started Jul 06 06:33:41 PM PDT 24
Finished Jul 06 06:42:06 PM PDT 24
Peak memory 213932 kb
Host smart-53e32732-45d2-4c22-b478-00d2be1753c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225903484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2225903484
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2430033301
Short name T19
Test name
Test status
Simulation time 245488856715 ps
CPU time 237.56 seconds
Started Jul 06 06:33:31 PM PDT 24
Finished Jul 06 06:37:29 PM PDT 24
Peak memory 217768 kb
Host smart-8377a842-5e16-4f71-b1b4-9dcec6612675
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430033301 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2430033301
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3976115892
Short name T747
Test name
Test status
Simulation time 396979286 ps
CPU time 1.43 seconds
Started Jul 06 06:33:37 PM PDT 24
Finished Jul 06 06:33:39 PM PDT 24
Peak memory 201664 kb
Host smart-c3bea524-5447-41b9-89ac-9bbe220680b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976115892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3976115892
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.3287849074
Short name T263
Test name
Test status
Simulation time 181072681432 ps
CPU time 402.58 seconds
Started Jul 06 06:33:41 PM PDT 24
Finished Jul 06 06:40:24 PM PDT 24
Peak memory 201940 kb
Host smart-e4fc18eb-9376-4ece-b022-77842048feb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287849074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.3287849074
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1774687928
Short name T661
Test name
Test status
Simulation time 503445727780 ps
CPU time 1184.35 seconds
Started Jul 06 06:33:34 PM PDT 24
Finished Jul 06 06:53:19 PM PDT 24
Peak memory 201916 kb
Host smart-66cb2f6e-4172-4a16-8cf9-e077f34f0d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774687928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1774687928
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.192766903
Short name T109
Test name
Test status
Simulation time 162374584233 ps
CPU time 385.27 seconds
Started Jul 06 06:33:40 PM PDT 24
Finished Jul 06 06:40:06 PM PDT 24
Peak memory 201920 kb
Host smart-568fbada-deab-441b-83c3-ae4700ee73e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=192766903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.192766903
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1246814466
Short name T489
Test name
Test status
Simulation time 333098437209 ps
CPU time 509.4 seconds
Started Jul 06 06:33:41 PM PDT 24
Finished Jul 06 06:42:11 PM PDT 24
Peak memory 201984 kb
Host smart-64ecbcab-e124-49b1-94ea-308b10ae5edf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246814466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1246814466
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3224762202
Short name T337
Test name
Test status
Simulation time 358140777143 ps
CPU time 213.88 seconds
Started Jul 06 06:33:34 PM PDT 24
Finished Jul 06 06:37:09 PM PDT 24
Peak memory 201988 kb
Host smart-c4d83f1a-c431-43b6-b13c-88c9e95c4416
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224762202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3224762202
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2164243876
Short name T559
Test name
Test status
Simulation time 582538107849 ps
CPU time 246.45 seconds
Started Jul 06 06:33:35 PM PDT 24
Finished Jul 06 06:37:42 PM PDT 24
Peak memory 201912 kb
Host smart-2846777a-e4bc-41df-b97c-75c4e8a441f9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164243876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2164243876
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3095646635
Short name T755
Test name
Test status
Simulation time 36974350735 ps
CPU time 81.32 seconds
Started Jul 06 06:33:40 PM PDT 24
Finished Jul 06 06:35:01 PM PDT 24
Peak memory 201728 kb
Host smart-c77b3d38-e520-478a-8d41-befbb5709f8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095646635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3095646635
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2138254496
Short name T358
Test name
Test status
Simulation time 4843861366 ps
CPU time 5.91 seconds
Started Jul 06 06:33:33 PM PDT 24
Finished Jul 06 06:33:40 PM PDT 24
Peak memory 201712 kb
Host smart-d35b441b-5508-4ba3-9af7-506a740a4b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138254496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2138254496
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2696954103
Short name T616
Test name
Test status
Simulation time 5781421473 ps
CPU time 2.79 seconds
Started Jul 06 06:33:35 PM PDT 24
Finished Jul 06 06:33:38 PM PDT 24
Peak memory 201688 kb
Host smart-3902fa16-b976-4490-9ffa-1e46e722fd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696954103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2696954103
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.1810682860
Short name T286
Test name
Test status
Simulation time 447748422806 ps
CPU time 383.78 seconds
Started Jul 06 06:33:41 PM PDT 24
Finished Jul 06 06:40:05 PM PDT 24
Peak memory 210428 kb
Host smart-f42734f0-618d-419c-ae49-3ba2cf38bbeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810682860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.1810682860
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.3858115125
Short name T33
Test name
Test status
Simulation time 152816988332 ps
CPU time 66.67 seconds
Started Jul 06 06:33:40 PM PDT 24
Finished Jul 06 06:34:47 PM PDT 24
Peak memory 210264 kb
Host smart-a86a6406-5e5d-4bdd-aa68-f1eee045c41a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3858115125 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.3858115125
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.5514320
Short name T92
Test name
Test status
Simulation time 519811220 ps
CPU time 1.74 seconds
Started Jul 06 06:33:51 PM PDT 24
Finished Jul 06 06:33:53 PM PDT 24
Peak memory 201672 kb
Host smart-99344faa-d9f8-4628-bfb2-0bb992cbe187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5514320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.5514320
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.142784118
Short name T186
Test name
Test status
Simulation time 327672729080 ps
CPU time 72.38 seconds
Started Jul 06 06:33:43 PM PDT 24
Finished Jul 06 06:34:56 PM PDT 24
Peak memory 201940 kb
Host smart-b1bce801-4422-4c36-9be3-e12d0234d65b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142784118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.142784118
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.1440158171
Short name T95
Test name
Test status
Simulation time 368085709509 ps
CPU time 530.62 seconds
Started Jul 06 06:33:47 PM PDT 24
Finished Jul 06 06:42:38 PM PDT 24
Peak memory 201908 kb
Host smart-b8526f9a-2319-40be-91f7-f4051722bef9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440158171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.1440158171
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.3850296316
Short name T756
Test name
Test status
Simulation time 320930415673 ps
CPU time 703.17 seconds
Started Jul 06 06:33:39 PM PDT 24
Finished Jul 06 06:45:23 PM PDT 24
Peak memory 201940 kb
Host smart-0adddcf1-4e6d-44d4-a962-576b4a86160b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850296316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.3850296316
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.3203313390
Short name T445
Test name
Test status
Simulation time 166558817090 ps
CPU time 210.31 seconds
Started Jul 06 06:33:42 PM PDT 24
Finished Jul 06 06:37:13 PM PDT 24
Peak memory 201912 kb
Host smart-41390ca9-b33e-4bd2-be7f-b141d499188f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203313390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.3203313390
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.1158274384
Short name T110
Test name
Test status
Simulation time 487664117676 ps
CPU time 503.2 seconds
Started Jul 06 06:33:38 PM PDT 24
Finished Jul 06 06:42:01 PM PDT 24
Peak memory 201988 kb
Host smart-be1bde05-0d4d-4624-9753-b5aa51994d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158274384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.1158274384
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2489431910
Short name T734
Test name
Test status
Simulation time 170716624456 ps
CPU time 400.35 seconds
Started Jul 06 06:33:38 PM PDT 24
Finished Jul 06 06:40:19 PM PDT 24
Peak memory 201988 kb
Host smart-f66cbdfc-c3ed-4d9d-811e-5a97f02a4eb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489431910 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2489431910
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.1226529011
Short name T311
Test name
Test status
Simulation time 168981368643 ps
CPU time 95.78 seconds
Started Jul 06 06:33:42 PM PDT 24
Finished Jul 06 06:35:18 PM PDT 24
Peak memory 201976 kb
Host smart-085324d8-30a6-439c-8955-aadfe3e2955f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226529011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.1226529011
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.2986927582
Short name T724
Test name
Test status
Simulation time 397958361385 ps
CPU time 259.34 seconds
Started Jul 06 06:33:43 PM PDT 24
Finished Jul 06 06:38:03 PM PDT 24
Peak memory 201920 kb
Host smart-038e6346-be8c-4bb4-9856-0a41469efaed
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986927582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.2986927582
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1158161874
Short name T217
Test name
Test status
Simulation time 79978561635 ps
CPU time 247.2 seconds
Started Jul 06 06:33:46 PM PDT 24
Finished Jul 06 06:37:54 PM PDT 24
Peak memory 202220 kb
Host smart-96566956-65fd-4488-bd41-066c6dcd3c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158161874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1158161874
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.1802988342
Short name T609
Test name
Test status
Simulation time 41631824249 ps
CPU time 83.99 seconds
Started Jul 06 06:33:48 PM PDT 24
Finished Jul 06 06:35:12 PM PDT 24
Peak memory 201732 kb
Host smart-4672dbda-5f0c-4ca3-baca-027170835986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802988342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.1802988342
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.87171505
Short name T442
Test name
Test status
Simulation time 4955880007 ps
CPU time 6.5 seconds
Started Jul 06 06:33:46 PM PDT 24
Finished Jul 06 06:33:52 PM PDT 24
Peak memory 201708 kb
Host smart-e088184b-a4f4-4e1e-9f2a-1d0b728158fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87171505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.87171505
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.679566454
Short name T412
Test name
Test status
Simulation time 5880447421 ps
CPU time 4.05 seconds
Started Jul 06 06:33:38 PM PDT 24
Finished Jul 06 06:33:42 PM PDT 24
Peak memory 201720 kb
Host smart-36224488-52a9-44bc-899a-cf7885f6cbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679566454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.679566454
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1661534863
Short name T740
Test name
Test status
Simulation time 406682996781 ps
CPU time 1625.34 seconds
Started Jul 06 06:33:51 PM PDT 24
Finished Jul 06 07:00:57 PM PDT 24
Peak memory 210424 kb
Host smart-8d65e82f-5a71-4c0b-9579-89b9d52a249f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661534863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1661534863
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1041725978
Short name T605
Test name
Test status
Simulation time 432544562 ps
CPU time 0.9 seconds
Started Jul 06 06:34:01 PM PDT 24
Finished Jul 06 06:34:02 PM PDT 24
Peak memory 201668 kb
Host smart-59401933-d671-492b-a7f6-34bffaf59d34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041725978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1041725978
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.4148992786
Short name T679
Test name
Test status
Simulation time 162609515365 ps
CPU time 185.9 seconds
Started Jul 06 06:33:51 PM PDT 24
Finished Jul 06 06:36:58 PM PDT 24
Peak memory 201976 kb
Host smart-eecf674e-299e-4dc7-9077-05a2f1ce78b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148992786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.4148992786
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2802694993
Short name T596
Test name
Test status
Simulation time 334249234995 ps
CPU time 655.17 seconds
Started Jul 06 06:33:54 PM PDT 24
Finished Jul 06 06:44:50 PM PDT 24
Peak memory 201852 kb
Host smart-01bb45a9-177a-4727-81ca-0c06fb9b0d69
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802694993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2802694993
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4241283277
Short name T723
Test name
Test status
Simulation time 325490687142 ps
CPU time 364.56 seconds
Started Jul 06 06:33:52 PM PDT 24
Finished Jul 06 06:39:57 PM PDT 24
Peak memory 201924 kb
Host smart-41c6ab03-f630-4556-ae05-eaaa5ba56ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241283277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4241283277
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.511888658
Short name T546
Test name
Test status
Simulation time 486578663149 ps
CPU time 604.03 seconds
Started Jul 06 06:33:52 PM PDT 24
Finished Jul 06 06:43:57 PM PDT 24
Peak memory 201960 kb
Host smart-1606ed43-2fbb-496c-853e-3e44d57282ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=511888658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.511888658
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3951578800
Short name T419
Test name
Test status
Simulation time 173278706582 ps
CPU time 381 seconds
Started Jul 06 06:33:55 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 201896 kb
Host smart-712efb4c-4dff-48f6-a3ad-7fa23e7fadeb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951578800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3951578800
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1081184051
Short name T494
Test name
Test status
Simulation time 193981436508 ps
CPU time 204.47 seconds
Started Jul 06 06:33:55 PM PDT 24
Finished Jul 06 06:37:20 PM PDT 24
Peak memory 201908 kb
Host smart-7fefcee7-d1f9-4a21-b0e1-de1cb8390908
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1081184051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1081184051
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.2665551731
Short name T352
Test name
Test status
Simulation time 125471354510 ps
CPU time 560.51 seconds
Started Jul 06 06:33:57 PM PDT 24
Finished Jul 06 06:43:18 PM PDT 24
Peak memory 202148 kb
Host smart-9be52f8f-8e1c-4b0b-b509-7b98733b3e41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665551731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.2665551731
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.1449828059
Short name T104
Test name
Test status
Simulation time 39061364043 ps
CPU time 47.52 seconds
Started Jul 06 06:33:57 PM PDT 24
Finished Jul 06 06:34:45 PM PDT 24
Peak memory 201732 kb
Host smart-02d23843-94de-4ecc-974b-07effcc728f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449828059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.1449828059
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.1352200733
Short name T669
Test name
Test status
Simulation time 4949435029 ps
CPU time 3.78 seconds
Started Jul 06 06:33:57 PM PDT 24
Finished Jul 06 06:34:01 PM PDT 24
Peak memory 201656 kb
Host smart-80a0e50a-af5f-47ce-addc-a31a9f9c9764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352200733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.1352200733
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.1926052150
Short name T618
Test name
Test status
Simulation time 6118429076 ps
CPU time 13.26 seconds
Started Jul 06 06:33:52 PM PDT 24
Finished Jul 06 06:34:05 PM PDT 24
Peak memory 201696 kb
Host smart-11b9e013-3e1b-44a7-a60f-bc15b9b4952e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926052150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.1926052150
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1737032275
Short name T333
Test name
Test status
Simulation time 215380911850 ps
CPU time 473.52 seconds
Started Jul 06 06:34:00 PM PDT 24
Finished Jul 06 06:41:54 PM PDT 24
Peak memory 201844 kb
Host smart-fa564826-67e5-4071-ba34-c92cc4d0296e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737032275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1737032275
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2180284543
Short name T292
Test name
Test status
Simulation time 490539099583 ps
CPU time 124.48 seconds
Started Jul 06 06:34:00 PM PDT 24
Finished Jul 06 06:36:05 PM PDT 24
Peak memory 210236 kb
Host smart-59c5f04b-5b29-4f5e-8b8e-7c8ad39c4993
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180284543 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2180284543
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4140182239
Short name T80
Test name
Test status
Simulation time 278313250 ps
CPU time 1.25 seconds
Started Jul 06 06:34:12 PM PDT 24
Finished Jul 06 06:34:14 PM PDT 24
Peak memory 201592 kb
Host smart-c857a5fb-3c5b-4c6c-87ae-88d47d14399b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140182239 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4140182239
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.246556191
Short name T582
Test name
Test status
Simulation time 167405945541 ps
CPU time 360.88 seconds
Started Jul 06 06:34:12 PM PDT 24
Finished Jul 06 06:40:13 PM PDT 24
Peak memory 201916 kb
Host smart-f5798efe-1762-4cc9-bf9f-e097812791c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246556191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.246556191
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3443996112
Short name T102
Test name
Test status
Simulation time 490097807273 ps
CPU time 1012.23 seconds
Started Jul 06 06:34:06 PM PDT 24
Finished Jul 06 06:50:59 PM PDT 24
Peak memory 201904 kb
Host smart-ffa95cb9-b3bc-48d0-8933-3d232bbd5dba
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443996112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3443996112
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3515286038
Short name T725
Test name
Test status
Simulation time 332032532101 ps
CPU time 356.98 seconds
Started Jul 06 06:34:00 PM PDT 24
Finished Jul 06 06:39:57 PM PDT 24
Peak memory 201988 kb
Host smart-4d42e43b-41d5-4590-a1a1-d9625417d43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515286038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3515286038
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.1390561946
Short name T540
Test name
Test status
Simulation time 494995261583 ps
CPU time 1100.19 seconds
Started Jul 06 06:33:59 PM PDT 24
Finished Jul 06 06:52:19 PM PDT 24
Peak memory 201912 kb
Host smart-c160aba3-625f-4e01-a361-0654f4a54cf1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390561946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.1390561946
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1999746326
Short name T762
Test name
Test status
Simulation time 331538631376 ps
CPU time 800.82 seconds
Started Jul 06 06:34:08 PM PDT 24
Finished Jul 06 06:47:29 PM PDT 24
Peak memory 202000 kb
Host smart-042d7eaa-e4fc-403f-a1dc-2f31b7dd7985
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999746326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1999746326
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.92008031
Short name T717
Test name
Test status
Simulation time 394756401126 ps
CPU time 217.98 seconds
Started Jul 06 06:34:05 PM PDT 24
Finished Jul 06 06:37:44 PM PDT 24
Peak memory 201960 kb
Host smart-fa3e9336-6c56-48ea-b17d-a903358333b6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92008031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.a
dc_ctrl_filters_wakeup_fixed.92008031
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.115046662
Short name T477
Test name
Test status
Simulation time 119716203975 ps
CPU time 594.9 seconds
Started Jul 06 06:34:10 PM PDT 24
Finished Jul 06 06:44:06 PM PDT 24
Peak memory 202236 kb
Host smart-dc1e283f-afde-4e85-b722-aa3fff44525a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115046662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.115046662
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.924124425
Short name T395
Test name
Test status
Simulation time 25912980577 ps
CPU time 60.98 seconds
Started Jul 06 06:34:08 PM PDT 24
Finished Jul 06 06:35:09 PM PDT 24
Peak memory 201732 kb
Host smart-6ddde19a-4d64-413b-ba50-56c29bc4ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924124425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.924124425
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.2757758926
Short name T780
Test name
Test status
Simulation time 5538211020 ps
CPU time 14.66 seconds
Started Jul 06 06:34:10 PM PDT 24
Finished Jul 06 06:34:25 PM PDT 24
Peak memory 201728 kb
Host smart-261d65b5-b126-4abc-bf5d-2aec11edb71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757758926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.2757758926
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.1546372352
Short name T764
Test name
Test status
Simulation time 5779847444 ps
CPU time 13.33 seconds
Started Jul 06 06:34:00 PM PDT 24
Finished Jul 06 06:34:14 PM PDT 24
Peak memory 201740 kb
Host smart-0d052545-230a-445b-94b3-29c895556830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1546372352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.1546372352
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.3278411349
Short name T253
Test name
Test status
Simulation time 578712731053 ps
CPU time 698.12 seconds
Started Jul 06 06:34:13 PM PDT 24
Finished Jul 06 06:45:51 PM PDT 24
Peak memory 201912 kb
Host smart-cbc61373-f5b8-4e20-961c-9a628c23108a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278411349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.3278411349
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2966482548
Short name T640
Test name
Test status
Simulation time 487620744 ps
CPU time 1.66 seconds
Started Jul 06 06:34:25 PM PDT 24
Finished Jul 06 06:34:27 PM PDT 24
Peak memory 201664 kb
Host smart-4e8bd7ee-25e7-4156-b90f-476933f7532d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966482548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2966482548
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1519836733
Short name T229
Test name
Test status
Simulation time 185642695484 ps
CPU time 218.69 seconds
Started Jul 06 06:34:18 PM PDT 24
Finished Jul 06 06:37:57 PM PDT 24
Peak memory 201908 kb
Host smart-3403db85-1e8f-4d18-be38-6f8414fcf12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519836733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1519836733
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.3465740024
Short name T572
Test name
Test status
Simulation time 161603783050 ps
CPU time 89.47 seconds
Started Jul 06 06:34:16 PM PDT 24
Finished Jul 06 06:35:45 PM PDT 24
Peak memory 201892 kb
Host smart-c19de7f0-c0e2-40ac-8a78-05d05bee0ed7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465740024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.3465740024
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.2142678954
Short name T441
Test name
Test status
Simulation time 488485203517 ps
CPU time 286.63 seconds
Started Jul 06 06:34:13 PM PDT 24
Finished Jul 06 06:39:00 PM PDT 24
Peak memory 201916 kb
Host smart-2eeef355-4784-4ce9-a796-5bda76250841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142678954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.2142678954
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3768955475
Short name T709
Test name
Test status
Simulation time 162853733714 ps
CPU time 200.99 seconds
Started Jul 06 06:34:12 PM PDT 24
Finished Jul 06 06:37:34 PM PDT 24
Peak memory 201936 kb
Host smart-14baf278-c2b4-412d-b0ea-5bdf312a49c0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768955475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3768955475
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.4236489578
Short name T162
Test name
Test status
Simulation time 172370567476 ps
CPU time 80.45 seconds
Started Jul 06 06:34:19 PM PDT 24
Finished Jul 06 06:35:39 PM PDT 24
Peak memory 201932 kb
Host smart-0a752326-ed6f-4b00-9eee-16746f3997d2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236489578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.4236489578
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.27990103
Short name T421
Test name
Test status
Simulation time 208089204223 ps
CPU time 435.33 seconds
Started Jul 06 06:34:19 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 201904 kb
Host smart-2f2e6a97-885c-4ab5-8cd1-f263c894efcd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27990103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.a
dc_ctrl_filters_wakeup_fixed.27990103
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.2341028741
Short name T468
Test name
Test status
Simulation time 115002826456 ps
CPU time 404.4 seconds
Started Jul 06 06:34:24 PM PDT 24
Finished Jul 06 06:41:09 PM PDT 24
Peak memory 202196 kb
Host smart-400682e7-9069-4da1-9947-4547695f3498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341028741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.2341028741
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.2922650521
Short name T47
Test name
Test status
Simulation time 35435170140 ps
CPU time 39.37 seconds
Started Jul 06 06:34:24 PM PDT 24
Finished Jul 06 06:35:03 PM PDT 24
Peak memory 201708 kb
Host smart-cb82d567-3894-4f0c-a5c2-495b4723cc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922650521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.2922650521
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.1084873967
Short name T735
Test name
Test status
Simulation time 3974519130 ps
CPU time 2.92 seconds
Started Jul 06 06:34:18 PM PDT 24
Finished Jul 06 06:34:21 PM PDT 24
Peak memory 201740 kb
Host smart-d86c2c94-5850-43a9-b418-0510d8c02695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084873967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.1084873967
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2144517628
Short name T729
Test name
Test status
Simulation time 5954443435 ps
CPU time 4.45 seconds
Started Jul 06 06:34:11 PM PDT 24
Finished Jul 06 06:34:16 PM PDT 24
Peak memory 201684 kb
Host smart-f0c132c2-f58f-4df2-80fc-6531aa8259ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144517628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2144517628
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3502384100
Short name T175
Test name
Test status
Simulation time 199619800044 ps
CPU time 122.11 seconds
Started Jul 06 06:34:25 PM PDT 24
Finished Jul 06 06:36:27 PM PDT 24
Peak memory 201892 kb
Host smart-7e1d6cc4-7e93-4a34-8ed5-f76cbf9edaa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502384100 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3502384100
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.1233275996
Short name T651
Test name
Test status
Simulation time 143489314876 ps
CPU time 169.1 seconds
Started Jul 06 06:34:26 PM PDT 24
Finished Jul 06 06:37:15 PM PDT 24
Peak memory 210576 kb
Host smart-8cc28687-6e9f-4cdc-8716-f669ba7fcba6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233275996 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.1233275996
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1066409009
Short name T507
Test name
Test status
Simulation time 504600118 ps
CPU time 1.2 seconds
Started Jul 06 06:34:35 PM PDT 24
Finished Jul 06 06:34:37 PM PDT 24
Peak memory 201652 kb
Host smart-8cfe0947-d839-4bf2-bc27-ff24638d9a73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066409009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1066409009
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.4095337426
Short name T327
Test name
Test status
Simulation time 172346395462 ps
CPU time 89.55 seconds
Started Jul 06 06:34:30 PM PDT 24
Finished Jul 06 06:35:59 PM PDT 24
Peak memory 201924 kb
Host smart-1facb222-bc6f-44bd-8c46-2ff0c00d7a72
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095337426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.4095337426
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.2581343422
Short name T789
Test name
Test status
Simulation time 160643954038 ps
CPU time 51.94 seconds
Started Jul 06 06:34:29 PM PDT 24
Finished Jul 06 06:35:21 PM PDT 24
Peak memory 201912 kb
Host smart-8a584a75-2cad-4c76-bc35-c455b5269540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581343422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.2581343422
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2912435458
Short name T695
Test name
Test status
Simulation time 488219309446 ps
CPU time 1161.45 seconds
Started Jul 06 06:34:32 PM PDT 24
Finished Jul 06 06:53:54 PM PDT 24
Peak memory 201872 kb
Host smart-675dbf66-0966-4287-8b27-25a0a5454825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912435458 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2912435458
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.971505148
Short name T426
Test name
Test status
Simulation time 333902049877 ps
CPU time 175.76 seconds
Started Jul 06 06:34:29 PM PDT 24
Finished Jul 06 06:37:25 PM PDT 24
Peak memory 201864 kb
Host smart-ea24a443-6525-4904-86c0-efe56759443c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=971505148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrup
t_fixed.971505148
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.2192858593
Short name T792
Test name
Test status
Simulation time 328087683938 ps
CPU time 391.41 seconds
Started Jul 06 06:34:32 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 201984 kb
Host smart-b9dc8b96-c750-455b-a8b6-d2b11f611022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192858593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.2192858593
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.943127858
Short name T584
Test name
Test status
Simulation time 340596045104 ps
CPU time 209.91 seconds
Started Jul 06 06:34:29 PM PDT 24
Finished Jul 06 06:37:59 PM PDT 24
Peak memory 201916 kb
Host smart-ebca42bc-7dd4-4309-8c7e-f6d72ee327dc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=943127858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fixe
d.943127858
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.1397199037
Short name T781
Test name
Test status
Simulation time 199753247545 ps
CPU time 115.13 seconds
Started Jul 06 06:34:29 PM PDT 24
Finished Jul 06 06:36:24 PM PDT 24
Peak memory 201920 kb
Host smart-249e41b8-071e-4804-a24c-6b4c1823085b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397199037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.1397199037
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.2358578262
Short name T208
Test name
Test status
Simulation time 94275903234 ps
CPU time 294.53 seconds
Started Jul 06 06:34:30 PM PDT 24
Finished Jul 06 06:39:24 PM PDT 24
Peak memory 202152 kb
Host smart-15cde983-832a-44a2-af95-26bec1f63898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358578262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.2358578262
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.4272031587
Short name T487
Test name
Test status
Simulation time 30510698437 ps
CPU time 32.73 seconds
Started Jul 06 06:34:27 PM PDT 24
Finished Jul 06 06:35:00 PM PDT 24
Peak memory 201704 kb
Host smart-487c24e4-378c-4839-b71b-c368790b7555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272031587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.4272031587
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.4294757758
Short name T481
Test name
Test status
Simulation time 3730924640 ps
CPU time 2.28 seconds
Started Jul 06 06:34:27 PM PDT 24
Finished Jul 06 06:34:30 PM PDT 24
Peak memory 201696 kb
Host smart-ac873d03-9fdb-47a0-8027-33cd7e144bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294757758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.4294757758
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1523670895
Short name T649
Test name
Test status
Simulation time 5799416124 ps
CPU time 13.97 seconds
Started Jul 06 06:34:24 PM PDT 24
Finished Jul 06 06:34:39 PM PDT 24
Peak memory 201676 kb
Host smart-bb076a88-3014-4d4a-a34c-140391d968ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523670895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1523670895
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2972203836
Short name T50
Test name
Test status
Simulation time 275724587283 ps
CPU time 528.65 seconds
Started Jul 06 06:34:36 PM PDT 24
Finished Jul 06 06:43:25 PM PDT 24
Peak memory 202296 kb
Host smart-d374473c-2f0f-4513-861b-eff5726ea19f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972203836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2972203836
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.157192489
Short name T626
Test name
Test status
Simulation time 16922135463 ps
CPU time 35.65 seconds
Started Jul 06 06:34:28 PM PDT 24
Finished Jul 06 06:35:04 PM PDT 24
Peak memory 202100 kb
Host smart-75343f95-685b-4271-8096-3fc5efe82e14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157192489 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.157192489
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.3076220712
Short name T501
Test name
Test status
Simulation time 436727361 ps
CPU time 0.66 seconds
Started Jul 06 06:34:47 PM PDT 24
Finished Jul 06 06:34:48 PM PDT 24
Peak memory 201668 kb
Host smart-920aaa05-e1fd-4eba-8ed5-46c9755d814a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076220712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.3076220712
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.3191600941
Short name T336
Test name
Test status
Simulation time 182805776663 ps
CPU time 334.95 seconds
Started Jul 06 06:34:36 PM PDT 24
Finished Jul 06 06:40:12 PM PDT 24
Peak memory 201928 kb
Host smart-68bc372e-fdf7-4e39-a79a-e87e356df588
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191600941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.3191600941
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3007596915
Short name T298
Test name
Test status
Simulation time 490077574025 ps
CPU time 1037.62 seconds
Started Jul 06 06:34:37 PM PDT 24
Finished Jul 06 06:51:55 PM PDT 24
Peak memory 201980 kb
Host smart-b1304562-b32b-47a4-a8f8-b6fd0d808e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007596915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3007596915
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.57001529
Short name T564
Test name
Test status
Simulation time 333765308076 ps
CPU time 807.79 seconds
Started Jul 06 06:34:37 PM PDT 24
Finished Jul 06 06:48:05 PM PDT 24
Peak memory 201924 kb
Host smart-3d563e96-8bc8-445e-b862-130f870b8751
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=57001529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt
_fixed.57001529
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3627888588
Short name T256
Test name
Test status
Simulation time 329353975725 ps
CPU time 744.15 seconds
Started Jul 06 06:34:39 PM PDT 24
Finished Jul 06 06:47:03 PM PDT 24
Peak memory 201960 kb
Host smart-dfbed9e4-6bd2-451b-9ef1-7734ecb090d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627888588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3627888588
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2316764835
Short name T612
Test name
Test status
Simulation time 164509861122 ps
CPU time 89.72 seconds
Started Jul 06 06:34:36 PM PDT 24
Finished Jul 06 06:36:06 PM PDT 24
Peak memory 201920 kb
Host smart-9309c6f6-4153-49e4-8e88-b41087e4ded9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316764835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2316764835
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.139573893
Short name T722
Test name
Test status
Simulation time 194789854629 ps
CPU time 433.93 seconds
Started Jul 06 06:34:37 PM PDT 24
Finished Jul 06 06:41:51 PM PDT 24
Peak memory 201900 kb
Host smart-4d93d347-3d2e-4f89-abe2-1370da9e6275
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139573893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.139573893
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.4203575890
Short name T45
Test name
Test status
Simulation time 89395281606 ps
CPU time 346.47 seconds
Started Jul 06 06:34:42 PM PDT 24
Finished Jul 06 06:40:28 PM PDT 24
Peak memory 202272 kb
Host smart-a4e57034-78f1-4904-aed5-ea218ad7f4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203575890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.4203575890
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.152587285
Short name T411
Test name
Test status
Simulation time 29052189549 ps
CPU time 63.05 seconds
Started Jul 06 06:34:42 PM PDT 24
Finished Jul 06 06:35:45 PM PDT 24
Peak memory 201732 kb
Host smart-418e6091-0eec-44e2-8765-fafcd986120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152587285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.152587285
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3568056877
Short name T359
Test name
Test status
Simulation time 3663400732 ps
CPU time 8.5 seconds
Started Jul 06 06:34:41 PM PDT 24
Finished Jul 06 06:34:49 PM PDT 24
Peak memory 201736 kb
Host smart-0cd16fc2-c06e-4864-93de-cfa8cb72b99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568056877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3568056877
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.2828146871
Short name T659
Test name
Test status
Simulation time 6026013697 ps
CPU time 5.16 seconds
Started Jul 06 06:34:36 PM PDT 24
Finished Jul 06 06:34:42 PM PDT 24
Peak memory 201724 kb
Host smart-a43e5a5e-dc05-4720-9cc6-48aa1722e664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828146871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.2828146871
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.240239940
Short name T743
Test name
Test status
Simulation time 71988890142 ps
CPU time 40.07 seconds
Started Jul 06 06:34:47 PM PDT 24
Finished Jul 06 06:35:27 PM PDT 24
Peak memory 201712 kb
Host smart-d8fe755a-d2c6-4338-98a8-cb90c0c89781
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240239940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all.
240239940
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.1725253310
Short name T364
Test name
Test status
Simulation time 504277585 ps
CPU time 0.97 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:32:31 PM PDT 24
Peak memory 201620 kb
Host smart-9b4c64d8-605d-4d08-9ea0-13f2047bdc92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725253310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.1725253310
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1257834336
Short name T773
Test name
Test status
Simulation time 488334512380 ps
CPU time 147.43 seconds
Started Jul 06 06:32:30 PM PDT 24
Finished Jul 06 06:34:58 PM PDT 24
Peak memory 201880 kb
Host smart-00a5eea8-40ab-48b0-ba67-7422dd1dc520
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257834336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1257834336
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.1877744038
Short name T703
Test name
Test status
Simulation time 161813562581 ps
CPU time 137.88 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:34:48 PM PDT 24
Peak memory 201920 kb
Host smart-53cffd8d-6324-4c01-ab6f-d6345195e1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877744038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.1877744038
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3908489067
Short name T322
Test name
Test status
Simulation time 486719600032 ps
CPU time 1029 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:49:39 PM PDT 24
Peak memory 201968 kb
Host smart-4a726341-2025-4caf-8611-623f8c10ef34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908489067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3908489067
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.4203125200
Short name T635
Test name
Test status
Simulation time 332445214586 ps
CPU time 197.99 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:35:48 PM PDT 24
Peak memory 201892 kb
Host smart-ba2a1888-a506-46ce-afde-7f831d1c6e94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4203125200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.4203125200
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.362979701
Short name T705
Test name
Test status
Simulation time 167039589825 ps
CPU time 88.36 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:33:58 PM PDT 24
Peak memory 201956 kb
Host smart-84bac850-020c-4896-934a-9076b391a3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362979701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.362979701
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.790099847
Short name T454
Test name
Test status
Simulation time 496205867063 ps
CPU time 1173.08 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:52:03 PM PDT 24
Peak memory 201824 kb
Host smart-9c5dafcc-0a83-407a-aa4b-84c9ea664760
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=790099847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.790099847
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.3410065004
Short name T460
Test name
Test status
Simulation time 606167348583 ps
CPU time 737.3 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:44:47 PM PDT 24
Peak memory 201924 kb
Host smart-f4d4e67d-3ba5-4745-917d-43f3ed3a8bc6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410065004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.3410065004
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.198036887
Short name T486
Test name
Test status
Simulation time 594988052160 ps
CPU time 358.9 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:38:29 PM PDT 24
Peak memory 201900 kb
Host smart-5bc7948b-6b9d-4291-bb7d-2fcc39a561ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198036887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.a
dc_ctrl_filters_wakeup_fixed.198036887
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.1752367302
Short name T496
Test name
Test status
Simulation time 28347310508 ps
CPU time 16.84 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:32:47 PM PDT 24
Peak memory 201732 kb
Host smart-9203ca7f-d54f-467a-bf44-7961077fdbf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752367302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.1752367302
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1795935300
Short name T435
Test name
Test status
Simulation time 5909363283 ps
CPU time 2.4 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:32:31 PM PDT 24
Peak memory 201728 kb
Host smart-65eeb2c0-aa91-41a9-b390-7ae3101fec82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795935300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1795935300
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3038397428
Short name T62
Test name
Test status
Simulation time 7217574327 ps
CPU time 5.08 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:32:35 PM PDT 24
Peak memory 217252 kb
Host smart-76462df8-1112-46f5-b8b0-b9f0a4ceb65a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038397428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3038397428
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1999402774
Short name T558
Test name
Test status
Simulation time 5836941784 ps
CPU time 4.24 seconds
Started Jul 06 06:32:26 PM PDT 24
Finished Jul 06 06:32:31 PM PDT 24
Peak memory 201724 kb
Host smart-65746da1-aa48-4052-bacc-135eff2098bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999402774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1999402774
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3533707260
Short name T31
Test name
Test status
Simulation time 340521466622 ps
CPU time 100.23 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:34:10 PM PDT 24
Peak memory 201976 kb
Host smart-9e5d7756-ae8c-4c96-b528-7bf8f69b1b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533707260 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3533707260
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.4208825293
Short name T17
Test name
Test status
Simulation time 197063301604 ps
CPU time 54.95 seconds
Started Jul 06 06:32:27 PM PDT 24
Finished Jul 06 06:33:23 PM PDT 24
Peak memory 210240 kb
Host smart-30e7ad98-c455-4caf-8505-d1e97e5294ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208825293 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.4208825293
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.536836388
Short name T41
Test name
Test status
Simulation time 306561387 ps
CPU time 0.94 seconds
Started Jul 06 06:34:54 PM PDT 24
Finished Jul 06 06:34:55 PM PDT 24
Peak memory 201672 kb
Host smart-30d6fbba-82b5-4eea-8fbc-c3fee9fe61d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536836388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.536836388
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3591900319
Short name T607
Test name
Test status
Simulation time 174913666305 ps
CPU time 111.57 seconds
Started Jul 06 06:34:51 PM PDT 24
Finished Jul 06 06:36:42 PM PDT 24
Peak memory 201920 kb
Host smart-2d7c7935-2a7b-4c07-add7-76bbc6780abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591900319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3591900319
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2367821022
Short name T664
Test name
Test status
Simulation time 325959058532 ps
CPU time 148.53 seconds
Started Jul 06 06:34:48 PM PDT 24
Finished Jul 06 06:37:17 PM PDT 24
Peak memory 201888 kb
Host smart-4fa90656-289e-43ca-96b0-55dc67cda2ed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367821022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2367821022
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.3897189369
Short name T389
Test name
Test status
Simulation time 164326328470 ps
CPU time 103.27 seconds
Started Jul 06 06:34:46 PM PDT 24
Finished Jul 06 06:36:30 PM PDT 24
Peak memory 201892 kb
Host smart-62b011f0-e937-481c-9acf-9d2adb539c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897189369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.3897189369
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.2563962446
Short name T401
Test name
Test status
Simulation time 495809912140 ps
CPU time 1094.07 seconds
Started Jul 06 06:34:47 PM PDT 24
Finished Jul 06 06:53:01 PM PDT 24
Peak memory 201908 kb
Host smart-8f343219-4f15-419b-a28a-b811640c6533
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563962446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.2563962446
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1508060880
Short name T776
Test name
Test status
Simulation time 567983369754 ps
CPU time 1210.21 seconds
Started Jul 06 06:34:53 PM PDT 24
Finished Jul 06 06:55:04 PM PDT 24
Peak memory 201000 kb
Host smart-4842b305-963e-4e8b-aeac-110aa7a05a9d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508060880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1508060880
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.1283010816
Short name T500
Test name
Test status
Simulation time 390869326024 ps
CPU time 223.35 seconds
Started Jul 06 06:34:48 PM PDT 24
Finished Jul 06 06:38:32 PM PDT 24
Peak memory 201860 kb
Host smart-98807849-e74a-4f4f-b371-6ad53b4ab2d7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283010816 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.1283010816
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3514785986
Short name T206
Test name
Test status
Simulation time 103606612154 ps
CPU time 526.45 seconds
Started Jul 06 06:34:48 PM PDT 24
Finished Jul 06 06:43:35 PM PDT 24
Peak memory 202168 kb
Host smart-0fe3f13f-8985-4372-98b6-1c14ee8f01b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514785986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3514785986
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.3472765599
Short name T681
Test name
Test status
Simulation time 35573143672 ps
CPU time 20.95 seconds
Started Jul 06 06:34:49 PM PDT 24
Finished Jul 06 06:35:10 PM PDT 24
Peak memory 201732 kb
Host smart-e2c40b60-d680-460f-a667-090f135eab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472765599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.3472765599
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.1145711759
Short name T667
Test name
Test status
Simulation time 5133679105 ps
CPU time 6.08 seconds
Started Jul 06 06:34:48 PM PDT 24
Finished Jul 06 06:34:54 PM PDT 24
Peak memory 201728 kb
Host smart-0d00e961-f0f4-4d1d-b58c-e040a884d2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145711759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.1145711759
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.3273429892
Short name T627
Test name
Test status
Simulation time 6145103326 ps
CPU time 2 seconds
Started Jul 06 06:34:44 PM PDT 24
Finished Jul 06 06:34:47 PM PDT 24
Peak memory 201668 kb
Host smart-d6344b54-86c0-4223-acf3-7a7b87f5bd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3273429892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.3273429892
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3082776535
Short name T187
Test name
Test status
Simulation time 410568922679 ps
CPU time 242.12 seconds
Started Jul 06 06:34:53 PM PDT 24
Finished Jul 06 06:38:56 PM PDT 24
Peak memory 201848 kb
Host smart-c2772e69-9a7f-4aea-b501-2ccf199ab6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082776535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3082776535
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1936648914
Short name T658
Test name
Test status
Simulation time 180512718751 ps
CPU time 203.66 seconds
Started Jul 06 06:34:49 PM PDT 24
Finished Jul 06 06:38:13 PM PDT 24
Peak memory 211556 kb
Host smart-32908520-9db6-46b8-a3a6-c1f8b0bdcc51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936648914 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1936648914
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.478142498
Short name T619
Test name
Test status
Simulation time 483503486 ps
CPU time 1.7 seconds
Started Jul 06 06:35:03 PM PDT 24
Finished Jul 06 06:35:05 PM PDT 24
Peak memory 201636 kb
Host smart-676d0981-c498-4d00-a3e3-a648c84ddc38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478142498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.478142498
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.423231155
Short name T171
Test name
Test status
Simulation time 170353346484 ps
CPU time 43.9 seconds
Started Jul 06 06:35:00 PM PDT 24
Finished Jul 06 06:35:44 PM PDT 24
Peak memory 201936 kb
Host smart-da39b681-ea77-4e27-a83d-5863ec3b55ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423231155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.423231155
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.2263930313
Short name T632
Test name
Test status
Simulation time 161003777750 ps
CPU time 178.5 seconds
Started Jul 06 06:34:56 PM PDT 24
Finished Jul 06 06:37:55 PM PDT 24
Peak memory 201872 kb
Host smart-ba157792-3e91-4c28-a2d7-dfab8f13c16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263930313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.2263930313
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.2404689483
Short name T444
Test name
Test status
Simulation time 488397893647 ps
CPU time 1007.47 seconds
Started Jul 06 06:34:54 PM PDT 24
Finished Jul 06 06:51:42 PM PDT 24
Peak memory 201912 kb
Host smart-acf5373f-48e9-49fd-91a3-12928b328d7a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404689483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.2404689483
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.1080318434
Short name T733
Test name
Test status
Simulation time 327988007734 ps
CPU time 724.65 seconds
Started Jul 06 06:34:56 PM PDT 24
Finished Jul 06 06:47:01 PM PDT 24
Peak memory 201904 kb
Host smart-4d59a7b1-b2c7-404d-abac-5ef1d125ebcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080318434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.1080318434
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.2994600027
Short name T721
Test name
Test status
Simulation time 494311922955 ps
CPU time 1180.85 seconds
Started Jul 06 06:34:56 PM PDT 24
Finished Jul 06 06:54:37 PM PDT 24
Peak memory 201852 kb
Host smart-898ac96c-61a1-443e-80b5-c1efb6b78af1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994600027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.2994600027
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3903358961
Short name T189
Test name
Test status
Simulation time 376294880887 ps
CPU time 75.74 seconds
Started Jul 06 06:34:56 PM PDT 24
Finished Jul 06 06:36:12 PM PDT 24
Peak memory 201920 kb
Host smart-e1aeef60-dcf0-458d-b0b9-63cc75b370de
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903358961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3903358961
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3617105875
Short name T376
Test name
Test status
Simulation time 594568514035 ps
CPU time 310.87 seconds
Started Jul 06 06:35:02 PM PDT 24
Finished Jul 06 06:40:14 PM PDT 24
Peak memory 201956 kb
Host smart-536ba29d-43e3-4b36-bc87-2eb775b622f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617105875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31
.adc_ctrl_filters_wakeup_fixed.3617105875
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.1393289464
Short name T662
Test name
Test status
Simulation time 98527693201 ps
CPU time 421.65 seconds
Started Jul 06 06:35:01 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 202224 kb
Host smart-bb1d5c71-3f29-4884-975d-981e659a0530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393289464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.1393289464
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3711225696
Short name T492
Test name
Test status
Simulation time 44227437880 ps
CPU time 97.29 seconds
Started Jul 06 06:35:01 PM PDT 24
Finished Jul 06 06:36:38 PM PDT 24
Peak memory 201696 kb
Host smart-92e08d4b-c61c-4ff8-a73f-acaf4ba68291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711225696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3711225696
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1558292612
Short name T529
Test name
Test status
Simulation time 4484708661 ps
CPU time 3.39 seconds
Started Jul 06 06:35:02 PM PDT 24
Finished Jul 06 06:35:06 PM PDT 24
Peak memory 201680 kb
Host smart-6d8e4408-b6b0-482b-badf-3ccd2aa6777d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558292612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1558292612
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.1728456851
Short name T459
Test name
Test status
Simulation time 6038431091 ps
CPU time 3.62 seconds
Started Jul 06 06:34:53 PM PDT 24
Finished Jul 06 06:34:57 PM PDT 24
Peak memory 201680 kb
Host smart-b2d90a99-ab11-4bca-939c-be6e88eb0047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728456851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.1728456851
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2553018277
Short name T209
Test name
Test status
Simulation time 1986652860354 ps
CPU time 936.21 seconds
Started Jul 06 06:35:00 PM PDT 24
Finished Jul 06 06:50:36 PM PDT 24
Peak memory 213164 kb
Host smart-8ea60378-fd88-4df9-ba20-aec28996d03b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553018277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2553018277
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.2235226728
Short name T21
Test name
Test status
Simulation time 295459561659 ps
CPU time 270.89 seconds
Started Jul 06 06:35:00 PM PDT 24
Finished Jul 06 06:39:31 PM PDT 24
Peak memory 210196 kb
Host smart-2815fb15-cd18-4901-8641-739403680b9a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235226728 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.2235226728
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.852563782
Short name T383
Test name
Test status
Simulation time 358894586 ps
CPU time 0.8 seconds
Started Jul 06 06:35:15 PM PDT 24
Finished Jul 06 06:35:16 PM PDT 24
Peak memory 201688 kb
Host smart-09ec9236-0fca-4f39-8d8c-7f691e221529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852563782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.852563782
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.449143808
Short name T767
Test name
Test status
Simulation time 173071280817 ps
CPU time 376.71 seconds
Started Jul 06 06:35:12 PM PDT 24
Finished Jul 06 06:41:30 PM PDT 24
Peak memory 201868 kb
Host smart-498b54eb-1840-46d8-b5a7-17d19d03ac39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449143808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.449143808
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1080415609
Short name T297
Test name
Test status
Simulation time 170682715618 ps
CPU time 329.59 seconds
Started Jul 06 06:35:13 PM PDT 24
Finished Jul 06 06:40:43 PM PDT 24
Peak memory 201920 kb
Host smart-15548783-7c29-499f-a5fa-75131dcc8d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080415609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1080415609
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3397058374
Short name T408
Test name
Test status
Simulation time 489886165348 ps
CPU time 1067.99 seconds
Started Jul 06 06:35:10 PM PDT 24
Finished Jul 06 06:52:58 PM PDT 24
Peak memory 201908 kb
Host smart-313c3a78-c25b-4fb3-a0c3-6fb954dfb0a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397058374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3397058374
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2863942189
Short name T769
Test name
Test status
Simulation time 325987227666 ps
CPU time 187.48 seconds
Started Jul 06 06:35:14 PM PDT 24
Finished Jul 06 06:38:22 PM PDT 24
Peak memory 201940 kb
Host smart-24daf932-9dca-4073-aefd-283de6c6f05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863942189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2863942189
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.643117987
Short name T160
Test name
Test status
Simulation time 161027555568 ps
CPU time 101.76 seconds
Started Jul 06 06:35:13 PM PDT 24
Finished Jul 06 06:36:55 PM PDT 24
Peak memory 201972 kb
Host smart-e9c21005-6761-4604-98ef-d325d29e5fdd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=643117987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.643117987
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3946870355
Short name T312
Test name
Test status
Simulation time 380210321485 ps
CPU time 780.16 seconds
Started Jul 06 06:35:11 PM PDT 24
Finished Jul 06 06:48:11 PM PDT 24
Peak memory 201924 kb
Host smart-222d9676-e360-44eb-b41a-cc3a32e43e46
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946870355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3946870355
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2157682803
Short name T522
Test name
Test status
Simulation time 399808648814 ps
CPU time 458.87 seconds
Started Jul 06 06:35:13 PM PDT 24
Finished Jul 06 06:42:53 PM PDT 24
Peak memory 201900 kb
Host smart-d15cf805-bbb9-4c1b-9648-be91cf467ebe
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157682803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2157682803
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2613471422
Short name T583
Test name
Test status
Simulation time 83147600146 ps
CPU time 244.33 seconds
Started Jul 06 06:35:14 PM PDT 24
Finished Jul 06 06:39:18 PM PDT 24
Peak memory 202172 kb
Host smart-23fcd8eb-a868-469e-aab7-8350bbbaca1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613471422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2613471422
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.2239275403
Short name T674
Test name
Test status
Simulation time 29544164700 ps
CPU time 34.36 seconds
Started Jul 06 06:35:14 PM PDT 24
Finished Jul 06 06:35:49 PM PDT 24
Peak memory 201680 kb
Host smart-63d42906-27d5-4bb6-896a-0e724b307be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239275403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.2239275403
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.2822465278
Short name T199
Test name
Test status
Simulation time 4275254804 ps
CPU time 10.49 seconds
Started Jul 06 06:35:12 PM PDT 24
Finished Jul 06 06:35:22 PM PDT 24
Peak memory 201716 kb
Host smart-2a7580e1-fc45-4f6e-b7ac-1d0544bc8fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822465278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.2822465278
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.32484800
Short name T538
Test name
Test status
Simulation time 5885963445 ps
CPU time 3.99 seconds
Started Jul 06 06:35:02 PM PDT 24
Finished Jul 06 06:35:06 PM PDT 24
Peak memory 201700 kb
Host smart-dad87181-faab-4773-ad16-64678165fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32484800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.32484800
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.1627760503
Short name T218
Test name
Test status
Simulation time 650817415133 ps
CPU time 913.02 seconds
Started Jul 06 06:35:16 PM PDT 24
Finished Jul 06 06:50:29 PM PDT 24
Peak memory 210396 kb
Host smart-3d121ec8-6c03-4cd8-89fc-d8ff17131c52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627760503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.1627760503
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.4071990218
Short name T265
Test name
Test status
Simulation time 82264282386 ps
CPU time 209.93 seconds
Started Jul 06 06:35:11 PM PDT 24
Finished Jul 06 06:38:42 PM PDT 24
Peak memory 210552 kb
Host smart-487a767d-2e0c-4209-b61a-acf3ee8c8893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071990218 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.4071990218
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1753086731
Short name T374
Test name
Test status
Simulation time 327295492 ps
CPU time 0.78 seconds
Started Jul 06 06:35:22 PM PDT 24
Finished Jul 06 06:35:23 PM PDT 24
Peak memory 201660 kb
Host smart-29863f1e-5429-4b67-bd7a-b8a01f85d99f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753086731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1753086731
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.303749059
Short name T8
Test name
Test status
Simulation time 166393593601 ps
CPU time 384.46 seconds
Started Jul 06 06:35:19 PM PDT 24
Finished Jul 06 06:41:44 PM PDT 24
Peak memory 201900 kb
Host smart-0c290771-04d2-4c63-8144-ed0fcf0f000d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303749059 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.303749059
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.3836610786
Short name T301
Test name
Test status
Simulation time 164849225905 ps
CPU time 58.83 seconds
Started Jul 06 06:35:13 PM PDT 24
Finished Jul 06 06:36:12 PM PDT 24
Peak memory 201928 kb
Host smart-b81f27bb-032b-4868-a5cb-bd1fa0191396
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836610786 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.3836610786
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3356378223
Short name T495
Test name
Test status
Simulation time 488170573711 ps
CPU time 1100.07 seconds
Started Jul 06 06:35:13 PM PDT 24
Finished Jul 06 06:53:33 PM PDT 24
Peak memory 201896 kb
Host smart-836a9bbb-b9ae-4292-9869-b704bbe46473
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356378223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3356378223
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3996251156
Short name T101
Test name
Test status
Simulation time 332886946872 ps
CPU time 806.7 seconds
Started Jul 06 06:35:14 PM PDT 24
Finished Jul 06 06:48:41 PM PDT 24
Peak memory 201980 kb
Host smart-2ada9e98-7b62-4e6b-b944-8293114dde3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996251156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3996251156
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2685912483
Short name T726
Test name
Test status
Simulation time 329672690223 ps
CPU time 720.82 seconds
Started Jul 06 06:35:13 PM PDT 24
Finished Jul 06 06:47:14 PM PDT 24
Peak memory 201876 kb
Host smart-29beca0b-e1e1-46e0-a34b-36606702c55b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685912483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2685912483
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.3845506656
Short name T628
Test name
Test status
Simulation time 544979800492 ps
CPU time 1127.14 seconds
Started Jul 06 06:35:18 PM PDT 24
Finished Jul 06 06:54:06 PM PDT 24
Peak memory 201912 kb
Host smart-c85e4986-244d-4ec1-81fb-846f75bb6934
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845506656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.3845506656
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1937586856
Short name T428
Test name
Test status
Simulation time 608480481311 ps
CPU time 122.8 seconds
Started Jul 06 06:35:18 PM PDT 24
Finished Jul 06 06:37:21 PM PDT 24
Peak memory 201912 kb
Host smart-e13d22b0-c9f8-4909-9829-120b81eafeea
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937586856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1937586856
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.88026453
Short name T400
Test name
Test status
Simulation time 151976755936 ps
CPU time 561.94 seconds
Started Jul 06 06:35:23 PM PDT 24
Finished Jul 06 06:44:45 PM PDT 24
Peak memory 202164 kb
Host smart-af4a98c1-3c60-4a75-9cd7-4d959ca07b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88026453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.88026453
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1292607423
Short name T526
Test name
Test status
Simulation time 38233556624 ps
CPU time 15.7 seconds
Started Jul 06 06:35:18 PM PDT 24
Finished Jul 06 06:35:34 PM PDT 24
Peak memory 201708 kb
Host smart-90f84795-2e2b-4775-8758-b14ac9be337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292607423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1292607423
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3475501195
Short name T512
Test name
Test status
Simulation time 4516382621 ps
CPU time 8.45 seconds
Started Jul 06 06:35:17 PM PDT 24
Finished Jul 06 06:35:26 PM PDT 24
Peak memory 201724 kb
Host smart-b118d814-f7cb-46fe-bc2b-88603c41b2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475501195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3475501195
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2618228250
Short name T708
Test name
Test status
Simulation time 6198012769 ps
CPU time 1.66 seconds
Started Jul 06 06:35:12 PM PDT 24
Finished Jul 06 06:35:14 PM PDT 24
Peak memory 201724 kb
Host smart-235c6864-5e5a-4b79-abac-05f775baa01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618228250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2618228250
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.901858208
Short name T200
Test name
Test status
Simulation time 359506872817 ps
CPU time 1722.1 seconds
Started Jul 06 06:35:23 PM PDT 24
Finished Jul 06 07:04:05 PM PDT 24
Peak memory 210416 kb
Host smart-4147f36c-5067-4225-a1b3-291e6eb8875a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901858208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all.
901858208
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.335875113
Short name T30
Test name
Test status
Simulation time 530678352387 ps
CPU time 705.7 seconds
Started Jul 06 06:35:22 PM PDT 24
Finished Jul 06 06:47:08 PM PDT 24
Peak memory 210552 kb
Host smart-2a09ff9d-bdbb-48b7-bfd4-de2af621536c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335875113 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.335875113
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1267528012
Short name T482
Test name
Test status
Simulation time 518524384 ps
CPU time 1.65 seconds
Started Jul 06 06:35:30 PM PDT 24
Finished Jul 06 06:35:32 PM PDT 24
Peak memory 201644 kb
Host smart-af1eb4ba-c6d0-48dc-aa02-66b938a5e5e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267528012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1267528012
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2648443610
Short name T715
Test name
Test status
Simulation time 539840408650 ps
CPU time 550.67 seconds
Started Jul 06 06:35:25 PM PDT 24
Finished Jul 06 06:44:36 PM PDT 24
Peak memory 201932 kb
Host smart-58846645-c953-4674-8d9c-d1ccd6e72ab7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648443610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2648443610
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.2051450986
Short name T694
Test name
Test status
Simulation time 164859800115 ps
CPU time 107.17 seconds
Started Jul 06 06:35:23 PM PDT 24
Finished Jul 06 06:37:10 PM PDT 24
Peak memory 201984 kb
Host smart-27b1e2c8-a4e1-4670-bb4c-f36e54635eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051450986 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.2051450986
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.504767327
Short name T455
Test name
Test status
Simulation time 165967559359 ps
CPU time 385.17 seconds
Started Jul 06 06:35:22 PM PDT 24
Finished Jul 06 06:41:47 PM PDT 24
Peak memory 201844 kb
Host smart-c2230a7a-ad5b-498d-86fb-bcdee88ef8fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=504767327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrup
t_fixed.504767327
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.292220483
Short name T342
Test name
Test status
Simulation time 333455737841 ps
CPU time 181.38 seconds
Started Jul 06 06:35:22 PM PDT 24
Finished Jul 06 06:38:24 PM PDT 24
Peak memory 201960 kb
Host smart-53b4fcda-2faf-4bb5-b80f-50dc4f46c436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292220483 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.292220483
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.1309496075
Short name T778
Test name
Test status
Simulation time 490368102772 ps
CPU time 1063.4 seconds
Started Jul 06 06:35:22 PM PDT 24
Finished Jul 06 06:53:06 PM PDT 24
Peak memory 201880 kb
Host smart-de04b004-20d2-402c-a977-57fe1b9472b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309496075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.1309496075
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1976699139
Short name T766
Test name
Test status
Simulation time 181694135575 ps
CPU time 33.98 seconds
Started Jul 06 06:35:27 PM PDT 24
Finished Jul 06 06:36:01 PM PDT 24
Peak memory 201940 kb
Host smart-82f4d3d2-eadd-4bcc-a07e-3b8a24681b49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976699139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1976699139
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.902966911
Short name T357
Test name
Test status
Simulation time 609500234348 ps
CPU time 1396.59 seconds
Started Jul 06 06:35:26 PM PDT 24
Finished Jul 06 06:58:43 PM PDT 24
Peak memory 201840 kb
Host smart-c0f97412-7420-4b2b-a185-6cf2b9f81e19
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902966911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.902966911
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.2576680609
Short name T610
Test name
Test status
Simulation time 100259693323 ps
CPU time 578.04 seconds
Started Jul 06 06:35:31 PM PDT 24
Finished Jul 06 06:45:10 PM PDT 24
Peak memory 202216 kb
Host smart-f4ee4e19-12bc-41fc-b113-4b865aeee2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576680609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.2576680609
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.1516477470
Short name T83
Test name
Test status
Simulation time 33056924838 ps
CPU time 20.68 seconds
Started Jul 06 06:35:31 PM PDT 24
Finished Jul 06 06:35:52 PM PDT 24
Peak memory 201724 kb
Host smart-b3d0dc1c-2c95-4ad0-9d9e-a8822db532e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516477470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.1516477470
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.1983303666
Short name T791
Test name
Test status
Simulation time 3938327128 ps
CPU time 2.41 seconds
Started Jul 06 06:35:31 PM PDT 24
Finished Jul 06 06:35:34 PM PDT 24
Peak memory 201672 kb
Host smart-2e9623a5-9d23-45f2-9a57-99e37654d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983303666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.1983303666
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.636614920
Short name T534
Test name
Test status
Simulation time 5685618820 ps
CPU time 1.71 seconds
Started Jul 06 06:35:21 PM PDT 24
Finished Jul 06 06:35:23 PM PDT 24
Peak memory 201708 kb
Host smart-309cb6b3-1725-49f8-963e-8549ca891b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636614920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.636614920
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.1922000841
Short name T514
Test name
Test status
Simulation time 162014957088 ps
CPU time 355.5 seconds
Started Jul 06 06:35:31 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 201848 kb
Host smart-8d03af69-f602-4a9c-9070-93ae94a2659d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1922000841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.1922000841
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.671322156
Short name T350
Test name
Test status
Simulation time 133198478800 ps
CPU time 216 seconds
Started Jul 06 06:35:30 PM PDT 24
Finished Jul 06 06:39:06 PM PDT 24
Peak memory 210556 kb
Host smart-98a1b157-a353-44e2-bb76-33467e3e9332
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671322156 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.671322156
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.980279950
Short name T727
Test name
Test status
Simulation time 293694961 ps
CPU time 1.3 seconds
Started Jul 06 06:35:39 PM PDT 24
Finished Jul 06 06:35:41 PM PDT 24
Peak memory 201648 kb
Host smart-d90aeb24-bdab-4666-a253-15f505cc5dd0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980279950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.980279950
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3346995602
Short name T339
Test name
Test status
Simulation time 160113517687 ps
CPU time 341.62 seconds
Started Jul 06 06:35:42 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 201984 kb
Host smart-e125f474-f6ca-4980-9f28-66eebe79c768
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346995602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3346995602
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2719774521
Short name T188
Test name
Test status
Simulation time 550740926384 ps
CPU time 318.88 seconds
Started Jul 06 06:35:41 PM PDT 24
Finished Jul 06 06:41:00 PM PDT 24
Peak memory 201860 kb
Host smart-7152e8df-ca00-46e1-9280-50214ccdcb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2719774521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2719774521
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3403685224
Short name T105
Test name
Test status
Simulation time 162737119625 ps
CPU time 369.83 seconds
Started Jul 06 06:35:35 PM PDT 24
Finished Jul 06 06:41:45 PM PDT 24
Peak memory 201928 kb
Host smart-7c3dfa83-fa18-4224-927b-fd5a363b5aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403685224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3403685224
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.962601704
Short name T556
Test name
Test status
Simulation time 163256143418 ps
CPU time 339.78 seconds
Started Jul 06 06:35:34 PM PDT 24
Finished Jul 06 06:41:14 PM PDT 24
Peak memory 201832 kb
Host smart-0905fe40-0fa1-40b9-ada6-7fe1b97afdf3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=962601704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrup
t_fixed.962601704
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2284652957
Short name T143
Test name
Test status
Simulation time 490781288567 ps
CPU time 1109.95 seconds
Started Jul 06 06:35:34 PM PDT 24
Finished Jul 06 06:54:05 PM PDT 24
Peak memory 201896 kb
Host smart-3fc0695a-3ef9-45b7-b87e-04af4fb139cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284652957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2284652957
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2099564992
Short name T746
Test name
Test status
Simulation time 486909295009 ps
CPU time 286.3 seconds
Started Jul 06 06:35:35 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 201908 kb
Host smart-e3568d62-b6a1-4160-abc4-534cac30de2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099564992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2099564992
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.1802014653
Short name T666
Test name
Test status
Simulation time 644298812704 ps
CPU time 829.8 seconds
Started Jul 06 06:35:36 PM PDT 24
Finished Jul 06 06:49:26 PM PDT 24
Peak memory 202000 kb
Host smart-f099295f-cf76-4e8d-af24-fab06b50f26b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802014653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.1802014653
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.2603476672
Short name T81
Test name
Test status
Simulation time 203354307389 ps
CPU time 111.28 seconds
Started Jul 06 06:35:41 PM PDT 24
Finished Jul 06 06:37:32 PM PDT 24
Peak memory 201836 kb
Host smart-65d08d70-5e3a-47d6-a435-5985c06c224d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603476672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.2603476672
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.208790132
Short name T533
Test name
Test status
Simulation time 127973600389 ps
CPU time 379.68 seconds
Started Jul 06 06:35:42 PM PDT 24
Finished Jul 06 06:42:01 PM PDT 24
Peak memory 202300 kb
Host smart-e62e74b4-b1bd-442c-a783-6ff6ec29224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208790132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.208790132
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.381144665
Short name T424
Test name
Test status
Simulation time 44885449006 ps
CPU time 32.39 seconds
Started Jul 06 06:35:39 PM PDT 24
Finished Jul 06 06:36:12 PM PDT 24
Peak memory 201732 kb
Host smart-94378006-4607-4df2-9001-54af5c5d4429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381144665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.381144665
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3331115035
Short name T429
Test name
Test status
Simulation time 2879933062 ps
CPU time 1.57 seconds
Started Jul 06 06:35:40 PM PDT 24
Finished Jul 06 06:35:42 PM PDT 24
Peak memory 201736 kb
Host smart-5eb391e1-eeae-4c0a-8c39-7c1d71e5842b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331115035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3331115035
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.493374509
Short name T474
Test name
Test status
Simulation time 5863902159 ps
CPU time 7.61 seconds
Started Jul 06 06:35:36 PM PDT 24
Finished Jul 06 06:35:44 PM PDT 24
Peak memory 201740 kb
Host smart-65b3cfc5-c13f-47ed-ba7c-822d4720a07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493374509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.493374509
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.1211773533
Short name T245
Test name
Test status
Simulation time 51005685254 ps
CPU time 146.66 seconds
Started Jul 06 06:35:40 PM PDT 24
Finished Jul 06 06:38:06 PM PDT 24
Peak memory 211112 kb
Host smart-ac153182-5b7a-497a-ac6a-3d204c5682ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211773533 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.1211773533
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2564541406
Short name T519
Test name
Test status
Simulation time 397677852 ps
CPU time 0.85 seconds
Started Jul 06 06:35:47 PM PDT 24
Finished Jul 06 06:35:48 PM PDT 24
Peak memory 201656 kb
Host smart-9e26ff02-5a1d-4587-97a0-9d55bfc356c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564541406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2564541406
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2604241404
Short name T334
Test name
Test status
Simulation time 163794131001 ps
CPU time 357.51 seconds
Started Jul 06 06:35:47 PM PDT 24
Finished Jul 06 06:41:45 PM PDT 24
Peak memory 201900 kb
Host smart-917511ed-1d73-4539-b9c3-f2d6c0f5494e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604241404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2604241404
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.77739444
Short name T615
Test name
Test status
Simulation time 338827703655 ps
CPU time 200.76 seconds
Started Jul 06 06:35:42 PM PDT 24
Finished Jul 06 06:39:03 PM PDT 24
Peak memory 201916 kb
Host smart-f9368f61-00b8-44f0-828b-64bf78732fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77739444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.77739444
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.726109595
Short name T390
Test name
Test status
Simulation time 162817650615 ps
CPU time 36.74 seconds
Started Jul 06 06:35:43 PM PDT 24
Finished Jul 06 06:36:20 PM PDT 24
Peak memory 201888 kb
Host smart-59c3b4be-42a4-4d6f-b4b6-e5b898b01994
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=726109595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.726109595
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1644796316
Short name T576
Test name
Test status
Simulation time 331931378028 ps
CPU time 681.9 seconds
Started Jul 06 06:35:45 PM PDT 24
Finished Jul 06 06:47:07 PM PDT 24
Peak memory 201924 kb
Host smart-8a77256b-6183-4ff3-9c7d-4b93d3965372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644796316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1644796316
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.2870352133
Short name T29
Test name
Test status
Simulation time 492951965116 ps
CPU time 1036.93 seconds
Started Jul 06 06:35:43 PM PDT 24
Finished Jul 06 06:53:01 PM PDT 24
Peak memory 201908 kb
Host smart-37857c10-0234-4d1b-9820-016ddd5d28a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870352133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.2870352133
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.1256911467
Short name T262
Test name
Test status
Simulation time 176440329908 ps
CPU time 387.72 seconds
Started Jul 06 06:35:44 PM PDT 24
Finished Jul 06 06:42:12 PM PDT 24
Peak memory 201992 kb
Host smart-0551018c-f7d4-4456-af0a-c9a3839ae0d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256911467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.1256911467
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.1347679817
Short name T751
Test name
Test status
Simulation time 606731009873 ps
CPU time 693.82 seconds
Started Jul 06 06:35:43 PM PDT 24
Finished Jul 06 06:47:17 PM PDT 24
Peak memory 201916 kb
Host smart-9c3b1154-cd76-4219-ae17-2bdf910b8839
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347679817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.1347679817
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3072030813
Short name T49
Test name
Test status
Simulation time 92042848906 ps
CPU time 482.85 seconds
Started Jul 06 06:35:48 PM PDT 24
Finished Jul 06 06:43:51 PM PDT 24
Peak memory 202280 kb
Host smart-8f11087f-ac77-41a1-aef7-8bc7d4152fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072030813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3072030813
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.4060540007
Short name T568
Test name
Test status
Simulation time 26464993952 ps
CPU time 59.55 seconds
Started Jul 06 06:35:47 PM PDT 24
Finished Jul 06 06:36:46 PM PDT 24
Peak memory 201732 kb
Host smart-b868bde8-0013-4bd1-84ea-639b564cdb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060540007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.4060540007
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2860968300
Short name T425
Test name
Test status
Simulation time 4715561645 ps
CPU time 10.52 seconds
Started Jul 06 06:35:48 PM PDT 24
Finished Jul 06 06:35:59 PM PDT 24
Peak memory 201728 kb
Host smart-98499813-6ebe-423e-84db-d97fd4b18dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860968300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2860968300
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2516259163
Short name T691
Test name
Test status
Simulation time 5759831780 ps
CPU time 13.2 seconds
Started Jul 06 06:35:43 PM PDT 24
Finished Jul 06 06:35:57 PM PDT 24
Peak memory 201744 kb
Host smart-c0f633b8-4ba1-4473-a506-f6efd96c9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516259163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2516259163
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.2011000834
Short name T706
Test name
Test status
Simulation time 333097068738 ps
CPU time 542.88 seconds
Started Jul 06 06:35:47 PM PDT 24
Finished Jul 06 06:44:50 PM PDT 24
Peak memory 210384 kb
Host smart-6d3468d6-30c8-4103-b944-779b57daab98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011000834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.2011000834
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3444806840
Short name T64
Test name
Test status
Simulation time 110306332782 ps
CPU time 454.09 seconds
Started Jul 06 06:35:47 PM PDT 24
Finished Jul 06 06:43:22 PM PDT 24
Peak memory 211640 kb
Host smart-f98ebbd9-c476-4c6d-abe6-3acb5c681f2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444806840 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3444806840
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.1434199679
Short name T577
Test name
Test status
Simulation time 303458844 ps
CPU time 0.76 seconds
Started Jul 06 06:36:00 PM PDT 24
Finished Jul 06 06:36:02 PM PDT 24
Peak memory 201612 kb
Host smart-4e1d504c-36c4-4fc8-bb55-2af77a2a0b68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434199679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.1434199679
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.375857151
Short name T752
Test name
Test status
Simulation time 523945183038 ps
CPU time 450.48 seconds
Started Jul 06 06:35:56 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 201912 kb
Host smart-97d6eb62-5023-4378-9bdb-f7b8f8830f13
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375857151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gati
ng.375857151
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2098884796
Short name T758
Test name
Test status
Simulation time 167247031183 ps
CPU time 103.74 seconds
Started Jul 06 06:35:57 PM PDT 24
Finished Jul 06 06:37:41 PM PDT 24
Peak memory 201900 kb
Host smart-55ed8e2e-cd33-4c5d-9f7d-cf3f754589b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098884796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2098884796
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2035119072
Short name T437
Test name
Test status
Simulation time 506049125733 ps
CPU time 1225.13 seconds
Started Jul 06 06:35:52 PM PDT 24
Finished Jul 06 06:56:17 PM PDT 24
Peak memory 201936 kb
Host smart-e39ae412-9d77-4363-9dc9-512dcde52b98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035119072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2035119072
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1609691270
Short name T306
Test name
Test status
Simulation time 497107737369 ps
CPU time 445.45 seconds
Started Jul 06 06:35:53 PM PDT 24
Finished Jul 06 06:43:18 PM PDT 24
Peak memory 201924 kb
Host smart-90296326-ea2c-413c-aab4-1839dc48e904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609691270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1609691270
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.3984031324
Short name T182
Test name
Test status
Simulation time 329929083920 ps
CPU time 203.62 seconds
Started Jul 06 06:35:52 PM PDT 24
Finished Jul 06 06:39:16 PM PDT 24
Peak memory 201896 kb
Host smart-e13ee64b-e1fa-4dbd-96fb-d9da1e0ffb84
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984031324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.3984031324
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.129864594
Short name T243
Test name
Test status
Simulation time 360698059594 ps
CPU time 721.75 seconds
Started Jul 06 06:35:52 PM PDT 24
Finished Jul 06 06:47:54 PM PDT 24
Peak memory 201976 kb
Host smart-ec69eeab-5b0c-482f-9361-7faaa1fc7e6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129864594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_
wakeup.129864594
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.1409248916
Short name T713
Test name
Test status
Simulation time 198169392502 ps
CPU time 120.87 seconds
Started Jul 06 06:35:57 PM PDT 24
Finished Jul 06 06:37:58 PM PDT 24
Peak memory 201960 kb
Host smart-b281f143-be27-463f-8198-3320a4b1deff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409248916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.1409248916
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.3803531618
Short name T643
Test name
Test status
Simulation time 100971510146 ps
CPU time 398.39 seconds
Started Jul 06 06:36:00 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 202212 kb
Host smart-3ccbc83e-8dad-43a7-a83a-32725af9b11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803531618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.3803531618
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.3803764292
Short name T409
Test name
Test status
Simulation time 35092408365 ps
CPU time 39.06 seconds
Started Jul 06 06:36:00 PM PDT 24
Finished Jul 06 06:36:39 PM PDT 24
Peak memory 201724 kb
Host smart-cb0e71af-b2ac-4942-a9d0-48d8cccce59a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803764292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.3803764292
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.2924381119
Short name T381
Test name
Test status
Simulation time 3893467316 ps
CPU time 4.92 seconds
Started Jul 06 06:35:56 PM PDT 24
Finished Jul 06 06:36:01 PM PDT 24
Peak memory 201732 kb
Host smart-4155a32d-9602-4063-b98b-93f7a6503486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924381119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.2924381119
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.4063742283
Short name T585
Test name
Test status
Simulation time 5975666251 ps
CPU time 2.06 seconds
Started Jul 06 06:35:47 PM PDT 24
Finished Jul 06 06:35:49 PM PDT 24
Peak memory 201688 kb
Host smart-16d7f8da-fb99-47a3-97c2-0c488e76a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063742283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.4063742283
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2294363973
Short name T212
Test name
Test status
Simulation time 926545864877 ps
CPU time 2402.5 seconds
Started Jul 06 06:36:00 PM PDT 24
Finished Jul 06 07:16:03 PM PDT 24
Peak memory 210428 kb
Host smart-80086e51-8e88-4c10-9d38-bd6a26481d8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294363973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2294363973
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3918217900
Short name T515
Test name
Test status
Simulation time 398932332 ps
CPU time 1.57 seconds
Started Jul 06 06:36:19 PM PDT 24
Finished Jul 06 06:36:21 PM PDT 24
Peak memory 201684 kb
Host smart-d578a7c7-0665-4533-ad83-134890cef3ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918217900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3918217900
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.3701678450
Short name T97
Test name
Test status
Simulation time 323718945666 ps
CPU time 763.64 seconds
Started Jul 06 06:36:08 PM PDT 24
Finished Jul 06 06:48:52 PM PDT 24
Peak memory 201880 kb
Host smart-05c68d04-4027-4e09-81e6-37b785c9d979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701678450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.3701678450
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.128002314
Short name T524
Test name
Test status
Simulation time 165379107204 ps
CPU time 389.06 seconds
Started Jul 06 06:36:05 PM PDT 24
Finished Jul 06 06:42:34 PM PDT 24
Peak memory 201908 kb
Host smart-17f6a66d-e307-469f-9d13-2ee0c73cd5b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=128002314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.128002314
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.1667101125
Short name T329
Test name
Test status
Simulation time 487531228026 ps
CPU time 1083.32 seconds
Started Jul 06 06:36:04 PM PDT 24
Finished Jul 06 06:54:08 PM PDT 24
Peak memory 201916 kb
Host smart-4d6db7e8-b462-42c4-a361-f2a8e3f11ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667101125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.1667101125
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1298092226
Short name T571
Test name
Test status
Simulation time 161895201043 ps
CPU time 179.26 seconds
Started Jul 06 06:36:05 PM PDT 24
Finished Jul 06 06:39:05 PM PDT 24
Peak memory 201904 kb
Host smart-660405b5-3525-4141-b597-1a182dee0803
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298092226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1298092226
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.417255611
Short name T396
Test name
Test status
Simulation time 193517560938 ps
CPU time 102.91 seconds
Started Jul 06 06:36:10 PM PDT 24
Finished Jul 06 06:37:53 PM PDT 24
Peak memory 201928 kb
Host smart-fd035eca-7214-48ad-8670-937ad72cd0d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417255611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_
wakeup.417255611
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3507333543
Short name T565
Test name
Test status
Simulation time 198824441078 ps
CPU time 429.4 seconds
Started Jul 06 06:36:10 PM PDT 24
Finished Jul 06 06:43:19 PM PDT 24
Peak memory 201900 kb
Host smart-c1f6166b-7de1-40f4-a2ba-299008bc0b32
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507333543 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3507333543
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3683335599
Short name T793
Test name
Test status
Simulation time 102662098866 ps
CPU time 340.11 seconds
Started Jul 06 06:36:15 PM PDT 24
Finished Jul 06 06:41:55 PM PDT 24
Peak memory 202248 kb
Host smart-f0de23b0-df79-4708-9b80-cf0a33678d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683335599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3683335599
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1474774401
Short name T513
Test name
Test status
Simulation time 37744924533 ps
CPU time 23.72 seconds
Started Jul 06 06:36:08 PM PDT 24
Finished Jul 06 06:36:32 PM PDT 24
Peak memory 201724 kb
Host smart-c7e20bc2-e5b8-4956-b97c-0f16bb7ebe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474774401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1474774401
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.1148725847
Short name T687
Test name
Test status
Simulation time 3223140372 ps
CPU time 4.2 seconds
Started Jul 06 06:36:10 PM PDT 24
Finished Jul 06 06:36:15 PM PDT 24
Peak memory 201716 kb
Host smart-e1b907df-54a8-4f47-a28f-20183aeb3944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148725847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.1148725847
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.3489837668
Short name T488
Test name
Test status
Simulation time 5708536642 ps
CPU time 13.44 seconds
Started Jul 06 06:36:00 PM PDT 24
Finished Jul 06 06:36:14 PM PDT 24
Peak memory 201696 kb
Host smart-a9235f45-6cdc-4e2d-b605-0b802b0e3c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489837668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.3489837668
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3139932628
Short name T737
Test name
Test status
Simulation time 389581466626 ps
CPU time 1143.31 seconds
Started Jul 06 06:36:18 PM PDT 24
Finished Jul 06 06:55:22 PM PDT 24
Peak memory 218544 kb
Host smart-16712b6b-1ba2-4eee-a051-68ca8e3bfca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139932628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3139932628
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.2148688916
Short name T788
Test name
Test status
Simulation time 142462032201 ps
CPU time 44.21 seconds
Started Jul 06 06:36:12 PM PDT 24
Finished Jul 06 06:36:57 PM PDT 24
Peak memory 201980 kb
Host smart-2ac46deb-82dd-4772-9ef0-b84efda96cfd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148688916 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.2148688916
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2725089994
Short name T779
Test name
Test status
Simulation time 302494292 ps
CPU time 1.15 seconds
Started Jul 06 06:36:28 PM PDT 24
Finished Jul 06 06:36:29 PM PDT 24
Peak memory 201656 kb
Host smart-98409ed8-bd84-4076-ad09-d1f43825813b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725089994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2725089994
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2377664090
Short name T228
Test name
Test status
Simulation time 326484551289 ps
CPU time 658.3 seconds
Started Jul 06 06:36:21 PM PDT 24
Finished Jul 06 06:47:20 PM PDT 24
Peak memory 201952 kb
Host smart-1c8e03ee-7018-4452-8ce9-d758865e47bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377664090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2377664090
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.38951280
Short name T278
Test name
Test status
Simulation time 162570057562 ps
CPU time 379.8 seconds
Started Jul 06 06:36:18 PM PDT 24
Finished Jul 06 06:42:38 PM PDT 24
Peak memory 201920 kb
Host smart-4db8990c-06b2-4bd8-8fe0-737cf342a908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38951280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.38951280
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.66250530
Short name T676
Test name
Test status
Simulation time 495475341686 ps
CPU time 1181.65 seconds
Started Jul 06 06:36:22 PM PDT 24
Finished Jul 06 06:56:04 PM PDT 24
Peak memory 201924 kb
Host smart-7c765200-5204-446a-bd12-8f979d9f3ee1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=66250530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt
_fixed.66250530
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.245158498
Short name T281
Test name
Test status
Simulation time 162400140265 ps
CPU time 363.18 seconds
Started Jul 06 06:36:17 PM PDT 24
Finished Jul 06 06:42:21 PM PDT 24
Peak memory 201896 kb
Host smart-4df57376-7452-4ce5-98b3-226b50817a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245158498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.245158498
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2818693548
Short name T704
Test name
Test status
Simulation time 330954649553 ps
CPU time 46.39 seconds
Started Jul 06 06:36:17 PM PDT 24
Finished Jul 06 06:37:04 PM PDT 24
Peak memory 201860 kb
Host smart-151f4634-ba50-4b6e-89f6-41a3e5c2a565
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818693548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2818693548
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.2505536030
Short name T266
Test name
Test status
Simulation time 165889197322 ps
CPU time 197.02 seconds
Started Jul 06 06:36:21 PM PDT 24
Finished Jul 06 06:39:38 PM PDT 24
Peak memory 201956 kb
Host smart-3eb73b30-3cc4-4f63-82ab-dad17d3cde78
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505536030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.2505536030
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1649986629
Short name T730
Test name
Test status
Simulation time 208014731045 ps
CPU time 222.69 seconds
Started Jul 06 06:36:22 PM PDT 24
Finished Jul 06 06:40:05 PM PDT 24
Peak memory 201980 kb
Host smart-b85cdb85-20f2-476a-a26e-780f1902b6cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649986629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1649986629
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2086139236
Short name T201
Test name
Test status
Simulation time 69971175713 ps
CPU time 296.2 seconds
Started Jul 06 06:36:27 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 202272 kb
Host smart-83ac82f4-ff68-4358-bdbb-7d2985dc2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086139236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2086139236
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.866828286
Short name T509
Test name
Test status
Simulation time 30810215175 ps
CPU time 11.78 seconds
Started Jul 06 06:36:22 PM PDT 24
Finished Jul 06 06:36:34 PM PDT 24
Peak memory 201728 kb
Host smart-daeb158f-2ac7-4c76-8719-93d8ea4cea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866828286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.866828286
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.1706855160
Short name T2
Test name
Test status
Simulation time 3932955377 ps
CPU time 2.01 seconds
Started Jul 06 06:36:25 PM PDT 24
Finished Jul 06 06:36:27 PM PDT 24
Peak memory 201716 kb
Host smart-ce312828-9595-4f9e-b821-a592e8803cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706855160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.1706855160
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2513716321
Short name T438
Test name
Test status
Simulation time 5803681106 ps
CPU time 14.88 seconds
Started Jul 06 06:36:17 PM PDT 24
Finished Jul 06 06:36:32 PM PDT 24
Peak memory 201716 kb
Host smart-8bd4f0ed-d3ad-4386-89d7-bc48ca15b9c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513716321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2513716321
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1745523607
Short name T490
Test name
Test status
Simulation time 191258901099 ps
CPU time 91.06 seconds
Started Jul 06 06:36:28 PM PDT 24
Finished Jul 06 06:37:59 PM PDT 24
Peak memory 201972 kb
Host smart-64f2d459-d3ce-4efb-9628-a83fd9e4ccef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745523607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1745523607
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2332688139
Short name T471
Test name
Test status
Simulation time 428582128 ps
CPU time 1.61 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:32:38 PM PDT 24
Peak memory 201680 kb
Host smart-e67490a0-9149-4238-8e1d-29820936eefc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332688139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2332688139
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3267114755
Short name T146
Test name
Test status
Simulation time 355762389402 ps
CPU time 205.86 seconds
Started Jul 06 06:32:31 PM PDT 24
Finished Jul 06 06:35:57 PM PDT 24
Peak memory 201980 kb
Host smart-25bfc492-e5c2-43ea-bbd0-691e6ee0ffaa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267114755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3267114755
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.2460005
Short name T505
Test name
Test status
Simulation time 164411195228 ps
CPU time 376.29 seconds
Started Jul 06 06:32:27 PM PDT 24
Finished Jul 06 06:38:44 PM PDT 24
Peak memory 201936 kb
Host smart-3d2ce071-6c5a-46ca-9715-9e90470c9470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.2460005
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3053776558
Short name T652
Test name
Test status
Simulation time 162800645723 ps
CPU time 179.05 seconds
Started Jul 06 06:32:30 PM PDT 24
Finished Jul 06 06:35:29 PM PDT 24
Peak memory 201864 kb
Host smart-2d980f4e-4de7-4f0b-bb95-0222dcb42807
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053776558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3053776558
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3863235729
Short name T170
Test name
Test status
Simulation time 492702007228 ps
CPU time 104.77 seconds
Started Jul 06 06:32:28 PM PDT 24
Finished Jul 06 06:34:13 PM PDT 24
Peak memory 201844 kb
Host smart-0596a350-c72c-435a-a6df-cedc9635f09b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863235729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3863235729
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.1065584481
Short name T573
Test name
Test status
Simulation time 328221652960 ps
CPU time 665.28 seconds
Started Jul 06 06:32:32 PM PDT 24
Finished Jul 06 06:43:38 PM PDT 24
Peak memory 201916 kb
Host smart-aa45ce95-364c-4311-bf15-7796618cb15c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065584481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.1065584481
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.187253063
Short name T260
Test name
Test status
Simulation time 380034218823 ps
CPU time 395.11 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:39:08 PM PDT 24
Peak memory 201932 kb
Host smart-9e989c60-27d0-49ba-9938-9a6fc9bbdd97
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187253063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.187253063
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3358002435
Short name T579
Test name
Test status
Simulation time 398162807351 ps
CPU time 913.05 seconds
Started Jul 06 06:32:31 PM PDT 24
Finished Jul 06 06:47:45 PM PDT 24
Peak memory 201916 kb
Host smart-20a5deec-7e55-4c71-941d-838ec4ac2d6f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358002435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3358002435
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.126707551
Short name T549
Test name
Test status
Simulation time 113253718857 ps
CPU time 575.46 seconds
Started Jul 06 06:32:29 PM PDT 24
Finished Jul 06 06:42:06 PM PDT 24
Peak memory 202312 kb
Host smart-025515a8-1331-4832-aac0-b2c065b01fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126707551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.126707551
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.841540082
Short name T588
Test name
Test status
Simulation time 37424302228 ps
CPU time 20.21 seconds
Started Jul 06 06:32:31 PM PDT 24
Finished Jul 06 06:32:51 PM PDT 24
Peak memory 201728 kb
Host smart-83fecd85-f7db-4a89-b2bb-e0b63f021f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841540082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.841540082
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.86784051
Short name T85
Test name
Test status
Simulation time 5275558210 ps
CPU time 8.27 seconds
Started Jul 06 06:32:30 PM PDT 24
Finished Jul 06 06:32:39 PM PDT 24
Peak memory 201760 kb
Host smart-1ade8941-c04b-4e32-a234-8484f98ed4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86784051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.86784051
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2574176435
Short name T75
Test name
Test status
Simulation time 7792118930 ps
CPU time 15.89 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:32:51 PM PDT 24
Peak memory 217212 kb
Host smart-7c97bb44-6613-401c-8acb-bd973b7fec58
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574176435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2574176435
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1457307116
Short name T699
Test name
Test status
Simulation time 6089303224 ps
CPU time 15.01 seconds
Started Jul 06 06:32:31 PM PDT 24
Finished Jul 06 06:32:46 PM PDT 24
Peak memory 201728 kb
Host smart-bd712c77-a9e4-4998-bed6-cbae371858dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457307116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1457307116
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.4117018650
Short name T220
Test name
Test status
Simulation time 349912668805 ps
CPU time 219.14 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:36:15 PM PDT 24
Peak memory 201896 kb
Host smart-4c1b0119-fc98-4515-b5af-e101a0c52ecf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117018650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
4117018650
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.3400178569
Short name T96
Test name
Test status
Simulation time 49598677429 ps
CPU time 50.69 seconds
Started Jul 06 06:32:32 PM PDT 24
Finished Jul 06 06:33:23 PM PDT 24
Peak memory 210688 kb
Host smart-f411ebf2-2c3a-461a-a1df-656b5e7fc363
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400178569 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.3400178569
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.1907917459
Short name T736
Test name
Test status
Simulation time 531394661 ps
CPU time 0.88 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:36:41 PM PDT 24
Peak memory 201620 kb
Host smart-f9384207-669a-42ca-8add-a3233b8ccc75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907917459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.1907917459
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.1640157043
Short name T277
Test name
Test status
Simulation time 170216698343 ps
CPU time 58.39 seconds
Started Jul 06 06:36:31 PM PDT 24
Finished Jul 06 06:37:29 PM PDT 24
Peak memory 201984 kb
Host smart-3cd641db-4884-4504-ba97-8c4aed9a0044
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640157043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.1640157043
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.792953842
Short name T165
Test name
Test status
Simulation time 525936963906 ps
CPU time 307.28 seconds
Started Jul 06 06:36:31 PM PDT 24
Finished Jul 06 06:41:39 PM PDT 24
Peak memory 201916 kb
Host smart-32e37b24-bba5-4f3f-a99c-92124d959ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792953842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.792953842
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.893968775
Short name T343
Test name
Test status
Simulation time 487711834302 ps
CPU time 1000.52 seconds
Started Jul 06 06:36:28 PM PDT 24
Finished Jul 06 06:53:10 PM PDT 24
Peak memory 201904 kb
Host smart-aa6e1158-e292-4373-9133-9aaf973b2029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893968775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.893968775
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2945441508
Short name T485
Test name
Test status
Simulation time 326133886021 ps
CPU time 385.37 seconds
Started Jul 06 06:36:32 PM PDT 24
Finished Jul 06 06:42:57 PM PDT 24
Peak memory 201876 kb
Host smart-69463e20-4163-4e09-a13a-f919dea5424f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945441508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2945441508
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.3667714705
Short name T655
Test name
Test status
Simulation time 167549513390 ps
CPU time 381.7 seconds
Started Jul 06 06:36:34 PM PDT 24
Finished Jul 06 06:42:56 PM PDT 24
Peak memory 201996 kb
Host smart-b5546005-c8ca-46b0-a60c-6ec14fca3fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667714705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.3667714705
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.3902782221
Short name T365
Test name
Test status
Simulation time 493192434757 ps
CPU time 1074.93 seconds
Started Jul 06 06:36:27 PM PDT 24
Finished Jul 06 06:54:22 PM PDT 24
Peak memory 201868 kb
Host smart-3c83ab2e-9059-4a6d-9b3b-81bcc35cb585
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902782221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.3902782221
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.4030763932
Short name T163
Test name
Test status
Simulation time 552948599518 ps
CPU time 1365.57 seconds
Started Jul 06 06:36:32 PM PDT 24
Finished Jul 06 06:59:18 PM PDT 24
Peak memory 201940 kb
Host smart-08351ef9-8df5-469c-b86b-429e885dfbff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030763932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.4030763932
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.3889342605
Short name T506
Test name
Test status
Simulation time 210918296682 ps
CPU time 247.34 seconds
Started Jul 06 06:36:30 PM PDT 24
Finished Jul 06 06:40:38 PM PDT 24
Peak memory 201956 kb
Host smart-f484d56c-8923-40fd-badc-abb6c0405d80
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889342605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.3889342605
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.460543956
Short name T525
Test name
Test status
Simulation time 127159035099 ps
CPU time 688.82 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:48:09 PM PDT 24
Peak memory 202216 kb
Host smart-40f5d1b9-e8a8-400f-ae55-a1643f453363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460543956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.460543956
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.2031701095
Short name T480
Test name
Test status
Simulation time 22180834373 ps
CPU time 14.16 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:36:54 PM PDT 24
Peak memory 201700 kb
Host smart-7a1749bd-b64b-4aac-85a1-4dbf59623dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031701095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.2031701095
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1301504045
Short name T369
Test name
Test status
Simulation time 5132400646 ps
CPU time 12.37 seconds
Started Jul 06 06:36:35 PM PDT 24
Finished Jul 06 06:36:48 PM PDT 24
Peak memory 201736 kb
Host smart-fc4e8fc4-d2ef-4c15-b82d-2b7f09d42070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301504045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1301504045
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.428390809
Short name T763
Test name
Test status
Simulation time 5984889039 ps
CPU time 16.04 seconds
Started Jul 06 06:36:27 PM PDT 24
Finished Jul 06 06:36:43 PM PDT 24
Peak memory 201740 kb
Host smart-fb4c6241-b9b5-4da7-8f84-4ba977f17ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428390809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.428390809
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1879860965
Short name T589
Test name
Test status
Simulation time 306742176340 ps
CPU time 1042.65 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:54:03 PM PDT 24
Peak memory 210424 kb
Host smart-cb0db839-7fdb-4a00-8164-675b64ba7210
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879860965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1879860965
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.3194610160
Short name T12
Test name
Test status
Simulation time 146845342176 ps
CPU time 70.5 seconds
Started Jul 06 06:36:36 PM PDT 24
Finished Jul 06 06:37:47 PM PDT 24
Peak memory 210228 kb
Host smart-9dc356d6-3a34-4f6a-a006-d4acec7a0c55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194610160 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.3194610160
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2567511019
Short name T484
Test name
Test status
Simulation time 489125945 ps
CPU time 0.9 seconds
Started Jul 06 06:36:47 PM PDT 24
Finished Jul 06 06:36:48 PM PDT 24
Peak memory 201604 kb
Host smart-72533aa0-f154-401d-92aa-acd21595fb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567511019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2567511019
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.2685168621
Short name T147
Test name
Test status
Simulation time 166382417679 ps
CPU time 171.85 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:39:32 PM PDT 24
Peak memory 201948 kb
Host smart-708acbed-bdd1-47f5-ae42-103d891cb85f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685168621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.2685168621
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.924258393
Short name T785
Test name
Test status
Simulation time 332086496453 ps
CPU time 202.93 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:40:04 PM PDT 24
Peak memory 201916 kb
Host smart-f24cdff5-6d05-4e00-923f-64c6b732772b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924258393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.924258393
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.1373231337
Short name T167
Test name
Test status
Simulation time 323064725839 ps
CPU time 181.01 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:39:42 PM PDT 24
Peak memory 201928 kb
Host smart-4875cc93-bfed-4206-a528-ba07ef5d0051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373231337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.1373231337
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.545237993
Short name T363
Test name
Test status
Simulation time 488165302116 ps
CPU time 438.97 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:43:59 PM PDT 24
Peak memory 201908 kb
Host smart-d6af9f82-16e8-4807-be39-33d1b45a9eb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=545237993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrup
t_fixed.545237993
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1568925690
Short name T550
Test name
Test status
Simulation time 319951378546 ps
CPU time 651.43 seconds
Started Jul 06 06:36:36 PM PDT 24
Finished Jul 06 06:47:28 PM PDT 24
Peak memory 201980 kb
Host smart-95f6acb3-32d7-415e-9308-a5cc37a7dc45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568925690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1568925690
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3015607825
Short name T716
Test name
Test status
Simulation time 161658926301 ps
CPU time 396.7 seconds
Started Jul 06 06:36:36 PM PDT 24
Finished Jul 06 06:43:13 PM PDT 24
Peak memory 201840 kb
Host smart-4ed022e9-3d07-4cdd-b0e7-c547b7919908
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015607825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3015607825
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2481389819
Short name T602
Test name
Test status
Simulation time 554603659086 ps
CPU time 178.59 seconds
Started Jul 06 06:36:41 PM PDT 24
Finished Jul 06 06:39:40 PM PDT 24
Peak memory 201952 kb
Host smart-263b7199-3994-4307-9b5e-9c3963e8abaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481389819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2481389819
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1482916635
Short name T611
Test name
Test status
Simulation time 196431966334 ps
CPU time 191.82 seconds
Started Jul 06 06:36:41 PM PDT 24
Finished Jul 06 06:39:53 PM PDT 24
Peak memory 201908 kb
Host smart-7ff86b9e-5332-4ac6-9c79-e5d47c1c2913
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482916635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1482916635
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2482540155
Short name T384
Test name
Test status
Simulation time 80664060062 ps
CPU time 425.77 seconds
Started Jul 06 06:36:44 PM PDT 24
Finished Jul 06 06:43:50 PM PDT 24
Peak memory 202156 kb
Host smart-2ba5b92c-8d2e-45d9-9bc1-0f20c2308dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482540155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2482540155
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3962073461
Short name T555
Test name
Test status
Simulation time 45454477712 ps
CPU time 102.85 seconds
Started Jul 06 06:36:46 PM PDT 24
Finished Jul 06 06:38:29 PM PDT 24
Peak memory 201712 kb
Host smart-5acd385d-8325-4b5b-83cd-a9766adf44f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962073461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3962073461
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.826373667
Short name T483
Test name
Test status
Simulation time 2752762569 ps
CPU time 2.33 seconds
Started Jul 06 06:36:40 PM PDT 24
Finished Jul 06 06:36:42 PM PDT 24
Peak memory 201676 kb
Host smart-efe41459-7d79-4858-a69f-287a400bc49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826373667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.826373667
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1599414724
Short name T532
Test name
Test status
Simulation time 5962921033 ps
CPU time 14.26 seconds
Started Jul 06 06:36:36 PM PDT 24
Finished Jul 06 06:36:51 PM PDT 24
Peak memory 201744 kb
Host smart-24b9169b-2f0c-460e-87de-cf4a2abf6a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599414724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1599414724
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3428487704
Short name T13
Test name
Test status
Simulation time 11968375097 ps
CPU time 15.13 seconds
Started Jul 06 06:36:44 PM PDT 24
Finished Jul 06 06:36:59 PM PDT 24
Peak memory 218444 kb
Host smart-00796b1d-475d-44cb-ab0e-2adc6cb3307d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428487704 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3428487704
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.121923593
Short name T578
Test name
Test status
Simulation time 392539108 ps
CPU time 1.47 seconds
Started Jul 06 06:36:55 PM PDT 24
Finished Jul 06 06:36:57 PM PDT 24
Peak memory 201668 kb
Host smart-7c1b57fd-a5e0-437c-b50a-c688a8807682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121923593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.121923593
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2516863646
Short name T601
Test name
Test status
Simulation time 166045602676 ps
CPU time 22.42 seconds
Started Jul 06 06:36:50 PM PDT 24
Finished Jul 06 06:37:13 PM PDT 24
Peak memory 201996 kb
Host smart-a66dc3a9-2cdb-427c-8b78-f4d3f5cc3d2e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516863646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2516863646
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.1968521600
Short name T5
Test name
Test status
Simulation time 190414957172 ps
CPU time 400.86 seconds
Started Jul 06 06:36:53 PM PDT 24
Finished Jul 06 06:43:34 PM PDT 24
Peak memory 201928 kb
Host smart-35e72f02-f0e9-4ab6-a713-ad10325570a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968521600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.1968521600
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.550714574
Short name T235
Test name
Test status
Simulation time 164494227131 ps
CPU time 349.55 seconds
Started Jul 06 06:36:48 PM PDT 24
Finished Jul 06 06:42:37 PM PDT 24
Peak memory 201864 kb
Host smart-08224ac3-c799-458e-ab0a-0de362a32ea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550714574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.550714574
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.4198849088
Short name T394
Test name
Test status
Simulation time 163385669315 ps
CPU time 60.51 seconds
Started Jul 06 06:36:48 PM PDT 24
Finished Jul 06 06:37:49 PM PDT 24
Peak memory 201856 kb
Host smart-456ba12f-01b6-4293-84ad-905140baacf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198849088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.4198849088
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2207131858
Short name T403
Test name
Test status
Simulation time 167674079978 ps
CPU time 316.76 seconds
Started Jul 06 06:36:50 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 201920 kb
Host smart-440dbf2b-4f1f-4189-b441-f13b1cfe0589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207131858 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2207131858
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1811046147
Short name T159
Test name
Test status
Simulation time 488074716293 ps
CPU time 1115.49 seconds
Started Jul 06 06:36:47 PM PDT 24
Finished Jul 06 06:55:23 PM PDT 24
Peak memory 201896 kb
Host smart-6feca874-4eda-46c8-8102-685ae8247c26
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811046147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1811046147
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.1496170002
Short name T338
Test name
Test status
Simulation time 640865510372 ps
CPU time 396.58 seconds
Started Jul 06 06:36:48 PM PDT 24
Finished Jul 06 06:43:25 PM PDT 24
Peak memory 201936 kb
Host smart-8e07c89a-ea37-4613-b78c-b3fa08720333
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496170002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.1496170002
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3411461396
Short name T786
Test name
Test status
Simulation time 625860994253 ps
CPU time 222.98 seconds
Started Jul 06 06:36:47 PM PDT 24
Finished Jul 06 06:40:30 PM PDT 24
Peak memory 201904 kb
Host smart-544cd631-1c6e-450b-9912-cc16e5c15566
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411461396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3411461396
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.3833473937
Short name T598
Test name
Test status
Simulation time 122599088397 ps
CPU time 587.24 seconds
Started Jul 06 06:36:52 PM PDT 24
Finished Jul 06 06:46:40 PM PDT 24
Peak memory 202280 kb
Host smart-75d4cf6a-2edd-400e-9192-2580258add95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833473937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.3833473937
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2596024597
Short name T195
Test name
Test status
Simulation time 29005675522 ps
CPU time 63.65 seconds
Started Jul 06 06:36:53 PM PDT 24
Finished Jul 06 06:37:57 PM PDT 24
Peak memory 201712 kb
Host smart-a227b48c-96c3-42c9-87ae-9346e0f23703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596024597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2596024597
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.4217581418
Short name T528
Test name
Test status
Simulation time 4562859010 ps
CPU time 3.35 seconds
Started Jul 06 06:36:53 PM PDT 24
Finished Jul 06 06:36:57 PM PDT 24
Peak memory 201708 kb
Host smart-d7169638-bcb6-4b05-a522-3b9e562656e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217581418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.4217581418
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.3079258251
Short name T787
Test name
Test status
Simulation time 6017282331 ps
CPU time 7.88 seconds
Started Jul 06 06:36:49 PM PDT 24
Finished Jul 06 06:36:57 PM PDT 24
Peak memory 201696 kb
Host smart-931fbc66-33ed-436e-91af-e7d9907d8092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079258251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.3079258251
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.733375724
Short name T315
Test name
Test status
Simulation time 170557584714 ps
CPU time 171.29 seconds
Started Jul 06 06:36:57 PM PDT 24
Finished Jul 06 06:39:48 PM PDT 24
Peak memory 201968 kb
Host smart-c0c12068-b149-48aa-a95e-74e5e2dfd4df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733375724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all.
733375724
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.1853283680
Short name T457
Test name
Test status
Simulation time 330162931 ps
CPU time 1.03 seconds
Started Jul 06 06:37:08 PM PDT 24
Finished Jul 06 06:37:09 PM PDT 24
Peak memory 201696 kb
Host smart-79565c2a-fdbe-4e96-9a89-6df2f024eb1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853283680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.1853283680
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.2485596247
Short name T665
Test name
Test status
Simulation time 161840114508 ps
CPU time 183.79 seconds
Started Jul 06 06:37:04 PM PDT 24
Finished Jul 06 06:40:08 PM PDT 24
Peak memory 201908 kb
Host smart-e0128f8c-0735-4913-b3ac-cb982ab74cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2485596247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.2485596247
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.2220262811
Short name T305
Test name
Test status
Simulation time 167030933971 ps
CPU time 81.23 seconds
Started Jul 06 06:36:58 PM PDT 24
Finished Jul 06 06:38:20 PM PDT 24
Peak memory 201976 kb
Host smart-305082f3-1344-41d4-9e63-c07284cb3844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220262811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.2220262811
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2903488320
Short name T608
Test name
Test status
Simulation time 481540097609 ps
CPU time 1108.71 seconds
Started Jul 06 06:37:00 PM PDT 24
Finished Jul 06 06:55:29 PM PDT 24
Peak memory 201916 kb
Host smart-0e9748d0-660a-4277-bc97-ca14a7c91a38
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903488320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2903488320
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3088835599
Short name T78
Test name
Test status
Simulation time 166311233664 ps
CPU time 109.7 seconds
Started Jul 06 06:36:57 PM PDT 24
Finished Jul 06 06:38:47 PM PDT 24
Peak memory 201968 kb
Host smart-cfbfe11e-9aab-48ea-ba17-bbfba06893f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088835599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3088835599
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.3893501571
Short name T700
Test name
Test status
Simulation time 165171205833 ps
CPU time 397.74 seconds
Started Jul 06 06:37:00 PM PDT 24
Finished Jul 06 06:43:38 PM PDT 24
Peak memory 201892 kb
Host smart-c49696e6-ebf7-4909-b9a7-a8fdbc01b031
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893501571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.3893501571
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.3476069608
Short name T586
Test name
Test status
Simulation time 176460694742 ps
CPU time 196.51 seconds
Started Jul 06 06:36:58 PM PDT 24
Finished Jul 06 06:40:15 PM PDT 24
Peak memory 201996 kb
Host smart-f79d4c22-d8ce-4348-bc26-b4c2cacad788
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476069608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.3476069608
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.3454940008
Short name T639
Test name
Test status
Simulation time 589526851842 ps
CPU time 691.2 seconds
Started Jul 06 06:36:59 PM PDT 24
Finished Jul 06 06:48:31 PM PDT 24
Peak memory 201900 kb
Host smart-1dcd4964-f1bc-4a85-866e-56613229e079
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454940008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.3454940008
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1721105895
Short name T207
Test name
Test status
Simulation time 77556296509 ps
CPU time 384.87 seconds
Started Jul 06 06:37:06 PM PDT 24
Finished Jul 06 06:43:31 PM PDT 24
Peak memory 202264 kb
Host smart-a4240b39-82d9-4867-98a0-6ac607d9fd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721105895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1721105895
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.316616448
Short name T191
Test name
Test status
Simulation time 25912179397 ps
CPU time 58.57 seconds
Started Jul 06 06:37:06 PM PDT 24
Finished Jul 06 06:38:04 PM PDT 24
Peak memory 201744 kb
Host smart-0b24a681-a375-4d9f-8867-3d708cce8109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316616448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.316616448
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.610863197
Short name T650
Test name
Test status
Simulation time 3041310468 ps
CPU time 4.23 seconds
Started Jul 06 06:37:06 PM PDT 24
Finished Jul 06 06:37:10 PM PDT 24
Peak memory 201740 kb
Host smart-6772258e-0af3-451b-9271-743b4fc1d7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610863197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.610863197
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.208049730
Short name T134
Test name
Test status
Simulation time 6008225677 ps
CPU time 7.35 seconds
Started Jul 06 06:36:56 PM PDT 24
Finished Jul 06 06:37:04 PM PDT 24
Peak memory 201668 kb
Host smart-81a157c6-17f4-4657-a4da-aaf230387a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208049730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.208049730
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.368076063
Short name T597
Test name
Test status
Simulation time 173685999872 ps
CPU time 377.77 seconds
Started Jul 06 06:37:08 PM PDT 24
Finished Jul 06 06:43:26 PM PDT 24
Peak memory 201916 kb
Host smart-a2b138af-b08c-4e8e-b4de-3a4389a5e835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368076063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all.
368076063
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.3758263106
Short name T738
Test name
Test status
Simulation time 248013975824 ps
CPU time 102.88 seconds
Started Jul 06 06:37:04 PM PDT 24
Finished Jul 06 06:38:47 PM PDT 24
Peak memory 217992 kb
Host smart-590d64a0-b201-4696-85ed-2788920f460d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758263106 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.3758263106
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1698259905
Short name T518
Test name
Test status
Simulation time 473550168 ps
CPU time 1.15 seconds
Started Jul 06 06:37:15 PM PDT 24
Finished Jul 06 06:37:17 PM PDT 24
Peak memory 201652 kb
Host smart-e0ad71dc-d4e4-436c-a3b6-3822fdb93374
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698259905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1698259905
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.443560578
Short name T11
Test name
Test status
Simulation time 163625106317 ps
CPU time 396.4 seconds
Started Jul 06 06:39:02 PM PDT 24
Finished Jul 06 06:45:39 PM PDT 24
Peak memory 201904 kb
Host smart-d684898d-3c61-40b3-9c34-2ae5ff47e329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443560578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.443560578
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3742125441
Short name T181
Test name
Test status
Simulation time 154420485795 ps
CPU time 332.74 seconds
Started Jul 06 06:37:08 PM PDT 24
Finished Jul 06 06:42:41 PM PDT 24
Peak memory 201896 kb
Host smart-bf090788-7f28-4b32-b787-6cfb2a8137cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742125441 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3742125441
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3906459126
Short name T361
Test name
Test status
Simulation time 163860761932 ps
CPU time 200.03 seconds
Started Jul 06 06:37:09 PM PDT 24
Finished Jul 06 06:40:29 PM PDT 24
Peak memory 201896 kb
Host smart-fd01e141-bac2-4cfd-bfa4-11b1b19e20ea
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906459126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3906459126
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.1815565783
Short name T542
Test name
Test status
Simulation time 157836970063 ps
CPU time 331.15 seconds
Started Jul 06 06:37:09 PM PDT 24
Finished Jul 06 06:42:40 PM PDT 24
Peak memory 201904 kb
Host smart-80a30112-1b07-4b55-a75f-4553c3618410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815565783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.1815565783
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.623561009
Short name T84
Test name
Test status
Simulation time 495735179241 ps
CPU time 541.12 seconds
Started Jul 06 06:37:08 PM PDT 24
Finished Jul 06 06:46:09 PM PDT 24
Peak memory 201936 kb
Host smart-b50dfec4-2be2-440e-bd49-0e0d26cea2e5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=623561009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fixe
d.623561009
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1703176095
Short name T689
Test name
Test status
Simulation time 172493524835 ps
CPU time 202.77 seconds
Started Jul 06 06:37:12 PM PDT 24
Finished Jul 06 06:40:35 PM PDT 24
Peak memory 201944 kb
Host smart-a67259b4-287e-4977-99db-fb2408662888
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703176095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1703176095
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.437267620
Short name T688
Test name
Test status
Simulation time 391090119617 ps
CPU time 82.94 seconds
Started Jul 06 06:37:12 PM PDT 24
Finished Jul 06 06:38:35 PM PDT 24
Peak memory 201840 kb
Host smart-0206ac94-72fb-4af8-82a5-fd1109760a78
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437267620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.437267620
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1862410397
Short name T203
Test name
Test status
Simulation time 119767270877 ps
CPU time 603.88 seconds
Started Jul 06 06:37:15 PM PDT 24
Finished Jul 06 06:47:19 PM PDT 24
Peak memory 202216 kb
Host smart-52719335-e788-437c-9560-30b571313a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862410397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1862410397
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.1102691263
Short name T575
Test name
Test status
Simulation time 41332543076 ps
CPU time 9.71 seconds
Started Jul 06 06:37:16 PM PDT 24
Finished Jul 06 06:37:26 PM PDT 24
Peak memory 201736 kb
Host smart-42085a29-5b6e-496c-ab4f-368d28fe3b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102691263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.1102691263
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.3272850264
Short name T399
Test name
Test status
Simulation time 3099446250 ps
CPU time 2.64 seconds
Started Jul 06 06:37:15 PM PDT 24
Finished Jul 06 06:37:18 PM PDT 24
Peak memory 201680 kb
Host smart-ff925ea5-a766-454a-91d3-ef4af429d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272850264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.3272850264
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1440979329
Short name T693
Test name
Test status
Simulation time 6016990311 ps
CPU time 4.34 seconds
Started Jul 06 06:37:08 PM PDT 24
Finished Jul 06 06:37:12 PM PDT 24
Peak memory 201724 kb
Host smart-5af08127-3e81-44dc-980d-d7e2e9fcbc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440979329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1440979329
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.2026619332
Short name T276
Test name
Test status
Simulation time 516167144422 ps
CPU time 1839.54 seconds
Started Jul 06 06:37:16 PM PDT 24
Finished Jul 06 07:07:56 PM PDT 24
Peak memory 210460 kb
Host smart-bcaabd43-d5d8-49c1-97d1-2fa2d3a05ff6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026619332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.2026619332
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.3326028645
Short name T99
Test name
Test status
Simulation time 377647692259 ps
CPU time 114.17 seconds
Started Jul 06 06:37:16 PM PDT 24
Finished Jul 06 06:39:10 PM PDT 24
Peak memory 210244 kb
Host smart-a550ebfa-ca2f-4b84-a5d2-c35fe2dbf5b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326028645 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.3326028645
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1056662820
Short name T548
Test name
Test status
Simulation time 330542979 ps
CPU time 0.81 seconds
Started Jul 06 06:37:29 PM PDT 24
Finished Jul 06 06:37:30 PM PDT 24
Peak memory 201680 kb
Host smart-26de7826-ac99-41b7-82fe-d7e63971173f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056662820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1056662820
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2456867921
Short name T194
Test name
Test status
Simulation time 348877381030 ps
CPU time 794.56 seconds
Started Jul 06 06:37:24 PM PDT 24
Finished Jul 06 06:50:39 PM PDT 24
Peak memory 201920 kb
Host smart-05346a0c-1213-446f-a3b9-6b7c3f5a50e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456867921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2456867921
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2630872098
Short name T404
Test name
Test status
Simulation time 161197139082 ps
CPU time 32.89 seconds
Started Jul 06 06:37:21 PM PDT 24
Finished Jul 06 06:37:54 PM PDT 24
Peak memory 201884 kb
Host smart-61139d8b-7d69-406d-9c7e-1a84c5e6492d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630872098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2630872098
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.3688919111
Short name T697
Test name
Test status
Simulation time 162236549201 ps
CPU time 23.08 seconds
Started Jul 06 06:37:15 PM PDT 24
Finished Jul 06 06:37:39 PM PDT 24
Peak memory 201940 kb
Host smart-45c59866-2e3a-4aac-8c84-fa06708cea09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688919111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.3688919111
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.343711256
Short name T198
Test name
Test status
Simulation time 489829822168 ps
CPU time 818.48 seconds
Started Jul 06 06:37:20 PM PDT 24
Finished Jul 06 06:50:59 PM PDT 24
Peak memory 201948 kb
Host smart-7e4a9c7b-c4e1-496b-8028-fd1c1a4bc901
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=343711256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.343711256
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.1874764102
Short name T670
Test name
Test status
Simulation time 200736353379 ps
CPU time 242.38 seconds
Started Jul 06 06:37:27 PM PDT 24
Finished Jul 06 06:41:30 PM PDT 24
Peak memory 201828 kb
Host smart-273e14b2-5a93-4bbe-97b5-517f5a63532f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874764102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.1874764102
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.529531030
Short name T732
Test name
Test status
Simulation time 67325482602 ps
CPU time 277.2 seconds
Started Jul 06 06:37:25 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 202236 kb
Host smart-72169a4c-56c9-4efb-995b-6db65c86b306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=529531030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.529531030
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1189990940
Short name T757
Test name
Test status
Simulation time 30318822052 ps
CPU time 64.6 seconds
Started Jul 06 06:37:24 PM PDT 24
Finished Jul 06 06:38:29 PM PDT 24
Peak memory 201720 kb
Host smart-3ab085ab-6310-4537-b315-33fa7546cca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189990940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1189990940
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4098656338
Short name T633
Test name
Test status
Simulation time 2901793755 ps
CPU time 7.85 seconds
Started Jul 06 06:37:25 PM PDT 24
Finished Jul 06 06:37:33 PM PDT 24
Peak memory 201732 kb
Host smart-e75a4ecf-b007-4d05-8e8b-64f83d315afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098656338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4098656338
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2852588400
Short name T622
Test name
Test status
Simulation time 5757107761 ps
CPU time 15.12 seconds
Started Jul 06 06:37:19 PM PDT 24
Finished Jul 06 06:37:34 PM PDT 24
Peak memory 201752 kb
Host smart-d4dd5805-5a4a-4a0e-80c3-676b2f9a14a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852588400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2852588400
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2714379743
Short name T731
Test name
Test status
Simulation time 460971417051 ps
CPU time 797.2 seconds
Started Jul 06 06:37:28 PM PDT 24
Finished Jul 06 06:50:45 PM PDT 24
Peak memory 210376 kb
Host smart-bda07de0-6b38-4d96-bc87-a1b7015c4a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714379743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2714379743
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1906583656
Short name T100
Test name
Test status
Simulation time 420305163974 ps
CPU time 602.45 seconds
Started Jul 06 06:37:29 PM PDT 24
Finished Jul 06 06:47:32 PM PDT 24
Peak memory 210608 kb
Host smart-396e6613-e4b7-4603-b0a9-2bf7713d982e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906583656 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1906583656
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.2224657516
Short name T543
Test name
Test status
Simulation time 323792317 ps
CPU time 0.95 seconds
Started Jul 06 06:37:37 PM PDT 24
Finished Jul 06 06:37:38 PM PDT 24
Peak memory 201644 kb
Host smart-4581bc09-8f2d-42f9-994d-b36ac5847c62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224657516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.2224657516
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.2097367350
Short name T236
Test name
Test status
Simulation time 499949465164 ps
CPU time 412.33 seconds
Started Jul 06 06:37:31 PM PDT 24
Finished Jul 06 06:44:23 PM PDT 24
Peak memory 201924 kb
Host smart-9a93d5ac-3c7f-4856-87f4-9ce47018eeb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097367350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.2097367350
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3858397190
Short name T290
Test name
Test status
Simulation time 163691296551 ps
CPU time 192 seconds
Started Jul 06 06:37:36 PM PDT 24
Finished Jul 06 06:40:48 PM PDT 24
Peak memory 201832 kb
Host smart-fce67cd9-a332-45cd-93a2-867da1dbadf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858397190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3858397190
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3594564841
Short name T517
Test name
Test status
Simulation time 166196941251 ps
CPU time 92.12 seconds
Started Jul 06 06:37:33 PM PDT 24
Finished Jul 06 06:39:05 PM PDT 24
Peak memory 201960 kb
Host smart-f8fb8f4a-2dcb-479a-88e4-558da06e3d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594564841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3594564841
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3494637833
Short name T569
Test name
Test status
Simulation time 169136562351 ps
CPU time 38.99 seconds
Started Jul 06 06:37:32 PM PDT 24
Finished Jul 06 06:38:11 PM PDT 24
Peak memory 201900 kb
Host smart-09de5d50-ec7e-4b69-b835-77c84d68a706
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494637833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3494637833
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2561139162
Short name T587
Test name
Test status
Simulation time 330534265099 ps
CPU time 735.4 seconds
Started Jul 06 06:37:32 PM PDT 24
Finished Jul 06 06:49:48 PM PDT 24
Peak memory 201972 kb
Host smart-f768d274-165d-47da-bac1-ea70aad511c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561139162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2561139162
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1939177652
Short name T197
Test name
Test status
Simulation time 159846905562 ps
CPU time 90.01 seconds
Started Jul 06 06:37:32 PM PDT 24
Finished Jul 06 06:39:02 PM PDT 24
Peak memory 201912 kb
Host smart-cec33e93-ca72-4018-863b-8999c27377c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939177652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1939177652
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3004448545
Short name T273
Test name
Test status
Simulation time 188826916661 ps
CPU time 401.87 seconds
Started Jul 06 06:37:33 PM PDT 24
Finished Jul 06 06:44:15 PM PDT 24
Peak memory 201964 kb
Host smart-0c9385d9-a723-402b-a6c9-4b200f9b7be6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004448545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3004448545
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.1654958718
Short name T427
Test name
Test status
Simulation time 202691857005 ps
CPU time 117.14 seconds
Started Jul 06 06:37:36 PM PDT 24
Finished Jul 06 06:39:33 PM PDT 24
Peak memory 201892 kb
Host smart-98f85eca-5274-4d16-8826-3867bde36ebd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654958718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.1654958718
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.1232455443
Short name T545
Test name
Test status
Simulation time 136034734787 ps
CPU time 683.56 seconds
Started Jul 06 06:37:37 PM PDT 24
Finished Jul 06 06:49:01 PM PDT 24
Peak memory 202164 kb
Host smart-c43bb6ae-4b43-43a1-9f65-a6468e053203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232455443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.1232455443
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.3930287246
Short name T625
Test name
Test status
Simulation time 31379937592 ps
CPU time 73.58 seconds
Started Jul 06 06:37:36 PM PDT 24
Finished Jul 06 06:38:50 PM PDT 24
Peak memory 201644 kb
Host smart-e540f887-f0fa-4b0f-836b-f6a86be53c84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930287246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.3930287246
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2074147621
Short name T422
Test name
Test status
Simulation time 3463726080 ps
CPU time 2.51 seconds
Started Jul 06 06:37:33 PM PDT 24
Finished Jul 06 06:37:35 PM PDT 24
Peak memory 201736 kb
Host smart-1217a52e-d2ac-4cd8-91de-af6f6d818724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074147621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2074147621
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.1939333667
Short name T378
Test name
Test status
Simulation time 5700300985 ps
CPU time 3.53 seconds
Started Jul 06 06:37:30 PM PDT 24
Finished Jul 06 06:37:33 PM PDT 24
Peak memory 201696 kb
Host smart-94d3ebca-cce9-43d3-9430-94a31d2ae3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939333667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.1939333667
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.408872562
Short name T620
Test name
Test status
Simulation time 459205124701 ps
CPU time 954.67 seconds
Started Jul 06 06:37:38 PM PDT 24
Finished Jul 06 06:53:33 PM PDT 24
Peak memory 201908 kb
Host smart-c07f0693-dc8d-4933-9162-6b4df7764002
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408872562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
408872562
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.196180906
Short name T523
Test name
Test status
Simulation time 97479775784 ps
CPU time 230.76 seconds
Started Jul 06 06:37:37 PM PDT 24
Finished Jul 06 06:41:28 PM PDT 24
Peak memory 218076 kb
Host smart-4d0ea215-96bb-4e51-a989-075323d4be50
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196180906 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.196180906
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.905670762
Short name T414
Test name
Test status
Simulation time 311159046 ps
CPU time 1.33 seconds
Started Jul 06 06:37:48 PM PDT 24
Finished Jul 06 06:37:50 PM PDT 24
Peak memory 201708 kb
Host smart-565b7bac-5a9f-43fa-8cfe-63f7a6264687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905670762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.905670762
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.3376909620
Short name T772
Test name
Test status
Simulation time 424448034593 ps
CPU time 494.69 seconds
Started Jul 06 06:37:46 PM PDT 24
Finished Jul 06 06:46:01 PM PDT 24
Peak memory 201924 kb
Host smart-cb8501ad-4ec6-4e38-aa15-cbe3545d9461
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376909620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.3376909620
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.194896185
Short name T140
Test name
Test status
Simulation time 165486204247 ps
CPU time 390.89 seconds
Started Jul 06 06:37:44 PM PDT 24
Finished Jul 06 06:44:15 PM PDT 24
Peak memory 201920 kb
Host smart-23322c97-3fd2-4eb5-a30e-16f25156426e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194896185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.194896185
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.1395419787
Short name T275
Test name
Test status
Simulation time 322963672321 ps
CPU time 750.58 seconds
Started Jul 06 06:37:41 PM PDT 24
Finished Jul 06 06:50:12 PM PDT 24
Peak memory 201924 kb
Host smart-aff09eb1-a02e-4554-b9f9-2cea9655805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395419787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.1395419787
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3548361948
Short name T647
Test name
Test status
Simulation time 163520718659 ps
CPU time 93.11 seconds
Started Jul 06 06:37:41 PM PDT 24
Finished Jul 06 06:39:14 PM PDT 24
Peak memory 201800 kb
Host smart-81441979-14e0-4788-8328-8cbe591d5edc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548361948 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3548361948
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.610256122
Short name T247
Test name
Test status
Simulation time 163450428754 ps
CPU time 28.63 seconds
Started Jul 06 06:37:40 PM PDT 24
Finished Jul 06 06:38:09 PM PDT 24
Peak memory 201836 kb
Host smart-3b20b254-3046-4586-9f19-f47050971cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610256122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.610256122
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.450107366
Short name T656
Test name
Test status
Simulation time 162225112075 ps
CPU time 372.57 seconds
Started Jul 06 06:37:41 PM PDT 24
Finished Jul 06 06:43:54 PM PDT 24
Peak memory 201860 kb
Host smart-537a5e3f-3218-46e0-950e-934b617ac79f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=450107366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fixe
d.450107366
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1778515525
Short name T183
Test name
Test status
Simulation time 169561703133 ps
CPU time 372.95 seconds
Started Jul 06 06:37:47 PM PDT 24
Finished Jul 06 06:44:01 PM PDT 24
Peak memory 201848 kb
Host smart-6cb8b1b5-e965-4c73-bc52-62b47c9ad329
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778515525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1778515525
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.888422252
Short name T530
Test name
Test status
Simulation time 595994405763 ps
CPU time 367.33 seconds
Started Jul 06 06:37:44 PM PDT 24
Finished Jul 06 06:43:52 PM PDT 24
Peak memory 201904 kb
Host smart-3424db71-476f-4370-9a95-e3600032b611
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888422252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.888422252
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4027811007
Short name T204
Test name
Test status
Simulation time 104031025278 ps
CPU time 433.96 seconds
Started Jul 06 06:37:44 PM PDT 24
Finished Jul 06 06:44:59 PM PDT 24
Peak memory 202208 kb
Host smart-aeba0775-c79e-4b47-8182-b3c92da22f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027811007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4027811007
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3905695277
Short name T710
Test name
Test status
Simulation time 30065282032 ps
CPU time 33.25 seconds
Started Jul 06 06:37:47 PM PDT 24
Finished Jul 06 06:38:20 PM PDT 24
Peak memory 201732 kb
Host smart-7c799b0a-ce85-403e-ba10-b65e3c66188f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905695277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3905695277
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.533986065
Short name T657
Test name
Test status
Simulation time 4115962981 ps
CPU time 10.46 seconds
Started Jul 06 06:37:45 PM PDT 24
Finished Jul 06 06:37:55 PM PDT 24
Peak memory 201728 kb
Host smart-68cbc591-c045-45c3-aff8-00f17fc6de41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533986065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.533986065
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.2972496664
Short name T446
Test name
Test status
Simulation time 5898418893 ps
CPU time 4.33 seconds
Started Jul 06 06:37:42 PM PDT 24
Finished Jul 06 06:37:46 PM PDT 24
Peak memory 201740 kb
Host smart-63480955-b6c1-488e-b46e-2ce5b5a7bff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972496664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.2972496664
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.386444444
Short name T225
Test name
Test status
Simulation time 330849785010 ps
CPU time 458.07 seconds
Started Jul 06 06:37:48 PM PDT 24
Finished Jul 06 06:45:26 PM PDT 24
Peak memory 202216 kb
Host smart-ec0c9784-0b35-4a06-98a4-7ce74e56d0ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386444444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
386444444
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2689776324
Short name T39
Test name
Test status
Simulation time 50145948717 ps
CPU time 117.59 seconds
Started Jul 06 06:37:52 PM PDT 24
Finished Jul 06 06:39:50 PM PDT 24
Peak memory 218440 kb
Host smart-4285a5b9-08a9-45ff-ad53-65118835b772
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689776324 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2689776324
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.3778952681
Short name T753
Test name
Test status
Simulation time 463246983 ps
CPU time 1.71 seconds
Started Jul 06 06:37:57 PM PDT 24
Finished Jul 06 06:37:59 PM PDT 24
Peak memory 201652 kb
Host smart-99508ea3-4053-4bdb-a675-fd8d0f7658c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778952681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.3778952681
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3713036806
Short name T145
Test name
Test status
Simulation time 168388175614 ps
CPU time 378.06 seconds
Started Jul 06 06:37:51 PM PDT 24
Finished Jul 06 06:44:09 PM PDT 24
Peak memory 201964 kb
Host smart-25877199-0f77-4096-901f-cfa6722d2bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713036806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3713036806
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.173312472
Short name T368
Test name
Test status
Simulation time 159410538815 ps
CPU time 105.36 seconds
Started Jul 06 06:37:48 PM PDT 24
Finished Jul 06 06:39:34 PM PDT 24
Peak memory 201912 kb
Host smart-6dd154a6-e382-4abb-9772-73d340e1b947
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=173312472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.173312472
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1971118191
Short name T151
Test name
Test status
Simulation time 165181834235 ps
CPU time 368.68 seconds
Started Jul 06 06:37:50 PM PDT 24
Finished Jul 06 06:43:59 PM PDT 24
Peak memory 201988 kb
Host smart-af520dbf-d4de-457f-8adc-a4ce37fd1590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971118191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1971118191
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2479539495
Short name T466
Test name
Test status
Simulation time 328204218195 ps
CPU time 211.14 seconds
Started Jul 06 06:37:50 PM PDT 24
Finished Jul 06 06:41:21 PM PDT 24
Peak memory 201856 kb
Host smart-ee02e7b0-d66c-4425-b2a7-a2ce23d48e5f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479539495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2479539495
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.952292810
Short name T154
Test name
Test status
Simulation time 534781188131 ps
CPU time 1055.69 seconds
Started Jul 06 06:37:49 PM PDT 24
Finished Jul 06 06:55:25 PM PDT 24
Peak memory 201972 kb
Host smart-5e62253e-5a38-4286-a5cd-f421ae90c6d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952292810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_
wakeup.952292810
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2735056734
Short name T684
Test name
Test status
Simulation time 602097859124 ps
CPU time 337.16 seconds
Started Jul 06 06:37:49 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 201888 kb
Host smart-08cb8e2f-ea8b-4320-b267-5b0f8c96f428
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735056734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2735056734
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3688274677
Short name T354
Test name
Test status
Simulation time 116633221977 ps
CPU time 367.77 seconds
Started Jul 06 06:37:54 PM PDT 24
Finished Jul 06 06:44:02 PM PDT 24
Peak memory 202176 kb
Host smart-11575c0e-9bb6-42e8-8e7e-817dbefd94aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688274677 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3688274677
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.1670991798
Short name T479
Test name
Test status
Simulation time 46071539920 ps
CPU time 104.03 seconds
Started Jul 06 06:37:53 PM PDT 24
Finished Jul 06 06:39:37 PM PDT 24
Peak memory 201728 kb
Host smart-58f50ec5-10e3-4628-80ed-b60521bedeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670991798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.1670991798
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.3100806769
Short name T686
Test name
Test status
Simulation time 3988393498 ps
CPU time 9.97 seconds
Started Jul 06 06:37:53 PM PDT 24
Finished Jul 06 06:38:04 PM PDT 24
Peak memory 201708 kb
Host smart-ac7115e9-5fab-43fb-b924-cae7b1e7ad06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100806769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.3100806769
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.48384205
Short name T40
Test name
Test status
Simulation time 5798008877 ps
CPU time 6.66 seconds
Started Jul 06 06:37:52 PM PDT 24
Finished Jul 06 06:37:59 PM PDT 24
Peak memory 201720 kb
Host smart-8bec52db-9f0b-4540-842f-dac072f7132b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48384205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.48384205
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1052085859
Short name T320
Test name
Test status
Simulation time 330546645737 ps
CPU time 378.73 seconds
Started Jul 06 06:37:58 PM PDT 24
Finished Jul 06 06:44:17 PM PDT 24
Peak memory 201904 kb
Host smart-1515f0d1-55f9-4764-bb49-8b749f975757
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052085859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1052085859
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2349781998
Short name T673
Test name
Test status
Simulation time 1158936886207 ps
CPU time 251.71 seconds
Started Jul 06 06:37:53 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 218644 kb
Host smart-a26e28b9-21f0-476b-99b4-38a2e21a5a8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349781998 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2349781998
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.263823103
Short name T371
Test name
Test status
Simulation time 299535353 ps
CPU time 1.28 seconds
Started Jul 06 06:38:05 PM PDT 24
Finished Jul 06 06:38:07 PM PDT 24
Peak memory 201696 kb
Host smart-9ad3da87-07bb-43b0-9a9b-1faa0442d238
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263823103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.263823103
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.3535492302
Short name T284
Test name
Test status
Simulation time 158618573026 ps
CPU time 41.32 seconds
Started Jul 06 06:38:04 PM PDT 24
Finished Jul 06 06:38:46 PM PDT 24
Peak memory 201932 kb
Host smart-14da24d7-a044-4e7b-a0a4-cabbbf3afedf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535492302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.3535492302
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1548383918
Short name T332
Test name
Test status
Simulation time 330376618928 ps
CPU time 173.25 seconds
Started Jul 06 06:38:02 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 201976 kb
Host smart-e3007ccd-b3ed-494f-ace7-2a44fc69ebd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548383918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1548383918
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.970427025
Short name T335
Test name
Test status
Simulation time 328677202727 ps
CPU time 809.5 seconds
Started Jul 06 06:37:58 PM PDT 24
Finished Jul 06 06:51:28 PM PDT 24
Peak memory 201924 kb
Host smart-941f1830-8e36-41e8-a073-3acd8c219d86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970427025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.970427025
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.1911533079
Short name T452
Test name
Test status
Simulation time 330550855048 ps
CPU time 148.79 seconds
Started Jul 06 06:38:04 PM PDT 24
Finished Jul 06 06:40:33 PM PDT 24
Peak memory 201904 kb
Host smart-1446f73d-3043-492e-943f-0925349a91f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911533079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.1911533079
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3069829778
Short name T391
Test name
Test status
Simulation time 164713975286 ps
CPU time 37.87 seconds
Started Jul 06 06:37:57 PM PDT 24
Finished Jul 06 06:38:35 PM PDT 24
Peak memory 201916 kb
Host smart-4d5c08a9-69ea-4c18-9bda-e0a9ff4ab719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069829778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3069829778
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.2303090318
Short name T398
Test name
Test status
Simulation time 330928318183 ps
CPU time 374.71 seconds
Started Jul 06 06:37:58 PM PDT 24
Finished Jul 06 06:44:13 PM PDT 24
Peak memory 201916 kb
Host smart-e5da1f25-3510-444f-b5b9-f99abc4dfa31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303090318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.2303090318
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.928059134
Short name T176
Test name
Test status
Simulation time 537814379902 ps
CPU time 310.65 seconds
Started Jul 06 06:38:01 PM PDT 24
Finished Jul 06 06:43:12 PM PDT 24
Peak memory 201968 kb
Host smart-d5a48ff1-adb0-4462-8c93-0b640a896849
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928059134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_
wakeup.928059134
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2965648696
Short name T613
Test name
Test status
Simulation time 412655715169 ps
CPU time 524.13 seconds
Started Jul 06 06:38:01 PM PDT 24
Finished Jul 06 06:46:46 PM PDT 24
Peak memory 201912 kb
Host smart-09993ad2-eecb-4f71-94f4-8c57d83ae730
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965648696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2965648696
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2435802676
Short name T216
Test name
Test status
Simulation time 123159902400 ps
CPU time 501.86 seconds
Started Jul 06 06:38:07 PM PDT 24
Finished Jul 06 06:46:29 PM PDT 24
Peak memory 202216 kb
Host smart-61177cdf-cce1-4605-beeb-1dacc9468b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435802676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2435802676
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.4086681539
Short name T707
Test name
Test status
Simulation time 33878909836 ps
CPU time 76.33 seconds
Started Jul 06 06:38:06 PM PDT 24
Finished Jul 06 06:39:23 PM PDT 24
Peak memory 201724 kb
Host smart-2b12dfe9-5548-4a12-94de-4c60908bb442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086681539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.4086681539
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3205123661
Short name T603
Test name
Test status
Simulation time 3838481402 ps
CPU time 1.61 seconds
Started Jul 06 06:38:03 PM PDT 24
Finished Jul 06 06:38:05 PM PDT 24
Peak memory 201680 kb
Host smart-859e20f4-43de-48cf-a97d-593d90571228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205123661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3205123661
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.1917168857
Short name T617
Test name
Test status
Simulation time 5680657503 ps
CPU time 4.06 seconds
Started Jul 06 06:38:00 PM PDT 24
Finished Jul 06 06:38:04 PM PDT 24
Peak memory 201752 kb
Host smart-956e6c79-d053-4f1e-99d9-6480e48be380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917168857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.1917168857
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.3867079157
Short name T267
Test name
Test status
Simulation time 167548398465 ps
CPU time 6.24 seconds
Started Jul 06 06:38:05 PM PDT 24
Finished Jul 06 06:38:11 PM PDT 24
Peak memory 201916 kb
Host smart-c3a7c14b-65b5-4dc9-a0f9-edbf51d635c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867079157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.3867079157
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1946248605
Short name T250
Test name
Test status
Simulation time 95431348828 ps
CPU time 172.68 seconds
Started Jul 06 06:38:05 PM PDT 24
Finished Jul 06 06:40:58 PM PDT 24
Peak memory 210536 kb
Host smart-b609a4eb-a0ee-4ae4-a499-6e4793bb1238
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946248605 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1946248605
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.2767624178
Short name T749
Test name
Test status
Simulation time 423544107 ps
CPU time 1.08 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:32:34 PM PDT 24
Peak memory 201664 kb
Host smart-ad951ca7-2feb-4d98-a774-90677d55200f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767624178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.2767624178
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2234212610
Short name T252
Test name
Test status
Simulation time 493723761042 ps
CPU time 908.86 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:47:44 PM PDT 24
Peak memory 201872 kb
Host smart-773c5b1e-c0fa-4d9a-9f83-fa4d77c2c862
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234212610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2234212610
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3209553640
Short name T535
Test name
Test status
Simulation time 338804023563 ps
CPU time 759.02 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:45:14 PM PDT 24
Peak memory 201900 kb
Host smart-e6ccfe04-0768-489f-a1e8-97fcff4a1711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209553640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3209553640
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.2672874599
Short name T759
Test name
Test status
Simulation time 330235289566 ps
CPU time 169.54 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:35:23 PM PDT 24
Peak memory 201976 kb
Host smart-5c72f06a-cfa3-4562-b14d-2958ece6cb49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2672874599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.2672874599
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.3932384072
Short name T402
Test name
Test status
Simulation time 159343349590 ps
CPU time 389.74 seconds
Started Jul 06 06:32:39 PM PDT 24
Finished Jul 06 06:39:09 PM PDT 24
Peak memory 201912 kb
Host smart-0beb60f0-5c92-4ffb-bddd-65aedf5c817f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932384072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.3932384072
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.291760116
Short name T141
Test name
Test status
Simulation time 333014579317 ps
CPU time 355.1 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:38:28 PM PDT 24
Peak memory 201936 kb
Host smart-7b6ad268-7b8f-416c-9cec-a1f7a68ea673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291760116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.291760116
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.2276698670
Short name T682
Test name
Test status
Simulation time 485971534696 ps
CPU time 1090.37 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:50:45 PM PDT 24
Peak memory 201848 kb
Host smart-f7137bb6-fe59-43d7-82a9-9f1ad8859aa5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276698670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.2276698670
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.123675833
Short name T641
Test name
Test status
Simulation time 598116045046 ps
CPU time 718.62 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:44:35 PM PDT 24
Peak memory 201968 kb
Host smart-c4b639b9-40be-4064-88c9-a318a2dde086
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123675833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_w
akeup.123675833
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.4052306763
Short name T750
Test name
Test status
Simulation time 403729726084 ps
CPU time 212.8 seconds
Started Jul 06 06:32:32 PM PDT 24
Finished Jul 06 06:36:06 PM PDT 24
Peak memory 201904 kb
Host smart-228107fb-09a3-4096-9991-7b68c35d19ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052306763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.4052306763
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1146817025
Short name T46
Test name
Test status
Simulation time 73048270024 ps
CPU time 280.32 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:37:13 PM PDT 24
Peak memory 202196 kb
Host smart-f52777cb-9ab5-4967-b1a3-afd07a979457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146817025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1146817025
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.912155056
Short name T367
Test name
Test status
Simulation time 23623106507 ps
CPU time 14.01 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:32:49 PM PDT 24
Peak memory 201728 kb
Host smart-19118756-6e9d-42ab-9427-8545f4e2a75b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912155056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.912155056
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4110331197
Short name T373
Test name
Test status
Simulation time 5197326875 ps
CPU time 11.59 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:32:45 PM PDT 24
Peak memory 201736 kb
Host smart-59028e74-1672-4627-94f8-50c8b89447f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110331197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4110331197
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.568462684
Short name T410
Test name
Test status
Simulation time 5809450824 ps
CPU time 7.3 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:32:42 PM PDT 24
Peak memory 201736 kb
Host smart-2aaa9469-5359-4998-8f57-3fff3585c92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568462684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.568462684
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.3592674920
Short name T453
Test name
Test status
Simulation time 66640416495 ps
CPU time 152.3 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:35:07 PM PDT 24
Peak memory 201720 kb
Host smart-ed675c18-abd1-4efa-9777-75607071e324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592674920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
3592674920
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3430145321
Short name T599
Test name
Test status
Simulation time 192891254253 ps
CPU time 247.55 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:36:41 PM PDT 24
Peak memory 210588 kb
Host smart-197403f0-341c-4107-a116-543e049f4ee6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430145321 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3430145321
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3439161415
Short name T470
Test name
Test status
Simulation time 290637714 ps
CPU time 0.96 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:32:38 PM PDT 24
Peak memory 201648 kb
Host smart-f700d0d8-7dd8-4983-addb-4012c5441886
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439161415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3439161415
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.2898199027
Short name T321
Test name
Test status
Simulation time 175529619297 ps
CPU time 90.03 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:34:04 PM PDT 24
Peak memory 201904 kb
Host smart-de083518-5d39-4795-aca1-0bf5760fb097
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898199027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.2898199027
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.3365610878
Short name T668
Test name
Test status
Simulation time 549753404997 ps
CPU time 1243.41 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:53:20 PM PDT 24
Peak memory 201904 kb
Host smart-5dfc6667-ec4e-44ee-a7fc-c1011feb911b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365610878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.3365610878
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1410511561
Short name T288
Test name
Test status
Simulation time 332735491929 ps
CPU time 154.4 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:35:09 PM PDT 24
Peak memory 201916 kb
Host smart-20230a85-4fea-46bb-a55a-d855c67141a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410511561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1410511561
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.3984456236
Short name T456
Test name
Test status
Simulation time 330079955077 ps
CPU time 383.09 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:38:57 PM PDT 24
Peak memory 201916 kb
Host smart-e129b1fd-9e47-4b92-966f-d3c8d943c5a1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984456236 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.3984456236
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2561553289
Short name T91
Test name
Test status
Simulation time 493631773633 ps
CPU time 1151.58 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:51:47 PM PDT 24
Peak memory 201888 kb
Host smart-06db59ec-65fd-4f12-9a27-4a693eeb6244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561553289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2561553289
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.238568224
Short name T771
Test name
Test status
Simulation time 163967093885 ps
CPU time 206.93 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:36:02 PM PDT 24
Peak memory 201896 kb
Host smart-afbee761-783c-4f2d-bf75-0c7c49bb07b0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=238568224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.238568224
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.2314275736
Short name T261
Test name
Test status
Simulation time 558589181764 ps
CPU time 1166.09 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:52:02 PM PDT 24
Peak memory 201896 kb
Host smart-f53b6485-cfdb-49ff-8b30-b4a331cca1af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314275736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.2314275736
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.4254007842
Short name T539
Test name
Test status
Simulation time 196263113361 ps
CPU time 453.43 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:40:09 PM PDT 24
Peak memory 201888 kb
Host smart-7bbecb87-d141-4bd7-950f-e4bae3bc0013
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254007842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.4254007842
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.940196644
Short name T405
Test name
Test status
Simulation time 67283346388 ps
CPU time 256.88 seconds
Started Jul 06 06:32:35 PM PDT 24
Finished Jul 06 06:36:52 PM PDT 24
Peak memory 202224 kb
Host smart-12f8c39d-305d-4836-92b3-20458900717d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940196644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.940196644
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2733509207
Short name T440
Test name
Test status
Simulation time 25386577736 ps
CPU time 15.32 seconds
Started Jul 06 06:32:33 PM PDT 24
Finished Jul 06 06:32:49 PM PDT 24
Peak memory 201672 kb
Host smart-851e45b0-26bb-4cdb-8686-ab2fe1b6bc58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733509207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2733509207
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.4123983607
Short name T614
Test name
Test status
Simulation time 5614492911 ps
CPU time 1.96 seconds
Started Jul 06 06:32:34 PM PDT 24
Finished Jul 06 06:32:37 PM PDT 24
Peak memory 201732 kb
Host smart-8e2ef46e-ba4b-433e-ac7e-5ab3e675be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123983607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.4123983607
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.3772333957
Short name T590
Test name
Test status
Simulation time 5926636000 ps
CPU time 4.38 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:32:41 PM PDT 24
Peak memory 201724 kb
Host smart-8a872a36-fa58-43aa-ba61-069c5431935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772333957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.3772333957
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2398116746
Short name T493
Test name
Test status
Simulation time 45077846678 ps
CPU time 93.82 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:34:10 PM PDT 24
Peak memory 201912 kb
Host smart-593bc89d-e98c-46ac-9482-4d600cc575f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398116746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2398116746
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.2296229049
Short name T393
Test name
Test status
Simulation time 395036916 ps
CPU time 1.45 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:32:38 PM PDT 24
Peak memory 201684 kb
Host smart-91045780-362b-4a6b-b33a-b277b85f7fa2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296229049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.2296229049
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.2604953162
Short name T770
Test name
Test status
Simulation time 162103100752 ps
CPU time 348.32 seconds
Started Jul 06 06:32:38 PM PDT 24
Finished Jul 06 06:38:27 PM PDT 24
Peak memory 201992 kb
Host smart-59a06bd1-4b56-4d63-b1d7-6e5e20e9ebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604953162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.2604953162
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3919057201
Short name T166
Test name
Test status
Simulation time 495579086453 ps
CPU time 288.04 seconds
Started Jul 06 06:32:38 PM PDT 24
Finished Jul 06 06:37:26 PM PDT 24
Peak memory 201924 kb
Host smart-15827b6e-1122-4d91-9308-840fdb8ba64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919057201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3919057201
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.3512088072
Short name T580
Test name
Test status
Simulation time 328543558424 ps
CPU time 338.82 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:38:15 PM PDT 24
Peak memory 201924 kb
Host smart-5d0270ef-4965-4bda-955c-523b51ea01bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512088072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.3512088072
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2189167283
Short name T156
Test name
Test status
Simulation time 491935014587 ps
CPU time 1165.07 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:52:02 PM PDT 24
Peak memory 201928 kb
Host smart-4e3dff7d-95f5-4041-8d12-01da5e5c5a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189167283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2189167283
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.77342466
Short name T690
Test name
Test status
Simulation time 325261489013 ps
CPU time 195.23 seconds
Started Jul 06 06:32:38 PM PDT 24
Finished Jul 06 06:35:54 PM PDT 24
Peak memory 201912 kb
Host smart-a0eb25ce-10eb-4b1f-9214-bffe702a9542
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=77342466 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.77342466
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1423606887
Short name T317
Test name
Test status
Simulation time 335322971374 ps
CPU time 201.65 seconds
Started Jul 06 06:32:39 PM PDT 24
Finished Jul 06 06:36:01 PM PDT 24
Peak memory 201940 kb
Host smart-282d1d8b-13a0-465e-aa81-328a44c635b5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423606887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1423606887
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3317472105
Short name T631
Test name
Test status
Simulation time 196449687346 ps
CPU time 61.7 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:33:39 PM PDT 24
Peak memory 201908 kb
Host smart-321d16bb-e226-4ba2-aba5-e877eb37f5a6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317472105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3317472105
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3084865023
Short name T711
Test name
Test status
Simulation time 77562801841 ps
CPU time 267.37 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:37:08 PM PDT 24
Peak memory 202212 kb
Host smart-a604994a-9c6a-4345-9239-fb275d2e6dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084865023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3084865023
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.277805454
Short name T720
Test name
Test status
Simulation time 25170798171 ps
CPU time 35 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:33:13 PM PDT 24
Peak memory 201712 kb
Host smart-3f5868fe-c78c-4ca7-baa0-dea1f0cda52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277805454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.277805454
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.3123616204
Short name T748
Test name
Test status
Simulation time 3111069779 ps
CPU time 5.52 seconds
Started Jul 06 06:32:38 PM PDT 24
Finished Jul 06 06:32:44 PM PDT 24
Peak memory 201716 kb
Host smart-776f37a3-c775-4557-848d-72e7b67b2623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123616204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.3123616204
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.161527778
Short name T552
Test name
Test status
Simulation time 6057743952 ps
CPU time 4.45 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:32:42 PM PDT 24
Peak memory 201744 kb
Host smart-67520da9-ca26-478a-961a-148b782f7def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161527778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.161527778
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.2924761462
Short name T227
Test name
Test status
Simulation time 495161594537 ps
CPU time 288.39 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:37:26 PM PDT 24
Peak memory 201912 kb
Host smart-eeeaad1b-8c9e-46b4-b01a-daa7cad13a8d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924761462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
2924761462
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2980700943
Short name T224
Test name
Test status
Simulation time 56019763151 ps
CPU time 94.25 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:34:12 PM PDT 24
Peak memory 210552 kb
Host smart-83994dd6-0214-48ea-b140-01252ca10fd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980700943 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2980700943
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.3859283065
Short name T567
Test name
Test status
Simulation time 393115034 ps
CPU time 1.53 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:32:43 PM PDT 24
Peak memory 201668 kb
Host smart-763deb9a-e658-4445-a0c4-a7f6719caa7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859283065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.3859283065
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3709829907
Short name T340
Test name
Test status
Simulation time 332654595634 ps
CPU time 210.12 seconds
Started Jul 06 06:32:39 PM PDT 24
Finished Jul 06 06:36:09 PM PDT 24
Peak memory 201900 kb
Host smart-c4f50598-1718-42ba-a163-f66e631ed1e2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709829907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3709829907
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.3336879876
Short name T177
Test name
Test status
Simulation time 322645648714 ps
CPU time 189.11 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:35:46 PM PDT 24
Peak memory 201876 kb
Host smart-39868de7-f98a-4dd5-9f9c-ad8f47d90e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336879876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.3336879876
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.114442082
Short name T642
Test name
Test status
Simulation time 160531710626 ps
CPU time 91.66 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:34:09 PM PDT 24
Peak memory 201868 kb
Host smart-26465404-9d9e-49b6-b8f4-784b27b206f3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=114442082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt
_fixed.114442082
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.3668036181
Short name T190
Test name
Test status
Simulation time 328528246704 ps
CPU time 391.93 seconds
Started Jul 06 06:32:36 PM PDT 24
Finished Jul 06 06:39:08 PM PDT 24
Peak memory 201928 kb
Host smart-28299212-7f7a-4a31-9741-a84586502f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668036181 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.3668036181
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3752459889
Short name T366
Test name
Test status
Simulation time 320788889315 ps
CPU time 495.39 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:40:53 PM PDT 24
Peak memory 201872 kb
Host smart-afb0b10b-c6a3-466d-89a4-06d6a6132657
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752459889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3752459889
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.1278599576
Short name T760
Test name
Test status
Simulation time 357297452941 ps
CPU time 119.83 seconds
Started Jul 06 06:32:37 PM PDT 24
Finished Jul 06 06:34:37 PM PDT 24
Peak memory 201980 kb
Host smart-680eb246-5603-4f76-841e-c3ee012d0131
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278599576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.1278599576
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3709766509
Short name T520
Test name
Test status
Simulation time 380905476990 ps
CPU time 157.62 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:35:18 PM PDT 24
Peak memory 201900 kb
Host smart-e6fb7de7-5149-4444-86ae-d8f8a74b015d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709766509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3709766509
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.1962458660
Short name T439
Test name
Test status
Simulation time 30579328728 ps
CPU time 49.85 seconds
Started Jul 06 06:32:50 PM PDT 24
Finished Jul 06 06:33:40 PM PDT 24
Peak memory 201728 kb
Host smart-a69a5034-903b-4e9f-942c-82a8b4fbc242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962458660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.1962458660
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.3761908672
Short name T790
Test name
Test status
Simulation time 2979733548 ps
CPU time 7.95 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:32:49 PM PDT 24
Peak memory 201708 kb
Host smart-84f5d62e-2bdf-4328-9554-b0ab83a15e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761908672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.3761908672
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1376535506
Short name T544
Test name
Test status
Simulation time 5885906387 ps
CPU time 4.43 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:32:45 PM PDT 24
Peak memory 201740 kb
Host smart-97d8430e-1e18-477b-afe9-2f22740f183f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376535506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1376535506
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.3184447509
Short name T630
Test name
Test status
Simulation time 378906032313 ps
CPU time 814.79 seconds
Started Jul 06 06:32:58 PM PDT 24
Finished Jul 06 06:46:34 PM PDT 24
Peak memory 201912 kb
Host smart-2eb84eca-d320-491a-9003-fb3dd7f5334d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184447509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
3184447509
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1332025210
Short name T461
Test name
Test status
Simulation time 484286633 ps
CPU time 1.14 seconds
Started Jul 06 06:32:39 PM PDT 24
Finished Jul 06 06:32:41 PM PDT 24
Peak memory 201900 kb
Host smart-3aefbdcf-87bd-45f7-a68c-7bbd30e976e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332025210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1332025210
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.3163202062
Short name T553
Test name
Test status
Simulation time 161317488154 ps
CPU time 357.8 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:38:38 PM PDT 24
Peak memory 201900 kb
Host smart-08872a44-68a6-437b-87d9-f06fabc7cdf3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163202062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.3163202062
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.4083010279
Short name T193
Test name
Test status
Simulation time 372090754654 ps
CPU time 205.66 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:36:07 PM PDT 24
Peak memory 201984 kb
Host smart-8ad704c9-fba1-47be-9af7-a6a422f1a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083010279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.4083010279
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.2050240546
Short name T226
Test name
Test status
Simulation time 165658757772 ps
CPU time 381.74 seconds
Started Jul 06 06:32:59 PM PDT 24
Finished Jul 06 06:39:21 PM PDT 24
Peak memory 201852 kb
Host smart-5a1c00ad-895a-4991-bb1f-f8f912962e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050240546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.2050240546
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1091379388
Short name T355
Test name
Test status
Simulation time 163669154977 ps
CPU time 352.15 seconds
Started Jul 06 06:33:00 PM PDT 24
Finished Jul 06 06:38:53 PM PDT 24
Peak memory 201840 kb
Host smart-d1541b66-8fe8-479e-9132-76bdbee520d2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091379388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1091379388
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.1225397131
Short name T623
Test name
Test status
Simulation time 329753791586 ps
CPU time 300.66 seconds
Started Jul 06 06:32:43 PM PDT 24
Finished Jul 06 06:37:44 PM PDT 24
Peak memory 201936 kb
Host smart-81648ee4-3322-4cb8-b628-615393fcc00a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225397131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.1225397131
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4025919920
Short name T192
Test name
Test status
Simulation time 170119605278 ps
CPU time 93.56 seconds
Started Jul 06 06:32:48 PM PDT 24
Finished Jul 06 06:34:22 PM PDT 24
Peak memory 201856 kb
Host smart-f316e2b5-2e0b-484e-ba31-f2969cbfce53
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025919920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4025919920
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2792620807
Short name T103
Test name
Test status
Simulation time 340788356595 ps
CPU time 204.97 seconds
Started Jul 06 06:32:40 PM PDT 24
Finished Jul 06 06:36:05 PM PDT 24
Peak memory 201984 kb
Host smart-4a434ee9-7b12-474c-b48b-1e32c3557438
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792620807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2792620807
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1151452868
Short name T606
Test name
Test status
Simulation time 398369660715 ps
CPU time 877.58 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:47:19 PM PDT 24
Peak memory 201876 kb
Host smart-c478acb1-b711-4058-90d9-0d91ae6cb1f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151452868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1151452868
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.3815778872
Short name T44
Test name
Test status
Simulation time 81794730064 ps
CPU time 367.08 seconds
Started Jul 06 06:32:42 PM PDT 24
Finished Jul 06 06:38:49 PM PDT 24
Peak memory 202232 kb
Host smart-be33f6a4-baad-4d75-979d-7a148239ce90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815778872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.3815778872
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.408492498
Short name T653
Test name
Test status
Simulation time 24868659825 ps
CPU time 9.13 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:32:50 PM PDT 24
Peak memory 201732 kb
Host smart-bb575660-a9a0-4926-9395-36de37b482c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408492498 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.408492498
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.731666178
Short name T498
Test name
Test status
Simulation time 3208902043 ps
CPU time 1.15 seconds
Started Jul 06 06:32:42 PM PDT 24
Finished Jul 06 06:32:43 PM PDT 24
Peak memory 201740 kb
Host smart-98518681-c424-4732-9d00-8e548737c59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731666178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.731666178
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.579945302
Short name T663
Test name
Test status
Simulation time 5721543053 ps
CPU time 14.28 seconds
Started Jul 06 06:32:41 PM PDT 24
Finished Jul 06 06:32:55 PM PDT 24
Peak memory 201668 kb
Host smart-94fbe5e7-21fd-4908-ac18-38d348c8f5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579945302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.579945302
Directory /workspace/9.adc_ctrl_smoke/latest
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