Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7026	1			T3	26		T4	119		T6	35
testmodes[AdcCtrlTestmodeNormal]	5248	1			T1	1		T2	3		T3	12
testmodes[AdcCtrlTestmodeLowpower]	5669	1			T3	4		T4	61		T6	34
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3874	1			T3	22		T4	68		T6	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1656	1			T3	3		T4	26		T6	12
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1379	1			T3	1		T4	24		T6	11
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1686	1			T3	3		T4	26		T6	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1915	1			T2	2		T3	7		T4	20
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1313	1			T3	2		T4	19		T6	15
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1361	1			T4	25		T6	10		T10	11
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1324	1			T3	2		T4	18		T6	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2738	1			T3	1		T4	18		T6	8