Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20459

1

T3

42

T4

249

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

5435

1

T1

7

T2

3

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19989

1

T3

46

T4

240

T5

2

auto[1]

5905

1

T1

7

T2

3

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	1	1			T215	1		-	-		-	-
values[0]	39	1			T216	9		T217	1		T218	16
values[1]	675	1			T3	8		T30	2		T219	1
values[2]	767	1			T6	1		T70	17		T220	3
values[3]	755	1			T5	2		T11	8		T30	3
values[4]	565	1			T3	4		T6	15		T11	26
values[5]	492	1			T28	35		T30	3		T72	10
values[6]	671	1			T8	1		T108	1		T202	1
values[7]	664	1			T11	31		T108	1		T143	6
values[8]	853	1			T29	22		T28	23		T70	17
values[9]	3357	1			T1	7		T2	3		T4	9
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	958	1			T3	8		T30	2		T219	1
values[1]	3011	1			T1	7		T2	3		T5	2
values[2]	638	1			T11	8		T71	6		T136	23
values[3]	623	1			T6	15		T11	26		T12	8
values[4]	570	1			T3	4		T72	10		T181	7
values[5]	577	1			T8	1		T108	2		T202	1
values[6]	736	1			T11	31		T143	6		T182	2
values[7]	729	1			T29	22		T28	23		T69	1
values[8]	848	1			T28	8		T108	1		T37	8
values[9]	140	1			T4	9		T8	2		T69	1
minimum	17064	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	7		T30	2		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T139	1		T142	10		T171	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	1		T6	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1716	1			T1	1		T2	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T71	1		T136	18		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	4		T153	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	5		T11	13		T28	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T12	1		T29	12		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T72	5		T181	4		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	4		T34	7		T221	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T108	1		T202	1		T192	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	1		T108	1		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	16		T143	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T182	2		T152	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T29	11		T69	1		T146	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	11		T70	9		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T37	5		T47	3		T71	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T28	4		T108	1		T136	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T4	6		T8	1		T69	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T8	1		T177	1		T222	19
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	1		T70	8		T144	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T139	13		T150	15		T223	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T5	1		T220	2		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	892	1			T1	6		T30	2		T114	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T71	5		T136	5		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	4		T153	13		T148	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	10		T11	13		T28	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T12	7		T29	12		T28	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T72	5		T181	3		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T34	2		T221	12		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T192	2		T224	11		T225	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T144	8		T156	10		T226	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	15		T143	5		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T155	1		T149	12		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T29	11		T146	16		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T28	12		T70	8		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	3		T47	6		T71	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T28	4		T136	10		T177	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T4	3		T227	9		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T177	10		T222	13		T228	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T216	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T215	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T217	1		T21	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T216	1		T218	16		T229	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	7		T30	2		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T139	1		T142	10		T150	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	1		T70	9		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T155	13		T171	11		T230	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T136	18		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T11	4		T30	1		T70	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T6	5		T11	13		T71	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T3	4		T12	1		T29	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T28	1		T72	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T28	14		T30	1		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T108	1		T202	1		T181	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T8	1		T144	11		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	16		T143	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T108	1		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T29	11		T146	8		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T28	11		T70	9		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T4	6		T8	1		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1846	1			T1	1		T2	3		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T216	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	1		T144	5		T32	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T139	13		T150	15		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T70	8		T220	2		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T155	12		T230	1		T223	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	1		T136	5		T31	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	4		T30	2		T70	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	10		T11	13		T71	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T12	7		T29	12		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T28	4		T72	5		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T28	16		T30	2		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T181	3		T192	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T144	8		T34	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	15		T143	5		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T155	1		T149	12		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T29	11		T146	16		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T28	12		T70	8		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	3		T37	3		T47	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1057	1			T1	6		T28	4		T114	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T3	7		T30	2		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T139	14		T142	1		T171	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	2		T6	1		T220	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1235	1			T1	7		T2	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T71	6		T136	6		T31	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	5		T153	14		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	11		T11	14		T28	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	8		T29	13		T28	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T72	6		T181	4		T138	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	2		T34	5		T221	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T108	1		T202	1		T192	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T8	1		T108	1		T144	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	16		T143	6		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T182	2		T152	1		T155	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T29	12		T69	1		T146	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	13		T70	9		T143	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T37	4		T47	7		T71	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T28	6		T108	1		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T4	8		T8	1		T69	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T8	1		T177	11		T222	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T216	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T3	1		T70	8		T144	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T142	9		T171	10		T150	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T144	12		T140	20		T14	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1373	1			T38	32		T39	21		T70	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T136	17		T31	5		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	3		T142	11		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	4		T11	12		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T29	11		T28	12		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T72	4		T181	3		T145	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	2		T34	4		T221	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T192	4		T169	16		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T144	10		T156	7		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	15		T33	1		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T234	2		T149	14		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T29	10		T146	7		T13	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T28	10		T70	8		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	4		T47	2		T71	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	2		T136	11		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T4	1		T236	13		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T222	18		T237	11		T180	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T215	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T217	1		T21	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T216	9		T218	1		T229	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	7		T30	2		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	14		T142	1		T150	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T6	1		T70	9		T220	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T155	13		T171	1		T230	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T5	2		T136	6		T31	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	5		T30	3		T70	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	11		T11	14		T71	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	2		T12	8		T29	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T28	5		T72	6		T138	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T28	18		T30	3		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T108	1		T202	1		T181	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T8	1		T144	9		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T11	16		T143	6		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T108	1		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T29	12		T146	17		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T28	13		T70	9		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	8		T8	1		T37	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1423	1			T1	7		T2	3		T8	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T218	15		T229	11		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T144	1		T32	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T142	9		T150	2		T231	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T70	8		T144	12		T156	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T155	12		T171	10		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T136	17		T31	5		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T11	3		T70	14		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T6	4		T11	12		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T3	2		T29	11		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T72	4		T145	7		T171	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T28	12		T142	3		T160	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T181	3		T192	4		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T144	10		T34	4		T156	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	15		T33	1		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T149	14		T150	13		T238	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	10		T146	7		T239	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T28	10		T70	8		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T37	4		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1480	1			T28	2		T38	32		T39	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22612

1

T1

7

T2

3

T3

42

auto[ADC_CTRL_FILTER_COND_OUT]

3282

1

T3

4

T4

9

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20229

1

T3

42

T4

240

T6

132

auto[1]

5665

1

T1

7

T2

3

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T240	16		T241	12		-	-
values[0]	102	1			T150	18		T13	10		T242	23
values[1]	557	1			T11	26		T73	1		T143	6
values[2]	492	1			T28	30		T70	17		T140	11
values[3]	731	1			T12	8		T30	3		T108	1
values[4]	645	1			T8	1		T28	23		T30	3
values[5]	2900	1			T1	7		T2	3		T6	1
values[6]	831	1			T8	1		T11	31		T28	5
values[7]	761	1			T3	4		T37	8		T71	6
values[8]	549	1			T4	9		T8	1		T28	8
values[9]	1243	1			T3	8		T5	2		T6	15
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	809	1			T11	26		T73	1		T143	6
values[1]	514	1			T28	30		T70	17		T145	8
values[2]	708	1			T12	8		T30	3		T108	1
values[3]	2934	1			T1	7		T2	3		T8	1
values[4]	588	1			T6	1		T28	5		T30	3
values[5]	833	1			T8	1		T11	31		T29	22
values[6]	876	1			T3	4		T28	8		T71	6
values[7]	461	1			T4	9		T8	1		T11	8
values[8]	919	1			T3	8		T6	15		T29	24
values[9]	197	1			T5	2		T136	23		T143	5
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T143	1		T144	11		T33	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	13		T73	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T70	9		T145	8		T140	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T28	14		T178	1		T34	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T108	1		T143	1		T146	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T12	1		T30	1		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1689	1			T1	1		T2	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T153	1		T197	1		T140	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	1		T30	1		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T28	1		T108	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T29	11		T30	2		T37	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T8	1		T11	16		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	4		T71	1		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	4		T192	5		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T142	4		T157	13		T171	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	6		T8	1		T11	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T3	7		T29	12		T47	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T6	5		T219	1		T31	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T5	1		T136	18		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T137	1		T243	1		T26	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T143	5		T144	8		T33	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	13		T155	1		T239	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T70	8		T140	4		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T28	16		T34	2		T232	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T143	13		T146	16		T224	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T12	7		T30	2		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	890	1			T1	6		T28	12		T114	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T153	10		T197	12		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	2		T138	1		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	4		T71	9		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T29	11		T37	3		T70	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	15		T144	5		T32	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T28	4		T71	5		T31	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T192	2		T155	9		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T157	12		T35	1		T245	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T4	3		T11	4		T70	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T29	12		T47	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	10		T31	1		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T5	1		T136	5		T143	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T243	15		T26	4		T227	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T241	10		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T240	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T242	11		T176	1		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T150	3		T13	7		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T143	1		T144	11		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	13		T73	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T70	9		T140	7		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	14		T178	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T108	1		T220	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T12	1		T30	1		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T8	1		T28	11		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T192	1		T153	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1669	1			T1	1		T2	3		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T108	1		T69	1		T71	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T30	2		T70	15		T72	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T8	1		T11	16		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T37	5		T71	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T3	4		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T28	4		T31	7		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	6		T8	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	405	1			T3	7		T5	1		T29	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T6	5		T11	4		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T241	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T240	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T242	12		T176	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T150	15		T13	3		T16	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T143	5		T144	8		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	13		T239	6		T198	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T70	8		T140	4		T177	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T28	16		T155	1		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T220	2		T143	13		T146	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	7		T30	2		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T28	12		T30	2		T156	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T153	10		T197	12		T231	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T1	6		T29	11		T114	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T71	9		T159	12		T247	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T70	14		T72	5		T155	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	15		T28	4		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T37	3		T71	5		T153	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T192	2		T170	24		T232	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T28	4		T31	4		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T4	3		T155	9		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	1		T5	1		T29	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T6	10		T11	4		T70	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2