Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22622

1

T1

7

T2

3

T3

42

auto[ADC_CTRL_FILTER_COND_OUT]

3272

1

T3

4

T4

9

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20333

1

T3

46

T4

240

T5

2

auto[1]

5561

1

T1

7

T2

3

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T148	8		T317	1		T282	13
values[0]	94	1			T223	33		T275	13		T318	10
values[1]	605	1			T29	24		T28	31		T108	1
values[2]	784	1			T3	4		T6	1		T8	1
values[3]	698	1			T12	8		T30	3		T219	1
values[4]	641	1			T3	8		T8	1		T11	8
values[5]	634	1			T6	15		T28	5		T69	1
values[6]	719	1			T5	2		T8	1		T11	26
values[7]	686	1			T4	9		T71	6		T143	14
values[8]	550	1			T11	31		T29	22		T136	23
values[9]	3384	1			T1	7		T2	3		T9	3
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	844	1			T29	24		T28	8		T108	2
values[1]	933	1			T3	4		T6	1		T8	1
values[2]	612	1			T12	8		T30	3		T219	1
values[3]	587	1			T3	8		T8	1		T11	8
values[4]	730	1			T6	15		T8	1		T11	26
values[5]	661	1			T4	9		T5	2		T71	21
values[6]	2957	1			T1	7		T2	3		T9	3
values[7]	545	1			T70	29		T136	23		T140	6
values[8]	798	1			T30	3		T37	8		T72	10
values[9]	148	1			T178	1		T148	8		T230	5
minimum	17079	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T28	4		T108	1		T140	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T29	12		T108	1		T234	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T30	2		T47	3		T70	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	4		T6	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T30	1		T152	1		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T12	1		T219	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	7		T8	1		T28	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	4		T143	2		T31	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	13		T69	2		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T6	5		T8	1		T28	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T5	1		T71	12		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T4	6		T202	1		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T1	1		T2	3		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T137	1		T197	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T136	18		T177	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T70	15		T140	6		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T30	1		T37	5		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T72	5		T181	4		T144	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T148	1		T18	3		T319	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T178	1		T230	4		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T28	11		T244	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T28	4		T150	15		T223	21
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T29	12		T234	6		T232	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T47	6		T70	8		T138	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	5		T155	21		T156	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T30	2		T33	1		T153	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T12	7		T32	3		T232	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	1		T28	16		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T11	4		T143	9		T31	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	13		T192	2		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T6	10		T28	4		T70	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T71	9		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T4	3		T139	13		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	874	1			T1	6		T11	15		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T197	12		T177	10		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T136	5		T177	2		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T70	14		T81	13		T99	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	2		T37	3		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T72	5		T181	3		T144	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T148	7		T319	7		T215	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T230	1		T159	10		T16	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T28	12		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T148	1		T317	1		T284	7
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T282	13		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T223	12		T275	7		T318	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T299	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T28	4		T108	1		T169	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T29	12		T28	11		T234	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T30	2		T73	1		T140	21
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	4		T6	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T30	1		T47	3		T70	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T12	1		T219	1		T32	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T3	7		T8	1		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	4		T143	1		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T69	1		T31	5		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	5		T28	1		T70	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T11	13		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T8	1		T202	1		T136	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T71	1		T143	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	6		T137	1		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T11	16		T29	11		T136	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T197	1		T140	6		T142	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1784	1			T1	1		T2	3		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T70	15		T72	5		T181	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T148	7		T284	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T223	21		T275	6		T320	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T299	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T28	4		T150	15		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T29	12		T28	12		T234	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T160	9		T280	5		T173	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T144	5		T155	9		T242	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	2		T47	6		T70	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	7		T32	3		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T3	1		T28	16		T153	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T11	4		T143	4		T153	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T31	1		T155	1		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T6	10		T28	4		T70	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T5	1		T11	13		T71	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T136	10		T144	11		T139	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T71	5		T143	13		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T4	3		T177	10		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	15		T29	11		T136	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T197	12		T26	4		T158	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T1	6		T30	2		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T70	14		T72	5		T181	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T28	6		T108	1		T140	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T29	13		T108	1		T234	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T30	2		T47	7		T70	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	2		T6	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T30	3		T152	1		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	8		T219	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	7		T8	1		T28	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	5		T143	11		T31	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T11	14		T69	2		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	11		T8	1		T28	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	2		T71	10		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T4	8		T202	1		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1214	1			T1	7		T2	3		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	1		T197	13		T177	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T136	6		T177	3		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T70	15		T140	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	3		T37	4		T170	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T72	6		T181	4		T144	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T148	8		T18	3		T319	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T178	1		T230	2		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T28	13		T244	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T28	2		T140	20		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T29	11		T234	5		T232	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	2		T70	8		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	2		T144	1		T155	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T33	1		T156	11		T142	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T32	3		T169	4		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T3	1		T28	12		T31	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T11	3		T31	5		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	12		T192	4		T231	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	4		T70	8		T136	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T71	11		T32	2		T140	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T4	1		T234	2		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T11	15		T29	10		T38	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T142	3		T239	5		T233	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T136	17		T198	16		T85	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T70	14		T140	5		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T37	4		T157	12		T160	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T72	4		T181	3		T144	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T319	13		T215	8		T321	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T230	3		T16	1		T254	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T28	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T148	8		T317	1		T284	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T282	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T223	22		T275	7		T318	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T28	6		T108	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T29	13		T28	13		T234	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T30	2		T73	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	2		T6	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	3		T47	7		T70	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	8		T219	1		T32	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	7		T8	1		T28	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T11	5		T143	5		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T69	1		T31	3		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T6	11		T28	5		T70	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	2		T11	14		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T202	1		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T71	6		T143	14		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T4	8		T137	1		T177	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	16		T29	12		T136	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T197	13		T140	1		T142	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T1	7		T2	3		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	360	1			T70	15		T72	6		T181	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T284	6		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T223	11		T275	6		T318	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T299	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T28	2		T169	16		T150	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	11		T28	10		T234	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T140	20		T142	11		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	2		T144	1		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	2		T70	8		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T32	3		T155	12		T156	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T3	1		T28	12		T141	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T11	3		T171	10		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T31	3		T34	4		T231	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	4		T70	8		T31	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T11	12		T71	11		T192	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T136	11		T144	12		T239	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T223	16		T233	11		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	1		T234	2		T198	24
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	15		T29	10		T136	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T140	5		T142	3		T236	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T37	4		T38	32		T39	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T70	14		T72	4		T181	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4