Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22440

1

T1

7

T2

3

T3

42

auto[ADC_CTRL_FILTER_COND_OUT]

3454

1

T3

4

T8

1

T11

26

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19887

1

T3

38

T4

249

T6

118

auto[1]

6007

1

T1

7

T2

3

T3

8

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	31	1			T322	3		T282	13		T320	14
values[0]	49	1			T155	19		T287	6		T303	11
values[1]	920	1			T29	46		T30	3		T69	1
values[2]	3007	1			T1	7		T2	3		T8	1
values[3]	488	1			T11	8		T28	30		T71	6
values[4]	584	1			T3	8		T4	9		T30	2
values[5]	654	1			T8	1		T28	8		T69	1
values[6]	537	1			T5	2		T12	8		T28	23
values[7]	826	1			T8	1		T11	31		T219	1
values[8]	604	1			T108	1		T73	1		T152	2
values[9]	1139	1			T3	4		T6	16		T28	5
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1141	1			T8	1		T29	46		T30	3
values[1]	3005	1			T1	7		T2	3		T9	3
values[2]	474	1			T4	9		T28	30		T71	6
values[3]	630	1			T3	8		T30	2		T47	9
values[4]	629	1			T5	2		T8	1		T12	8
values[5]	489	1			T28	23		T30	3		T152	1
values[6]	880	1			T8	1		T11	31		T219	1
values[7]	568	1			T6	15		T28	5		T108	1
values[8]	795	1			T3	4		T108	2		T37	8
values[9]	214	1			T6	1		T32	12		T14	21
minimum	17069	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T8	1		T69	1		T153	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	387	1			T29	23		T30	1		T70	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1703	1			T1	1		T2	3		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	13		T70	9		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T4	6		T72	5		T192	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	14		T71	1		T220	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	7		T47	3		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	2		T202	1		T236	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T12	1		T28	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T8	1		T69	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T30	1		T137	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T28	11		T152	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T8	1		T11	16		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T219	1		T144	13		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T6	5		T28	1		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T177	1		T146	1		T232	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T70	9		T181	4		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	4		T108	2		T37	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T6	1		T32	9		T14	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T233	7		T227	1		T281	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T179	1		T208	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T153	13		T139	13		T177	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T29	23		T30	2		T70	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	936	1			T1	6		T11	4		T114	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	13		T70	8		T143	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T4	3		T72	5		T192	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T28	16		T71	5		T220	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T3	1		T47	6		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T264	15		T226	8		T97	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T5	1		T12	7		T28	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T157	12		T27	18		T289	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T30	2		T138	1		T234	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T28	12		T156	10		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	15		T153	10		T177	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T144	11		T197	12		T155	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T6	10		T28	4		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T177	11		T232	12		T159	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T70	8		T181	3		T143	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T37	3		T136	15		T34	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T32	3		T14	8		T322	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T227	1		T281	6		T16	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T208	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T322	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T282	13		T320	1		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T287	3		T303	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T155	10		T208	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T69	1		T139	1		T177	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T29	23		T30	1		T70	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1677	1			T1	1		T2	3		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T11	13		T70	9		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T11	4		T72	5		T140	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	14		T71	1		T220	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T3	7		T4	6		T47	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T30	2		T264	1		T324	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T28	4		T71	12		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T8	1		T69	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T5	1		T12	1		T30	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	11		T140	21		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T8	1		T11	16		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T219	1		T144	13		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T108	1		T73	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	1		T197	1		T177	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T6	6		T28	1		T70	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T3	4		T108	2		T37	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T322	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T320	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T287	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T155	9		T208	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T139	13		T177	2		T239	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T29	23		T30	2		T70	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T1	6		T114	11		T75	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	13		T70	8		T143	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T11	4		T72	5		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T28	16		T71	5		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	1		T4	3		T47	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T264	15		T97	13		T325	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	4		T71	9		T232	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T157	12		T289	8		T174	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T5	1		T12	7		T30	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T28	12		T156	10		T224	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T11	15		T153	10		T177	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T144	11		T155	12		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T221	13		T245	12		T99	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T197	12		T177	11		T170	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T6	10		T28	4		T70	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T37	3		T136	15		T34	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T8	1		T69	1		T153	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	442	1			T29	25		T30	3		T70	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T1	7		T2	3		T9	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	14		T70	9		T143	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	8		T72	6		T192	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T28	18		T71	6		T220	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	7		T47	7		T143	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	2		T202	1		T236	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T5	2		T12	8		T28	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T8	1		T69	1		T192	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T30	3		T137	1		T138	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T28	13		T152	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T8	1		T11	16		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T219	1		T144	12		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T6	11		T28	5		T108	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T177	12		T146	1		T232	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T70	9		T181	4		T143	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T3	2		T108	2		T37	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T6	1		T32	9		T14	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T233	1		T227	2		T281	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T179	1		T208	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T239	5		T171	23		T301	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	321	1			T29	21		T70	14		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T11	3		T38	32		T39	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	12		T70	8		T31	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	1		T72	4		T192	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T28	12		T145	7		T231	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	1		T47	2		T32	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T236	13		T226	10		T97	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T28	2		T71	11		T156	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T140	20		T234	2		T157	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T234	5		T233	11		T225	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T28	10		T156	11		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T11	15		T149	14		T242	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T144	12		T155	12		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T6	4		T144	10		T146	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T232	14		T253	7		T238	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T70	8		T181	3		T144	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	2		T37	4		T136	28
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T32	3		T14	11		T237	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T233	6		T281	4		T262	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T208	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T322	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T282	1		T320	14		T323	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T287	5		T303	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T155	10		T208	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T69	1		T139	14		T177	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	356	1			T29	25		T30	3		T70	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T1	7		T2	3		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T11	14		T70	9		T143	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	5		T72	6		T140	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T28	18		T71	6		T220	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	7		T4	8		T47	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	2		T264	16		T324	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T28	6		T71	10		T182	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	1		T69	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	2		T12	8		T30	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	13		T140	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T8	1		T11	16		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T219	1		T144	12		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T108	1		T73	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T152	1		T197	13		T177	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T6	12		T28	5		T70	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T3	2		T108	2		T37	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T282	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T287	1		T303	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T155	9		T208	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T239	5		T171	10		T301	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T29	21		T70	14		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T38	32		T39	21		T270	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	12		T70	8		T31	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	3		T72	4		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	12		T145	7		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	1		T4	1		T47	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T324	12		T97	11		T273	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T28	2		T71	11		T232	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T234	2		T157	12		T236	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T156	7		T230	3		T225	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T28	10		T140	20		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	15		T234	5		T149	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T144	12		T155	12		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T171	15		T221	11		T245	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T253	7		T238	15		T245	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	4		T70	8		T181	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	2		T37	4		T136	28

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4