Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22611

1

T1

7

T2

3

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3283

1

T3

8

T8

3

T11

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20034

1

T3

46

T4

240

T6

133

auto[1]

5860

1

T1

7

T2

3

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	327	1			T5	2		T11	26		T145	8
values[0]	19	1			T34	9		T240	10		-	-
values[1]	887	1			T8	1		T29	22		T28	23
values[2]	463	1			T219	1		T202	1		T220	3
values[3]	432	1			T8	1		T11	8		T28	8
values[4]	623	1			T3	8		T69	1		T71	21
values[5]	3022	1			T1	7		T2	3		T8	1
values[6]	859	1			T4	9		T30	3		T108	1
values[7]	751	1			T11	31		T12	8		T29	24
values[8]	479	1			T28	5		T30	3		T37	8
values[9]	977	1			T3	4		T6	16		T28	30
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	586	1			T28	23		T30	2		T108	1
values[1]	491	1			T8	1		T28	8		T219	1
values[2]	493	1			T11	8		T47	9		T182	1
values[3]	2956	1			T1	7		T2	3		T3	8
values[4]	712	1			T8	1		T136	22		T181	7
values[5]	796	1			T4	9		T30	3		T108	1
values[6]	707	1			T11	31		T12	8		T29	24
values[7]	545	1			T30	3		T37	8		T70	17
values[8]	996	1			T3	4		T5	2		T6	15
values[9]	155	1			T6	1		T11	26		T177	12
minimum	17457	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T30	2		T73	1		T144	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	11		T108	1		T146	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T219	1		T220	1		T31	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T8	1		T28	4		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	4		T182	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T47	3		T153	1		T170	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1698	1			T1	1		T2	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	7		T69	1		T71	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T181	4		T143	1		T142	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T136	12		T32	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T4	6		T70	15		T72	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T30	1		T108	1		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T12	1		T192	5		T268	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	16		T29	12		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T37	5		T143	1		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T30	1		T70	9		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T3	4		T5	1		T6	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T108	1		T69	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T6	1		T11	13		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T177	1		T142	4		T159	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17034	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T8	1		T182	1		T140	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T144	11		T138	1		T234	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	12		T146	16		T230	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T220	2		T31	4		T177	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T28	4		T239	6		T232	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	4		T139	13		T172	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	6		T153	13		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	906	1			T1	6		T114	11		T75	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	1		T71	9		T31	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T181	3		T143	13		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	10		T32	3		T197	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	3		T70	14		T72	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	2		T243	15		T231	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	7		T192	2		T264	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	15		T29	12		T28	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T37	3		T143	5		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T30	2		T70	8		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T5	1		T6	10		T28	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T155	12		T141	6		T232	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T11	13		T170	12		T222	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T177	11		T159	10		T241	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T29	11		T28	3		T24	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T280	5		T278	13		T273	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T5	1		T11	13		T169	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T145	8		T155	13		T141	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T34	7		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T240	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T29	11		T30	2		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T8	1		T28	11		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T219	1		T220	1		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T202	1		T239	6		T232	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	4		T308	1		T160	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T8	1		T28	4		T47	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T143	1		T182	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	7		T69	1		T71	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1750	1			T1	1		T2	3		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T8	1		T136	12		T32	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T4	6		T70	15		T72	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T30	1		T108	1		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T12	1		T192	5		T156	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	16		T29	12		T150	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T37	5		T143	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T28	1		T30	1		T70	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	311	1			T3	4		T6	6		T28	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T108	1		T69	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T5	1		T11	13		T227	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T155	12		T141	6		T150	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T34	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T240	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	11		T144	16		T234	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	12		T146	16		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T220	2		T31	4		T138	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T239	6		T232	5		T230	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	4		T160	18		T248	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T28	4		T47	6		T153	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T143	4		T139	13		T155	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T3	1		T71	9		T31	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T1	6		T114	11		T75	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T136	10		T32	3		T197	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	3		T70	14		T72	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T30	2		T243	15		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	7		T192	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	15		T29	12		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T37	3		T143	5		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T28	4		T30	2		T70	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T6	10		T28	16		T70	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T153	11		T177	11		T232	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T30	2		T73	1		T144	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	13		T108	1		T146	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T219	1		T220	3		T31	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T8	1		T28	6		T202	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	5		T182	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T47	7		T153	14		T170	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T1	7		T2	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	7		T69	1		T71	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T181	4		T143	14		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T8	1		T136	11		T32	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T4	8		T70	15		T72	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	3		T108	1		T243	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	8		T192	3		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	16		T29	13		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T37	4		T143	6		T140	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T30	3		T70	9		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T3	2		T5	2		T6	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T108	1		T69	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T6	1		T11	14		T170	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T177	12		T142	1		T159	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17189	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T8	1		T182	1		T140	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	12		T140	20		T234	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T28	10		T146	7		T230	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T31	5		T223	16		T160	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T28	2		T239	5		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	3		T248	1		T88	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T47	2		T35	1		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T38	32		T39	21		T270	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	1		T71	11		T31	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T181	3		T142	9		T171	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T136	11		T32	3		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T4	1		T70	14		T72	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T231	20		T301	11		T160	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T192	4		T268	10		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	15		T29	11		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T37	4		T140	6		T149	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T70	8		T225	1		T226	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T3	2		T6	4		T28	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	7		T155	12		T141	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T11	12		T227	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T142	3		T241	12		T326	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	10		T144	1		T34	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T140	5		T280	8		T278	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T5	2		T11	14		T169	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T145	1		T155	13		T141	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T34	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T240	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T29	12		T30	2		T73	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T8	1		T28	13		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T219	1		T220	3		T31	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T202	1		T239	7		T232	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	5		T308	1		T160	20
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T28	6		T47	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T143	5		T182	1		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	7		T69	1		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	7		T2	3		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T8	1		T136	11		T32	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	8		T70	15		T72	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T30	3		T108	1		T243	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	8		T192	3		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	16		T29	13		T150	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	4		T143	6		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T28	5		T30	3		T70	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T3	2		T6	12		T28	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T108	1		T69	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T11	12		T169	4		T253	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T145	7		T155	12		T141	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T34	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T29	10		T144	13		T140	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T28	10		T140	5		T146	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T31	5		T223	16		T265	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T239	5		T232	11		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	3		T160	19		T248	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T28	2		T47	2		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T155	9		T142	11		T221	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T71	11		T31	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1406	1			T38	32		T39	21		T270	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T136	11		T32	3		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	1		T70	14		T72	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T231	9		T160	5		T310	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T192	4		T156	7		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	15		T29	11		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T37	4		T149	14		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T70	8		T226	10		T248	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T3	2		T6	4		T28	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T232	14		T223	11		T225	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4