Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22571

1

T1

7

T2

3

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3323

1

T3

8

T8

2

T11

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20104

1

T3

46

T4

240

T6

133

auto[1]

5790

1

T1

7

T2

3

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	52	1			T253	8		T174	25		T89	16
values[0]	69	1			T73	1		T34	9		T278	26
values[1]	840	1			T8	1		T29	22		T28	23
values[2]	460	1			T219	1		T202	1		T220	3
values[3]	395	1			T8	1		T11	8		T28	8
values[4]	617	1			T3	8		T69	1		T71	21
values[5]	3103	1			T1	7		T2	3		T8	1
values[6]	856	1			T4	9		T30	3		T108	1
values[7]	705	1			T11	31		T12	8		T29	24
values[8]	496	1			T28	5		T70	17		T143	6
values[9]	1246	1			T3	4		T5	2		T6	16
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	977	1			T8	1		T29	22		T28	23
values[1]	449	1			T8	1		T28	8		T202	1
values[2]	524	1			T11	8		T219	1		T47	9
values[3]	3019	1			T1	7		T2	3		T3	8
values[4]	674	1			T8	1		T70	29		T136	22
values[5]	780	1			T4	9		T30	3		T108	1
values[6]	710	1			T11	31		T12	8		T29	24
values[7]	516	1			T30	3		T37	8		T70	17
values[8]	897	1			T3	4		T5	2		T6	15
values[9]	272	1			T6	1		T11	26		T28	30
minimum	17076	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T29	11		T73	1		T144	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T8	1		T28	11		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T8	1		T28	4		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T202	1		T239	6		T232	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	4		T219	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T47	3		T69	1		T153	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1763	1			T1	1		T2	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	7		T71	12		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T70	15		T181	4		T142	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	1		T136	12		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	6		T30	1		T72	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T108	1		T144	11		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	1		T192	5		T268	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	16		T29	12		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T37	5		T143	1		T140	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T30	1		T70	9		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	309	1			T3	4		T5	1		T6	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T108	1		T69	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T6	1		T11	13		T28	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T177	1		T142	4		T223	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16913	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T327	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	11		T144	16		T138	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T28	12		T146	16		T230	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T28	4		T220	2		T31	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T239	6		T232	5		T80	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	4		T139	13		T257	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T47	6		T153	13		T170	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T1	6		T114	11		T75	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	1		T71	9		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T70	14		T181	3		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T136	10		T143	13		T32	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T4	3		T30	2		T72	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T144	8		T243	15		T231	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T12	7		T192	2		T225	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	15		T29	12		T28	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T37	3		T143	5		T140	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	2		T70	8		T153	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T5	1		T6	10		T70	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T141	6		T232	12		T242	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T11	13		T28	16		T170	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T177	11		T223	21		T159	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T327	5		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T253	8		T174	5		T328	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T89	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T73	1		T34	7		T329	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T278	13		T240	1		T305	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T29	11		T144	15		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T8	1		T28	11		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T219	1		T220	1		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T202	1		T239	6		T232	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	1		T11	4		T28	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T47	3		T153	1		T170	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T143	1		T31	5		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	7		T69	1		T71	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1762	1			T1	1		T2	3		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T8	1		T136	12		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T4	6		T30	1		T70	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T108	1		T144	11		T243	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T192	5		T156	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	16		T29	12		T30	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T143	1		T146	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	1		T70	9		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	372	1			T3	4		T5	1		T6	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T108	1		T69	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T174	20		T328	2		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T89	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T34	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T278	13		T240	9		T327	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T29	11		T144	16		T234	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T28	12		T146	16		T216	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T220	2		T31	4		T138	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T239	6		T232	5		T230	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T11	4		T28	4		T160	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T47	6		T153	13		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T143	4		T31	1		T139	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T3	1		T71	9		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	896	1			T1	6		T114	11		T75	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T136	10		T143	13		T32	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T4	3		T30	2		T70	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	8		T243	15		T231	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T12	7		T192	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	15		T29	12		T30	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T143	5		T148	7		T149	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T28	4		T70	8		T225	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T5	1		T6	10		T11	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T153	11		T177	11		T141	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T29	12		T73	1		T144	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T8	1		T28	13		T30	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T8	1		T28	6		T220	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T202	1		T239	7		T232	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	5		T219	1		T182	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T47	7		T69	1		T153	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T1	7		T2	3		T9	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T3	7		T71	10		T32	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T70	15		T181	4		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	1		T136	11		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T4	8		T30	3		T72	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T108	1		T144	9		T243	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	8		T192	3		T268	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T11	16		T29	13		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T37	4		T143	6		T140	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T30	3		T70	9		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	2		T5	2		T6	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T108	1		T69	1		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T6	1		T11	14		T28	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T177	12		T142	1		T223	22
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T327	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T29	10		T144	13		T140	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T28	10		T140	5		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T28	2		T31	5		T223	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T239	5		T232	11		T80	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T11	3		T248	1		T88	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T47	2		T35	1		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1410	1			T38	32		T39	21		T270	25
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	1		T71	11		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T70	14		T181	3		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T136	11		T32	3		T233	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T4	1		T72	4		T136	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T144	10		T231	20		T301	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T192	4		T268	10		T225	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	15		T29	11		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T37	4		T140	6		T236	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T70	8		T225	1		T226	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T3	2		T6	4		T70	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T145	7		T141	4		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T11	12		T28	12		T227	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T142	3		T223	11		T249	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T327	5		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T253	1		T174	21		T328	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T89	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T73	1		T34	5		T329	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T278	14		T240	10		T305	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T29	12		T144	18		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T8	1		T28	13		T30	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T219	1		T220	3		T31	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T202	1		T239	7		T232	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T11	5		T28	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T47	7		T153	14		T170	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T143	5		T31	3		T182	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	7		T69	1		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1239	1			T1	7		T2	3		T9	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T8	1		T136	11		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	8		T30	3		T70	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T108	1		T144	9		T243	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	8		T192	3		T156	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	16		T29	13		T30	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T143	6		T146	1		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T28	5		T70	9		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T3	2		T5	2		T6	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T108	1		T69	1		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T253	7		T174	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T89	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T34	4		T329	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T278	12		T305	7		T327	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T29	10		T144	13		T140	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T28	10		T140	5		T146	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T31	5		T223	16		T265	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T239	5		T232	11		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T11	3		T28	2		T160	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T47	2		T35	1		T14	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T31	3		T155	9		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	1		T71	11		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1419	1			T38	32		T39	21		T270	25
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T136	11		T32	3		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T4	1		T70	14		T72	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	10		T231	9		T198	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T192	4		T156	7		T268	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	15		T29	11		T150	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T149	14		T236	13		T161	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T70	8		T225	1		T226	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	2		T6	4		T11	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T145	7		T141	4		T142	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4