Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22389

1

T1

7

T2

3

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3505

1

T3

8

T6

15

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19962

1

T3

34

T4

240

T5

2

auto[1]

5932

1

T1

7

T2

3

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	232	1			T8	1		T37	8		T153	11
values[0]	83	1			T28	23		T143	14		T239	12
values[1]	626	1			T29	24		T70	46		T152	1
values[2]	776	1			T11	8		T30	3		T219	1
values[3]	578	1			T3	8		T11	26		T28	30
values[4]	687	1			T71	21		T73	1		T143	6
values[5]	588	1			T4	9		T8	1		T28	5
values[6]	566	1			T5	2		T6	1		T29	22
values[7]	712	1			T3	4		T12	8		T69	1
values[8]	2811	1			T1	7		T2	3		T9	3
values[9]	1180	1			T6	15		T8	1		T11	31
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	568	1			T29	24		T70	17		T152	1
values[1]	724	1			T11	34		T30	3		T108	1
values[2]	602	1			T3	8		T28	30		T202	1
values[3]	756	1			T4	9		T30	3		T71	21
values[4]	544	1			T8	1		T28	5		T30	2
values[5]	663	1			T5	2		T6	1		T29	22
values[6]	2898	1			T1	7		T2	3		T3	4
values[7]	606	1			T69	1		T182	2		T155	2
values[8]	1063	1			T6	15		T8	2		T11	31
values[9]	115	1			T253	8		T226	29		T269	8
minimum	17355	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T29	12		T152	1		T177	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T70	9		T137	1		T169	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	4		T30	1		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	13		T219	1		T72	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T143	1		T145	8		T142	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	7		T28	14		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T4	6		T30	1		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T71	12		T152	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T31	5		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T28	1		T30	2		T144	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	1		T6	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T29	11		T108	1		T70	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1653	1			T1	1		T2	3		T3	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T71	1		T137	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T182	1		T155	1		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T69	1		T182	1		T34	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	1		T11	16		T28	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T6	5		T8	1		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T226	14		T256	16		T258	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T253	8		T269	8		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16984	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T28	11		T155	13		T244	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T29	12		T177	2		T239	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T70	8		T264	15		T248	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T11	4		T30	2		T220	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	13		T72	5		T136	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T143	5		T148	7		T158	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	1		T28	16		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T4	3		T30	2		T265	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T71	9		T13	3		T14	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T31	1		T149	12		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	4		T144	8		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T136	10		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T29	11		T70	8		T192	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T1	6		T12	7		T114	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T71	5		T33	1		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T155	1		T157	12		T158	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T34	2		T222	13		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	15		T28	4		T37	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	10		T47	6		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T226	15		T258	3		T330	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T259	8		T329	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T28	3		T70	14		T143	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T28	12		T155	12		T244	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	79	1			T37	5		T141	5		T247	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T8	1		T153	1		T159	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T143	1		T239	6		T263	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T28	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	12		T70	15		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T70	9		T137	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	4		T30	1		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T219	1		T72	5		T136	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T108	1		T145	8		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	7		T11	13		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T73	1		T143	1		T140	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T71	12		T144	2		T146	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T4	6		T8	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	1		T30	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T5	1		T6	1		T31	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T29	11		T108	1		T70	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	4		T12	1		T69	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T71	1		T192	5		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T1	1		T2	3		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T69	1		T182	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T8	1		T11	16		T28	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	391	1			T6	5		T47	3		T31	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T37	3		T141	6		T247	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T153	10		T159	10		T331	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T143	13		T239	6		T263	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T28	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	12		T70	14		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T70	8		T155	12		T264	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	4		T30	2		T220	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T72	5		T136	5		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T148	7		T14	1		T221	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T11	13		T28	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T143	5		T265	10		T160	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T71	9		T144	5		T146	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	3		T30	2		T149	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	4		T32	5		T170	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	1		T31	1		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T29	11		T70	8		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T12	7		T136	10		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T71	5		T192	2		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	872	1			T1	6		T114	11		T75	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T150	11		T238	13		T257	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	15		T28	4		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T6	10		T47	6		T31	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T29	13		T152	1		T177	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T70	9		T137	1		T169	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	5		T30	3		T108	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	14		T219	1		T72	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T143	6		T145	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	7		T28	18		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	8		T30	3		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T71	10		T152	1		T13	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T8	1		T31	3		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	5		T30	2		T144	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	2		T6	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T29	12		T108	1		T70	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T1	7		T2	3		T3	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T71	6		T137	1		T33	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T182	1		T155	2		T157	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T69	1		T182	1		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T8	1		T11	16		T28	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T6	11		T8	1		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T226	16		T256	1		T258	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T253	1		T269	1		T217	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17152	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T28	13		T155	13		T244	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	11		T239	5		T225	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T70	8		T169	4		T171	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	3		T233	11		T266	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	12		T72	4		T136	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T145	7		T142	11		T158	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	1		T28	12		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T4	1		T140	5		T265	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T71	11		T13	3		T14	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T31	3		T169	16		T149	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T144	10		T32	5		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T136	11		T224	14		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T29	10		T70	8		T192	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1306	1			T3	2		T38	32		T39	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T33	1		T150	13		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T157	12		T268	30		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T34	4		T171	10		T222	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T11	15		T28	2		T37	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	4		T47	2		T31	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T226	13		T256	15		T258	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T253	7		T269	7		T259	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T70	14		T232	11		T89	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T28	10		T155	12		T244	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T37	4		T141	7		T247	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T8	1		T153	11		T159	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T143	14		T239	7		T263	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T28	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T29	13		T70	15		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T70	9		T137	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T11	5		T30	3		T220	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T219	1		T72	6		T136	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T108	1		T145	1		T148	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	7		T11	14		T28	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T73	1		T143	6		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T71	10		T144	6		T146	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	8		T8	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	5		T30	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	2		T6	1		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T29	12		T108	1		T70	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T3	2		T12	8		T69	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T71	6		T192	3		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1196	1			T1	7		T2	3		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T69	1		T182	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T8	1		T11	16		T28	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	351	1			T6	11		T47	7		T31	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T37	4		T141	4		T245	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T253	7		T87	8		T332	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T239	5		T263	10		T292	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T28	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T29	11		T70	14		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	8		T155	12		T171	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T11	3		T226	11		T266	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T72	4		T136	17		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T145	7		T233	11		T221	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T11	12		T28	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T140	5		T142	11		T265	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T71	11		T144	1		T146	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	1		T149	14		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T32	5		T232	14		T230	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T31	3		T169	16		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T29	10		T70	8		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T3	2		T136	11		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T192	4		T33	1		T234	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T38	32		T39	21		T270	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T171	10		T150	13		T238	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T11	15		T28	2		T140	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T6	4		T47	2		T31	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4