Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T143	6		T144	9		T33	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	14		T73	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T70	9		T145	1		T140	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	18		T178	1		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T108	1		T143	14		T146	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T12	8		T30	3		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T1	7		T2	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T153	11		T197	13		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	1		T30	3		T202	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T28	5		T108	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T29	12		T30	2		T37	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T11	16		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T28	6		T71	6		T31	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T3	2		T192	3		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T142	1		T157	13		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T4	8		T8	1		T11	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	7		T29	13		T47	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T6	11		T219	1		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T5	2		T136	6		T143	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T137	1		T243	16		T26	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	10		T33	1		T242	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	12		T142	9		T239	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T70	8		T145	7		T140	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T28	12		T34	4		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T146	7		T169	16		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T144	12		T223	16		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1354	1			T28	10		T38	32		T39	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T140	20		T142	11		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T155	12		T234	2		T169	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T71	11		T244	9		T87	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T29	10		T37	4		T70	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	15		T144	1		T32	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T28	2		T31	5		T198	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	2		T192	4		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T142	3		T157	12		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T4	1		T11	3		T70	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	1		T29	11		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T6	4		T31	3		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T136	17		T226	10		T248	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T26	10		T249	1		T250	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T241	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T240	16		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T242	13		T176	10		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T150	16		T13	7		T16	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T143	6		T144	9		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T11	14		T73	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T70	9		T140	5		T177	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	18		T178	1		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T108	1		T220	3		T143	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T12	8		T30	3		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T8	1		T28	13		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T192	1		T153	11		T197	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T1	7		T2	3		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T108	1		T69	1		T71	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T30	2		T70	15		T72	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T8	1		T11	16		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	4		T71	6		T153	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	2		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	6		T31	6		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T4	8		T8	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	377	1			T3	7		T5	2		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T6	11		T11	5		T219	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T241	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T242	10		T251	18		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T150	2		T13	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T144	10		T33	1		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T11	12		T142	9		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T70	8		T140	6		T233	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T28	12		T236	13		T158	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T145	7		T146	7		T141	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	12		T34	4		T232	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T28	10		T156	7		T224	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T140	20		T142	11		T231	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1327	1			T29	10		T38	32		T39	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T71	11		T87	5		T252	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T70	14		T72	4		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	15		T144	1		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T37	4		T253	7		T88	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T3	2		T192	4		T232	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T28	2		T31	5		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	1		T155	9		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T3	1		T29	11		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T6	4		T11	3		T70	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4