Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22462

1

T1

7

T2

3

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3432

1

T3

8

T6

15

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19973

1

T3

34

T4

240

T5

2

auto[1]

5921

1

T1

7

T2

3

T3

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	65	1			T254	17		T217	1		T255	21
values[0]	123	1			T28	23		T143	14		T239	12
values[1]	606	1			T29	24		T70	46		T152	1
values[2]	738	1			T11	34		T30	3		T72	10
values[3]	601	1			T3	8		T28	30		T108	1
values[4]	698	1			T71	21		T73	1		T143	6
values[5]	617	1			T4	9		T8	1		T28	5
values[6]	512	1			T5	2		T6	1		T29	22
values[7]	674	1			T3	4		T12	8		T69	1
values[8]	2875	1			T1	7		T2	3		T9	3
values[9]	1330	1			T6	15		T8	2		T11	31
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	911	1			T29	24		T28	23		T70	46
values[1]	640	1			T11	8		T30	3		T108	1
values[2]	668	1			T3	8		T11	26		T28	30
values[3]	702	1			T4	9		T30	3		T71	21
values[4]	516	1			T8	1		T28	5		T30	2
values[5]	730	1			T5	2		T6	1		T69	1
values[6]	2878	1			T1	7		T2	3		T3	4
values[7]	571	1			T69	1		T182	2		T138	2
values[8]	1070	1			T6	15		T8	2		T11	31
values[9]	152	1			T153	11		T231	24		T253	8
minimum	17056	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T29	12		T70	15		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T28	11		T70	9		T144	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	1		T108	1		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T11	4		T219	1		T72	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T220	1		T145	8		T142	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	7		T11	13		T28	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	6		T30	1		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T71	12		T152	1		T146	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	1		T31	5		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T28	1		T30	2		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T5	1		T6	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T70	9		T192	5		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1635	1			T1	1		T2	3		T3	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T29	11		T71	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T182	1		T138	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T69	1		T182	1		T34	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T8	1		T11	16		T28	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T6	5		T8	1		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T231	12		T226	14		T256	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T153	1		T253	8		T16	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16913	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T29	12		T70	14		T143	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T28	12		T70	8		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	2		T243	15		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	4		T72	5		T136	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T220	2		T148	7		T221	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	1		T11	13		T28	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T4	3		T30	2		T143	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T71	9		T146	16		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T31	1		T35	1		T198	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T28	4		T144	8		T32	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T5	1		T136	10		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T70	8		T192	2		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	921	1			T1	6		T12	7		T114	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T29	11		T71	5		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T138	1		T155	1		T157	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T34	2		T222	13		T257	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	15		T28	4		T37	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	10		T47	6		T31	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T231	12		T226	15		T258	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T153	10		T16	1		T259	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T254	9		T21	3		T260	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T217	1		T255	12		T261	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T143	1		T239	6		T91	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T28	11		T262	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T29	12		T70	15		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T70	9		T137	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T30	1		T220	1		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	17		T72	5		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T108	1		T145	8		T140	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	7		T28	14		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T73	1		T143	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T71	12		T144	2		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	6		T8	1		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	1		T30	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T6	1		T31	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T29	11		T108	1		T70	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	4		T12	1		T69	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T71	1		T192	5		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1632	1			T1	1		T2	3		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T69	1		T182	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	355	1			T8	1		T11	16		T28	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	389	1			T6	5		T8	1		T47	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T254	8		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T255	9		T261	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T143	13		T239	6		T263	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T28	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T29	12		T70	14		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T70	8		T155	12		T264	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T30	2		T220	2		T153	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	17		T72	5		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T148	7		T14	1		T158	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	1		T28	16		T136	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T143	5		T265	10		T221	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T71	9		T144	5		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	3		T30	2		T149	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T28	4		T32	3		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T5	1		T31	1		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T29	11		T70	8		T144	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	7		T136	10		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T71	5		T192	2		T33	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	884	1			T1	6		T114	11		T75	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T150	11		T160	11		T238	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T11	15		T28	4		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T6	10		T47	6		T31	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T29	13		T70	15		T143	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	13		T70	9		T144	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	3		T108	1		T192	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	5		T219	1		T72	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T220	3		T145	1		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T3	7		T11	14		T28	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	8		T30	3		T73	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T71	10		T152	1		T146	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T8	1		T31	3		T148	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T28	5		T30	2		T108	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T5	2		T6	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T70	9		T192	3		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T1	7		T2	3		T3	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T29	12		T71	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T182	1		T138	2		T155	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T69	1		T182	1		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T8	1		T11	16		T28	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T6	11		T8	1		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T231	13		T226	16		T256	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T153	11		T253	1		T16	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17056	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T29	11		T70	14		T239	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T28	10		T70	8		T144	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T266	10		T80	6		T267	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	3		T72	4		T136	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T145	7		T142	11		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T11	12		T28	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T4	1		T140	5		T149	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T71	11		T146	7		T13	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T31	3		T35	1		T198	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	10		T32	5		T156	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T136	11		T169	16		T224	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T70	8		T192	4		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T3	2		T38	32		T39	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T29	10		T150	13		T160	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T157	12		T268	10		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	4		T171	10		T222	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T11	15		T28	2		T37	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T6	4		T47	2		T31	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T231	11		T226	13		T256	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T253	7		T269	7		T259	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T254	9		T21	2		T260	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T217	1		T255	10		T261	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T143	14		T239	7		T91	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T28	13		T262	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T29	13		T70	15		T152	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T70	9		T137	1		T155	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T30	3		T220	3		T192	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	19		T72	6		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T108	1		T145	1		T140	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T3	7		T28	18		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T73	1		T143	6		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T71	10		T144	6		T32	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	8		T8	1		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T28	5		T30	2		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	2		T6	1		T31	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T29	12		T108	1		T70	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	2		T12	8		T69	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T71	6		T192	3		T33	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T1	7		T2	3		T9	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T69	1		T182	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	346	1			T8	1		T11	16		T28	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	374	1			T6	11		T8	1		T47	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T254	8		T21	1		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T255	11		T261	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T239	5		T91	10		T263	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T28	10		T262	2		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T29	11		T70	14		T232	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T70	8		T155	12		T171	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T226	11		T266	10		T80	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	15		T72	4		T144	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T145	7		T140	5		T233	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	1		T28	12		T136	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T142	11		T265	4		T233	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T71	11		T144	1		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	1		T149	14		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T32	3		T232	14		T230	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T31	3		T169	16		T198	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T29	10		T70	8		T144	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T3	2		T136	11		T181	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T192	4		T33	1		T234	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1305	1			T38	32		T39	21		T270	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T171	10		T150	13		T160	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T11	15		T28	2		T37	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	322	1			T6	4		T47	2		T31	5

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4