Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22432

1

T1

7

T2

3

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

3462

1

T3

12

T4

9

T8

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19898

1

T3

42

T4

249

T6

118

auto[1]

5996

1

T1

7

T2

3

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	11	1			T268	11		-	-		-	-
values[0]	78	1			T182	1		T26	15		T81	14
values[1]	641	1			T8	1		T108	1		T219	1
values[2]	746	1			T69	1		T71	21		T72	10
values[3]	631	1			T11	26		T12	8		T30	2
values[4]	2910	1			T1	7		T2	3		T9	3
values[5]	829	1			T3	8		T5	2		T6	15
values[6]	509	1			T4	9		T8	1		T29	22
values[7]	609	1			T28	5		T37	8		T136	22
values[8]	651	1			T11	8		T28	30		T108	1
values[9]	1224	1			T3	4		T6	1		T8	1
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	888	1			T8	1		T108	1		T219	1
values[1]	679	1			T11	26		T30	2		T72	10
values[2]	644	1			T12	8		T28	8		T69	1
values[3]	2984	1			T1	7		T2	3		T6	15
values[4]	640	1			T3	8		T5	2		T11	31
values[5]	614	1			T4	9		T8	1		T29	22
values[6]	711	1			T28	30		T37	8		T70	29
values[7]	548	1			T8	1		T11	8		T108	1
values[8]	843	1			T3	4		T6	1		T70	17
values[9]	256	1			T152	1		T264	16		T172	3
minimum	17087	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T8	1		T108	1		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T202	1		T152	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T72	5		T181	4		T144	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	13		T30	2		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T12	1		T28	4		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T69	1		T71	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1693	1			T1	1		T2	3		T6	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T29	12		T30	1		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T5	1		T137	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T3	7		T11	16		T28	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T8	1		T143	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T4	6		T29	11		T28	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	5		T144	11		T140	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	14		T70	15		T136	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	4		T47	3		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T8	1		T108	1		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T6	1		T70	9		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	4		T136	18		T31	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T269	15		T271	7		T272	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T152	1		T264	1		T172	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16928	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T250	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T71	9		T197	12		T140	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T153	13		T155	9		T265	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T72	5		T181	3		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	13		T31	4		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	7		T28	4		T242	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T71	5		T148	7		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T1	6		T6	10		T30	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T29	12		T30	2		T170	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T5	1		T146	16		T14	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	1		T11	15		T28	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T143	5		T170	12		T224	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T4	3		T29	11		T28	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	3		T144	8		T230	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	16		T70	14		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	4		T47	6		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T32	2		T34	2		T232	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T70	8		T153	11		T155	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T136	5		T31	1		T33	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T271	12		T272	12		T215	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T264	15		T172	2		T257	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T250	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T268	11		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T182	1		T26	11		T255	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T81	1		T273	1		T274	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	1		T108	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T202	1		T152	1		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T71	12		T72	5		T181	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T69	1		T31	7		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T73	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	13		T30	2		T71	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1696	1			T1	1		T2	3		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T29	12		T30	1		T140	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T5	1		T6	5		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	7		T11	16		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T137	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T4	6		T29	11		T70	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T37	5		T143	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T28	1		T136	12		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	4		T143	1		T144	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T28	14		T108	1		T70	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T6	1		T47	3		T70	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	373	1			T3	4		T8	1		T136	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T26	4		T255	2		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T81	13		T273	1		T274	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T197	12		T140	4		T266	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T153	13		T265	10		T79	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T71	9		T72	5		T181	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T31	4		T144	11		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T12	7		T138	1		T242	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T11	13		T71	5		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T1	6		T28	4		T30	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T29	12		T30	2		T170	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T5	1		T6	10		T143	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	1		T11	15		T28	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T146	16		T170	12		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T4	3		T29	11		T70	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	3		T143	5		T230	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T28	4		T136	10		T156	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	4		T143	13		T144	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	16		T70	14		T192	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T47	6		T70	8		T153	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T136	5		T31	1		T33	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T8	1		T108	1		T219	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T202	1		T152	1		T153	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T72	6		T181	4		T144	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T11	14		T30	2		T31	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T12	8		T28	6		T73	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T69	1		T71	6		T148	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1279	1			T1	7		T2	3		T6	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T29	13		T30	3		T108	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	2		T137	1		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	7		T11	16		T28	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T8	1		T143	6		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T4	8		T29	12		T28	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	4		T144	9		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	18		T70	15		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T11	5		T47	7		T143	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	1		T108	1		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T6	1		T70	9		T153	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	2		T136	6		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T269	1		T271	13		T272	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T152	1		T264	16		T172	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17058	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T250	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T71	11		T140	6		T234	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T155	9		T169	16		T265	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T72	4		T181	3		T144	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	12		T31	5		T144	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T28	2		T242	10		T233	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T171	13		T198	16		T161	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1345	1			T6	4		T38	32		T39	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T29	11		T140	20		T235	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T146	7		T14	11		T245	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	1		T11	15		T28	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T224	14		T223	16		T221	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T4	1		T29	10		T70	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T37	4		T144	10		T140	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T28	12		T70	14		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	3		T47	2		T142	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T32	2		T34	4		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T70	8		T157	12		T232	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	2		T136	17		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T269	14		T271	6		T272	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T85	18		T275	7		T21	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T255	15		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T250	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T268	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T182	1		T26	5		T255	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T81	14		T273	2		T274	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T8	1		T108	1		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T202	1		T152	1		T153	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T71	10		T72	6		T181	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T69	1		T31	6		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T12	8		T73	1		T138	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T11	14		T30	2		T71	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T1	7		T2	3		T9	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T29	13		T30	3		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	2		T6	11		T143	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	7		T11	16		T28	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	1		T137	1		T178	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T4	8		T29	12		T70	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T37	4		T143	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T28	5		T136	11		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T11	5		T143	14		T144	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T28	18		T108	1		T70	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T6	1		T47	7		T70	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T3	2		T8	1		T136	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T268	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T26	10		T255	15		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T276	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T140	6		T253	7		T161	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T169	16		T171	10		T265	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T71	11		T72	4		T181	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T31	5		T144	12		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T242	10		T226	13		T277	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	12		T149	14		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T28	2		T38	32		T39	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T29	11		T140	20		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	4		T13	3		T14	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	1		T11	15		T28	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T146	7		T224	14		T223	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T4	1		T29	10		T70	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T37	4		T140	5		T169	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T136	11		T156	18		T142	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T11	3		T144	10		T142	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T28	12		T70	14		T192	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T47	2		T70	8		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T3	2		T136	17		T31	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4