Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22667

1

T1

7

T2

3

T3

42

auto[ADC_CTRL_FILTER_COND_OUT]

3227

1

T3

4

T4

9

T6

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20207

1

T3

46

T4

240

T5

2

auto[1]

5687

1

T1

7

T2

3

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	181	1			T72	10		T178	1		T157	25
values[0]	46	1			T223	33		T275	13		-	-
values[1]	636	1			T29	24		T28	31		T108	1
values[2]	801	1			T3	4		T6	1		T8	1
values[3]	727	1			T12	8		T30	3		T108	1
values[4]	600	1			T3	8		T8	1		T11	8
values[5]	617	1			T6	15		T69	1		T70	17
values[6]	774	1			T5	2		T8	1		T11	26
values[7]	713	1			T4	9		T29	22		T71	6
values[8]	528	1			T11	31		T70	29		T136	23
values[9]	3216	1			T1	7		T2	3		T9	3
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	469	1			T108	2		T140	21		T234	12
values[1]	989	1			T3	4		T6	1		T8	1
values[2]	612	1			T3	8		T12	8		T30	3
values[3]	632	1			T8	1		T11	8		T28	30
values[4]	636	1			T6	15		T8	1		T11	26
values[5]	739	1			T4	9		T5	2		T28	5
values[6]	2892	1			T1	7		T2	3		T9	3
values[7]	593	1			T70	29		T136	23		T140	6
values[8]	785	1			T30	3		T37	8		T72	10
values[9]	150	1			T181	7		T148	8		T230	5
minimum	17397	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T108	1		T140	21		T234	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T108	1		T232	15		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T30	2		T47	3		T70	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T3	4		T6	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	7		T30	1		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T12	1		T219	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T8	1		T31	5		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	4		T28	14		T143	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	13		T69	1		T70	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T6	5		T8	1		T136	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	1		T69	1		T71	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T4	6		T28	1		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1695	1			T1	1		T2	3		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T137	1		T197	1		T177	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T136	18		T177	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T70	15		T140	6		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T30	1		T37	5		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T72	5		T144	11		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T148	1		T230	4		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T181	4		T97	8		T16	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16982	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T29	12		T28	11		T278	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T234	6		T150	15		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T232	12		T35	1		T242	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T47	6		T70	8		T138	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T144	5		T155	21		T264	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T3	1		T30	2		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T12	7		T32	3		T156	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T31	1		T155	1		T141	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T11	4		T28	16		T143	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	13		T70	8		T153	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T6	10		T136	10		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T71	9		T143	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	3		T28	4		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	860	1			T1	6		T11	15		T29	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T197	12		T177	10		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T136	5		T177	2		T216	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T70	14		T81	13		T99	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T30	2		T37	3		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T72	5		T144	8		T146	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T148	7		T230	1		T159	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T181	3		T97	7		T16	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T28	7		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T29	12		T28	12		T278	13

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T157	13		T159	1		T262	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T72	5		T178	1		T97	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T223	12		T275	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T28	4		T108	1		T234	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T29	12		T28	11		T232	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T30	2		T73	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T3	4		T6	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T30	1		T47	3		T70	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T108	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	7		T8	1		T177	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	4		T28	14		T143	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T69	1		T70	9		T31	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T6	5		T220	1		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	1		T11	13		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T8	1		T28	1		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T29	11		T71	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T4	6		T137	1		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	16		T136	18		T177	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T70	15		T197	1		T140	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1765	1			T1	1		T2	3		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T181	4		T144	11		T146	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T157	12		T159	10		T279	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T72	5		T97	7		T240	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T223	21		T275	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T28	4		T234	6		T150	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T29	12		T28	12		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T138	1		T280	5		T248	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T144	5		T155	9		T242	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T30	2		T47	6		T70	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T12	7		T32	3		T155	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	1		T177	11		T141	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T11	4		T28	16		T143	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T70	8		T31	1		T155	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T6	10		T220	2		T31	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T5	1		T11	13		T71	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T28	4		T136	10		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T29	11		T71	5		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T4	3		T177	10		T170	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T11	15		T136	5		T177	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T70	14		T197	12		T158	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	928	1			T1	6		T30	2		T37	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T181	3		T144	8		T146	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T108	1		T140	1		T234	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T108	1		T232	13		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	345	1			T30	2		T47	7		T70	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	2		T6	1		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	7		T30	3		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	8		T219	1		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T8	1		T31	3		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T11	5		T28	18		T143	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T11	14		T69	1		T70	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	11		T8	1		T136	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T5	2		T69	1		T71	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T4	8		T28	5		T202	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1203	1			T1	7		T2	3		T9	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T137	1		T197	13		T177	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T136	6		T177	3		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T70	15		T140	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	3		T37	4		T170	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T72	6		T144	9		T178	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T148	8		T230	2		T159	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T181	4		T97	8		T16	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17168	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T29	13		T28	13		T278	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T140	20		T234	5		T142	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T232	14		T35	1		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T47	2		T70	8		T145	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	2		T144	1		T155	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	1		T33	1		T142	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T32	3		T156	11		T169	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T31	3		T141	4		T231	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	3		T28	12		T31	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	12		T70	8		T34	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T6	4		T136	11		T144	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T71	11		T192	4		T32	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	1		T140	6		T234	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T11	15		T29	10		T38	32
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T233	6		T26	10		T198	24
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T136	17		T198	16		T85	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T70	14		T140	5		T236	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T37	4		T157	12		T160	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T72	4		T144	10		T146	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T230	3		T215	8		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T181	3		T97	7		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T28	2		T223	11		T281	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T29	11		T28	10		T278	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T157	13		T159	11		T262	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T72	6		T178	1		T97	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T223	22		T275	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T28	6		T108	1		T234	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T29	13		T28	13		T232	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T30	2		T73	1		T138	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T3	2		T6	1		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T30	3		T47	7		T70	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T12	8		T108	1		T219	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	7		T8	1		T177	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	5		T28	18		T143	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T69	1		T70	9		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T6	11		T220	3		T31	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T5	2		T11	14		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T8	1		T28	5		T202	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T29	12		T71	6		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T4	8		T137	1		T177	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T11	16		T136	6		T177	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T70	15		T197	13		T140	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T1	7		T2	3		T9	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T181	4		T144	9		T146	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T157	12		T262	2		T279	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T72	4		T97	7		T282	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T223	11		T275	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T28	2		T234	5		T169	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T29	11		T28	10		T232	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T140	20		T142	11		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	2		T144	1		T155	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T47	2		T70	8		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T32	3		T155	12		T156	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T3	1		T141	4		T142	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T11	3		T28	12		T171	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T70	8		T31	3		T34	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	4		T31	5		T235	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T11	12		T71	11		T192	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T136	11		T144	12		T140	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T29	10		T223	16		T221	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T4	1		T234	2		T233	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	15		T136	17		T142	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T70	14		T140	5		T236	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1416	1			T37	4		T38	32		T39	21
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T181	3		T144	10		T146	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4