Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20454

1

T3

42

T4

249

T5

2

auto[ADC_CTRL_FILTER_COND_OUT]

5440

1

T1

7

T2

3

T3

4

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20011

1

T3

46

T4

240

T5

2

auto[1]

5883

1

T1

7

T2

3

T4

9

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	218	1			T8	2		T69	1		T71	21
values[0]	15	1			T21	1		T283	1		T284	1
values[1]	684	1			T3	8		T30	2		T219	1
values[2]	807	1			T6	1		T70	17		T220	3
values[3]	716	1			T5	2		T11	8		T30	3
values[4]	576	1			T6	15		T11	26		T12	8
values[5]	527	1			T3	4		T28	35		T72	10
values[6]	610	1			T8	1		T108	1		T181	7
values[7]	768	1			T11	31		T108	1		T202	1
values[8]	803	1			T29	22		T28	23		T70	17
values[9]	3115	1			T1	7		T2	3		T4	9
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	780	1			T3	8		T219	1		T70	17
values[1]	3003	1			T1	7		T2	3		T5	2
values[2]	679	1			T11	8		T71	6		T136	23
values[3]	548	1			T6	15		T11	26		T12	8
values[4]	598	1			T3	4		T28	5		T72	10
values[5]	653	1			T8	1		T108	2		T202	1
values[6]	729	1			T11	31		T143	6		T182	2
values[7]	719	1			T29	22		T28	23		T108	1
values[8]	838	1			T8	1		T28	8		T37	8
values[9]	108	1			T4	9		T8	1		T69	1
minimum	17239	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	7		T219	1		T70	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T139	1		T150	3		T223	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T6	1		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1720	1			T1	1		T2	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T71	1		T136	18		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	4		T153	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T6	5		T11	13		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T12	1		T29	12		T28	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T28	1		T72	5		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T3	4		T34	7		T142	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T108	1		T202	1		T181	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T8	1		T108	1		T144	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T11	16		T143	1		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T182	2		T152	1		T155	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T29	11		T152	1		T146	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T28	11		T108	1		T70	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T37	5		T47	3		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T8	1		T28	4		T136	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T4	6		T8	1		T69	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T177	1		T237	12		T228	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16962	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T142	10		T218	16		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T3	1		T70	8		T197	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T139	13		T150	15		T223	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T5	1		T220	2		T144	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	896	1			T1	6		T30	2		T114	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T71	5		T136	5		T31	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	4		T153	13		T148	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T6	10		T11	13		T140	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T12	7		T29	12		T28	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	4		T72	5		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T34	2		T221	12		T286	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T181	3		T192	2		T224	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T144	8		T156	10		T226	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	15		T143	5		T33	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T155	1		T149	12		T150	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T29	11		T146	16		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T28	12		T70	8		T143	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	3		T47	6		T71	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T28	4		T136	10		T177	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T4	3		T227	9		T228	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T177	10		T228	1		T180	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T28	3		T24	4		T144	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T287	3		T288	7		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T8	1		T69	1		T71	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T8	1		T226	11		T289	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T21	1		T283	1		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T229	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	7		T30	2		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T139	1		T142	10		T150	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	1		T70	9		T220	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T155	13		T171	11		T230	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T5	1		T136	18		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T11	4		T30	1		T70	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T6	5		T11	13		T71	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T12	1		T29	12		T30	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T28	1		T72	5		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T3	4		T28	14		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T108	1		T181	4		T192	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T8	1		T144	11		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T11	16		T202	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T108	1		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T29	11		T152	1		T146	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T28	11		T70	9		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	6		T37	5		T47	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1765	1			T1	1		T2	3		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T71	9		T290	5		T42	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T226	8		T289	11		T291	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	1		T144	5		T32	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T139	13		T150	15		T231	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T70	8		T220	2		T144	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T155	12		T230	1		T223	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T5	1		T136	5		T31	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T11	4		T30	2		T70	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	10		T11	13		T71	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T12	7		T29	12		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T28	4		T72	5		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T28	16		T221	12		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T181	3		T192	2		T224	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T144	8		T34	2		T156	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T11	15		T143	5		T33	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T155	1		T149	12		T150	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T29	11		T146	16		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T28	12		T70	8		T143	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T4	3		T37	3		T47	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1008	1			T1	6		T28	4		T114	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T3	7		T219	1		T70	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T139	14		T150	16		T223	22
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T5	2		T6	1		T220	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1242	1			T1	7		T2	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T71	6		T136	6		T31	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	5		T153	14		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T6	11		T11	14		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T12	8		T29	13		T28	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T28	5		T72	6		T138	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	2		T34	5		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T108	1		T202	1		T181	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T8	1		T108	1		T144	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T11	16		T143	6		T33	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T182	2		T152	1		T155	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T29	12		T152	1		T146	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T28	13		T108	1		T70	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	4		T47	7		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T8	1		T28	6		T136	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T4	8		T8	1		T69	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T177	11		T237	1		T228	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17124	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T142	1		T218	1		T285	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	1		T70	8		T141	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T150	2		T223	11		T231	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T144	12		T140	20		T14	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1374	1			T38	32		T39	21		T70	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T136	17		T31	5		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	3		T142	11		T157	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T6	4		T11	12		T140	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T29	11		T28	12		T32	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T72	4		T145	7		T171	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	2		T34	4		T142	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T181	3		T192	4		T169	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T144	10		T156	7		T233	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T11	15		T33	1		T155	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T234	2		T149	14		T150	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T29	10		T146	7		T13	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T28	10		T70	8		T31	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T37	4		T47	2		T71	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T28	2		T136	11		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T4	1		T236	13		T227	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T237	11		T180	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T144	1		T32	3		T169	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T142	9		T218	15		T292	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T8	1		T69	1		T71	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T8	1		T226	9		T289	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T21	1		T283	1		T284	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T229	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	7		T30	2		T219	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T139	14		T142	1		T150	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T6	1		T70	9		T220	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T155	13		T171	1		T230	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	2		T136	6		T31	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	5		T30	3		T70	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	11		T11	14		T71	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T12	8		T29	13		T30	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T28	5		T72	6		T138	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	2		T28	18		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T108	1		T181	4		T192	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T8	1		T144	9		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T11	16		T202	1		T143	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T108	1		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T29	12		T152	1		T146	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T28	13		T70	9		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T4	8		T37	4		T47	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1362	1			T1	7		T2	3		T9	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T71	11		T236	13		T277	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T226	10		T289	12		T291	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T229	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T3	1		T144	1		T32	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T142	9		T150	2		T231	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T70	8		T144	12		T156	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T155	12		T171	10		T230	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T136	17		T31	5		T232	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T11	3		T70	14		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T6	4		T11	12		T140	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T29	11		T32	2		T140	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T72	4		T145	7		T171	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T3	2		T28	12		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T181	3		T192	4		T224	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T144	10		T34	4		T156	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	15		T33	1		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T149	14		T150	13		T238	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T29	10		T146	7		T239	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T28	10		T70	8		T31	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T4	1		T37	4		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1411	1			T28	2		T38	32		T39	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4