Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22747

1

T1

7

T2

3

T3

38

auto[ADC_CTRL_FILTER_COND_OUT]

3147

1

T3

8

T4

9

T5

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19743

1

T3

46

T4

227

T5

2

auto[1]

6151

1

T1

7

T2

3

T4

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	450	1			T4	13		T6	1		T10	3
values[0]	63	1			T81	14		T293	1		T215	20
values[1]	632	1			T3	4		T28	5		T30	3
values[2]	2904	1			T1	7		T2	3		T4	9
values[3]	868	1			T6	1		T29	46		T28	31
values[4]	676	1			T11	31		T202	1		T31	6
values[5]	790	1			T30	3		T108	1		T71	21
values[6]	555	1			T5	2		T37	8		T219	1
values[7]	507	1			T3	8		T11	8		T30	2
values[8]	560	1			T6	15		T8	1		T11	26
values[9]	1278	1			T8	1		T12	8		T70	46
minimum	16611	1			T3	34		T4	227		T6	116

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	836	1			T3	4		T28	5		T30	3
values[1]	2891	1			T1	7		T2	3		T4	9
values[2]	843	1			T11	31		T29	46		T28	23
values[3]	812	1			T30	3		T72	10		T144	24
values[4]	619	1			T71	21		T140	6		T234	3
values[5]	569	1			T3	8		T5	2		T108	1
values[6]	485	1			T8	1		T30	2		T69	1
values[7]	694	1			T6	15		T11	34		T28	30
values[8]	923	1			T8	1		T70	17		T143	14
values[9]	129	1			T12	8		T143	6		T152	1
minimum	17093	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T3	4		T28	1		T47	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T30	1		T182	1		T153	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1721	1			T1	1		T2	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T4	6		T8	1		T31	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T11	16		T29	23		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T28	11		T108	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T30	1		T144	13		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T72	5		T140	7		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T158	9		T172	1		T238	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T71	12		T140	6		T234	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T108	1		T37	5		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	7		T5	1		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T8	1		T182	1		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T30	2		T69	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T6	5		T11	17		T28	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T70	9		T153	1		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T70	9		T143	1		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T8	1		T137	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T12	1		T143	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T32	3		T170	1		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16921	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T178	1		T295	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T28	4		T47	6		T71	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T30	2		T153	11		T177	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T1	6		T28	4		T114	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	3		T31	4		T239	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T11	15		T29	23		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T28	12		T31	1		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T30	2		T144	11		T138	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T72	5		T140	4		T232	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T158	9		T172	2		T238	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T71	9		T156	10		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T37	3		T136	5		T220	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T3	1		T5	1		T143	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T153	10		T226	15		T227	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T149	12		T42	1		T79	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T6	10		T11	17		T28	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T70	8		T153	13		T14	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T70	8		T143	13		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T170	12		T223	21		T222	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T12	7		T143	5		T266	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T32	2		T170	12		T296	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T295	11		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T4	13		T6	1		T10	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T32	3		T297	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T81	1		T298	14		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T293	1		T215	9		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	4		T28	1		T47	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	1		T153	1		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1683	1			T1	1		T2	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T4	6		T8	1		T31	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	1		T29	23		T28	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T28	11		T108	1		T72	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T11	16		T139	1		T142	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T202	1		T31	5		T140	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	1		T108	1		T144	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T71	12		T140	6		T156	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T37	5		T219	1		T220	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T5	1		T69	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T11	4		T136	18		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	7		T30	2		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T6	5		T8	1		T11	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T70	9		T153	1		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	369	1			T12	1		T70	24		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T8	1		T137	1		T170	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16468	1			T3	34		T4	227		T6	116
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T32	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T81	13		T298	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T215	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	4		T47	6		T146	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T30	2		T153	11		T177	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T1	6		T114	11		T71	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	3		T31	4		T192	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T29	23		T28	4		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T28	12		T72	5		T144	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	15		T139	13		T14	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T31	1		T140	4		T34	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T30	2		T144	11		T138	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T71	9		T156	10		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T37	3		T220	2		T234	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T5	1		T143	4		T155	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T11	4		T136	5		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T3	1		T225	1		T280	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T6	10		T11	13		T28	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T70	8		T153	13		T149	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	339	1			T12	7		T70	22		T143	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T170	24		T223	21		T14	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	2		T28	5		T47	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T30	3		T182	1		T153	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T1	7		T2	3		T6	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T4	8		T8	1		T31	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T11	16		T29	25		T33	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T28	13		T108	1		T202	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T30	3		T144	12		T138	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T72	6		T140	5		T178	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T158	10		T172	3		T238	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T71	10		T140	1		T234	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T108	1		T37	4		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	7		T5	2		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	1		T182	1		T153	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T30	2		T69	1		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T6	11		T11	19		T28	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T70	9		T153	14		T170	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	320	1			T70	9		T143	14		T192	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T8	1		T137	1		T170	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T12	8		T143	6		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T32	3		T170	13		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17073	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T178	1		T295	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	2		T47	2		T155	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T155	9		T13	3		T223	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1383	1			T28	2		T38	32		T39	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T4	1		T31	5		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	15		T29	21		T33	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T28	10		T31	3		T144	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T144	12		T235	11		T198	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T72	4		T140	6		T232	25
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T158	8		T238	15		T245	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T71	11		T140	5		T234	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T37	4		T136	17		T234	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T3	1		T171	10		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T226	13		T87	5		T227	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T140	20		T149	14		T249	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	4		T11	15		T28	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T70	8		T14	11		T198	25
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T70	8		T145	7		T242	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T142	9		T223	11		T233	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T233	13		T266	12		T299	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T32	2		T77	4		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T146	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	444	1			T4	13		T6	1		T10	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T32	3		T297	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T81	14		T298	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T293	1		T215	12		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	2		T28	5		T47	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T30	3		T153	12		T177	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1231	1			T1	7		T2	3		T9	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T4	8		T8	1		T31	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	1		T29	25		T28	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T28	13		T108	1		T72	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	16		T139	14		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T202	1		T31	3		T140	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T30	3		T108	1		T144	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T71	10		T140	1		T156	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T37	4		T219	1		T220	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T5	2		T69	1		T143	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T11	5		T136	6		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	7		T30	2		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T6	11		T8	1		T11	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T70	9		T153	14		T170	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	410	1			T12	8		T70	24		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	331	1			T8	1		T137	1		T170	26
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	34		T4	227		T6	116
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T32	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T298	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T215	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	2		T47	2		T146	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T155	9		T267	3		T300	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1352	1			T38	32		T39	21		T270	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	1		T31	5		T192	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T29	21		T28	2		T33	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T28	10		T72	4		T144	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	15		T142	3		T169	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T31	3		T140	6		T34	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T144	12		T235	11		T198	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T71	11		T140	5		T156	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T37	4		T234	5		T156	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T140	20		T234	2		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T11	3		T136	17		T265	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	1		T268	10		T225	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T6	4		T11	12		T28	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T70	8		T149	14		T198	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T70	22		T145	7		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T142	9		T223	11		T14	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4