Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22556

1

T1

7

T2

3

T3

34

auto[ADC_CTRL_FILTER_COND_OUT]

3338

1

T3

12

T8

1

T11

31

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19587

1

T3

46

T4

227

T5

2

auto[1]

6307

1

T1

7

T2

3

T4

22

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	620	1			T4	13		T6	1		T10	3
values[0]	63	1			T81	14		T293	1		T215	20
values[1]	611	1			T3	4		T28	5		T30	3
values[2]	2868	1			T1	7		T2	3		T8	1
values[3]	846	1			T4	9		T6	1		T29	46
values[4]	808	1			T11	31		T30	3		T72	10
values[5]	745	1			T71	21		T143	5		T144	24
values[6]	535	1			T5	2		T108	1		T37	8
values[7]	538	1			T3	8		T28	30		T30	2
values[8]	530	1			T6	15		T8	1		T11	34
values[9]	1119	1			T8	1		T12	8		T70	46
minimum	16611	1			T3	34		T4	227		T6	116

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	661	1			T3	4		T28	5		T30	3
values[1]	2898	1			T1	7		T2	3		T4	9
values[2]	831	1			T11	31		T29	46		T28	31
values[3]	862	1			T30	3		T72	10		T202	1
values[4]	603	1			T71	21		T140	6		T234	3
values[5]	595	1			T3	8		T5	2		T108	1
values[6]	490	1			T8	1		T11	26		T28	30
values[7]	625	1			T6	15		T11	8		T70	17
values[8]	1016	1			T8	1		T70	46		T73	1
values[9]	79	1			T12	8		T143	6		T152	1
minimum	17234	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T71	1		T153	1		T146	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	4		T28	1		T30	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1713	1			T1	1		T2	3		T4	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T108	1		T31	7		T144	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T29	23		T28	4		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	16		T28	11		T31	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T30	1		T72	5		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T202	1		T138	1		T140	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T71	12		T234	3		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T140	6		T156	8		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T5	1		T37	5		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	7		T108	1		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T8	1		T11	13		T28	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T30	2		T152	1		T140	21
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	5		T11	4		T136	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T70	9		T182	1		T153	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T70	15		T73	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T8	1		T70	9		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T12	1		T143	1		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T170	1		T266	13		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16938	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T178	1		T97	12		T293	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T71	5		T153	11		T146	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T28	4		T30	2		T47	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T1	6		T4	3		T114	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T31	4		T144	5		T239	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T29	23		T28	4		T192	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T11	15		T28	12		T31	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T30	2		T72	5		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T138	1		T140	4		T232	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T71	9		T172	2		T238	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T156	10		T35	1		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T5	1		T37	3		T136	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T3	1		T143	4		T150	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T11	13		T28	16		T153	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T42	1		T280	5		T27	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T6	10		T11	4		T136	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T70	8		T153	13		T177	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T70	14		T143	13		T197	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T70	8		T32	2		T170	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T12	7		T143	5		T296	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T170	12		T266	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T28	3		T24	4		T32	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T97	13		T275	8		T255	9

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	471	1			T4	13		T6	1		T10	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T32	3		T170	2		T222	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T81	1		T293	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T215	9		T298	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T153	1		T146	8		T155	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	4		T28	1		T30	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1676	1			T1	1		T2	3		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T108	1		T31	7		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T4	6		T6	1		T29	23
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T28	11		T144	2		T32	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T30	1		T72	5		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	16		T202	1		T31	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T71	12		T144	13		T235	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T143	1		T138	1		T140	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	1		T37	5		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T108	1		T137	1		T171	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T28	14		T136	18		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	7		T30	2		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T6	5		T8	1		T11	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T70	9		T182	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T12	1		T70	15		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T8	1		T70	9		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16468	1			T3	34		T4	227		T6	116
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T197	12		T264	15		T176	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T32	2		T170	24		T222	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T81	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T215	11		T298	14		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T153	11		T146	16		T155	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T28	4		T30	2		T47	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T1	6		T114	11		T71	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T31	4		T239	6		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T4	3		T29	23		T28	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T28	12		T144	5		T32	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	2		T72	5		T34	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	15		T31	1		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T71	9		T144	11		T238	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T143	4		T138	1		T156	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T5	1		T37	3		T220	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T150	15		T158	9		T290	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T28	16		T136	5		T153	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T3	1		T280	5		T267	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T6	10		T11	17		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T70	8		T153	13		T177	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T12	7		T70	14		T143	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T70	8		T223	21		T242	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T71	6		T153	12		T146	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	2		T28	5		T30	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1286	1			T1	7		T2	3		T4	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T108	1		T31	6		T144	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T29	25		T28	6		T108	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T11	16		T28	13		T31	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T30	3		T72	6		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T202	1		T138	2		T140	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T71	10		T234	1		T243	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	1		T156	11		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	2		T37	4		T219	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	7		T108	1		T69	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	1		T11	14		T28	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T30	2		T152	1		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	11		T11	5		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T70	9		T182	1		T153	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T70	15		T73	1		T143	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T8	1		T70	9		T192	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T12	8		T143	6		T152	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T170	13		T266	15		T294	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17114	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T178	1		T97	14		T293	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T146	7		T155	12		T169	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	2		T47	2		T155	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1369	1			T4	1		T38	32		T39	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T31	5		T144	1		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T29	21		T28	2		T192	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	15		T28	10		T31	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T72	4		T144	12		T235	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T140	6		T232	14		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T71	11		T234	2		T301	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T140	5		T156	7		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T37	4		T136	17		T234	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T3	1		T171	10		T150	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T11	12		T28	12		T226	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T140	20		T85	18		T87	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T6	4		T11	3		T136	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T70	8		T198	25		T302	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T70	14		T145	7		T14	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T70	8		T32	2		T142	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T266	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T303	9		T304	5		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T97	11		T305	7		T275	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	501	1			T4	13		T6	1		T10	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T32	3		T170	26		T222	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T81	14		T293	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T215	12		T298	15		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T153	12		T146	17		T155	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	2		T28	5		T30	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T1	7		T2	3		T8	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T108	1		T31	6		T182	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	8		T6	1		T29	25
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T28	13		T144	6		T32	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	3		T72	6		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T11	16		T202	1		T31	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T71	10		T144	12		T235	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T143	5		T138	2		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T5	2		T37	4		T219	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T108	1		T137	1		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T28	18		T136	6		T153	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	7		T30	2		T69	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T6	11		T8	1		T11	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T70	9		T182	1		T153	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T12	8		T70	15		T73	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T8	1		T70	9		T192	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16611	1			T3	34		T4	227		T6	116
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T306	7		T269	7		T288	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T32	2		T266	12		T307	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T215	8		T298	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T146	7		T155	12		T169	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	2		T47	2		T155	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T38	32		T39	21		T270	25
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T31	5		T239	5		T13	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T29	21		T28	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T28	10		T144	1		T32	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T72	4		T34	4		T142	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	15		T31	3		T140	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T71	11		T144	12		T235	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T140	5		T156	7		T171	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T37	4		T234	7		T266	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T171	10		T150	2		T158	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T28	12		T136	17		T156	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	1		T140	20		T268	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T6	4		T11	15		T136	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T70	8		T198	9		T85	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T70	14		T145	7		T157	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T70	8		T142	9		T223	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4