Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25894

1

T1

7

T2

3

T3

46

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22612

1

T1

7

T2

3

T3

42

auto[ADC_CTRL_FILTER_COND_OUT]

3282

1

T3

4

T4

9

T6

15

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20241

1

T3

42

T4

240

T6

132

auto[1]

5653

1

T1

7

T2

3

T3

4

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22107

1

T1

1

T2

3

T3

45

auto[1]

3787

1

T1

6

T3

1

T4

3

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	383	1			T6	15		T181	7		T177	11
values[0]	13	1			T16	3		T176	10		-	-
values[1]	683	1			T11	26		T73	1		T143	6
values[2]	454	1			T28	30		T70	17		T140	11
values[3]	714	1			T12	8		T30	3		T108	1
values[4]	681	1			T8	1		T28	23		T136	22
values[5]	2892	1			T1	7		T2	3		T6	1
values[6]	844	1			T8	1		T11	31		T28	5
values[7]	695	1			T3	4		T37	8		T71	6
values[8]	603	1			T4	9		T8	1		T28	8
values[9]	877	1			T3	8		T5	2		T11	8
minimum	17055	1			T3	34		T4	240		T6	117

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	581	1			T144	19		T137	1		T33	3
values[1]	520	1			T28	30		T70	17		T143	14
values[2]	750	1			T12	8		T30	3		T108	1
values[3]	2853	1			T1	7		T2	3		T8	1
values[4]	640	1			T6	1		T29	22		T28	5
values[5]	832	1			T8	1		T11	31		T30	2
values[6]	783	1			T3	4		T28	8		T71	6
values[7]	541	1			T4	9		T8	1		T11	8
values[8]	957	1			T3	8		T5	2		T6	15
values[9]	164	1			T136	23		T243	16		T226	19
minimum	17273	1			T3	34		T4	240		T6	117

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

4164

1

T3

3

T4

1

T6

4

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T144	11		T33	2		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T137	1		T155	1		T142	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T70	9		T143	1		T145	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T28	14		T178	1		T34	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T108	1		T146	9		T308	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T12	1		T30	1		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1663	1			T1	1		T2	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T153	1		T197	1		T140	21
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	1		T29	11		T30	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	1		T108	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T30	2		T37	5		T70	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T11	16		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T28	4		T71	1		T31	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	4		T192	5		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T234	6		T157	13		T171	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	6		T8	1		T11	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T3	7		T5	1		T29	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T6	5		T219	1		T31	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T136	18		T226	11		T248	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T243	1		T249	2		T277	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16961	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T11	13		T73	1		T150	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T144	8		T33	1		T148	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T155	1		T239	6		T13	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T70	8		T143	13		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T28	16		T34	2		T232	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T146	16		T224	11		T150	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T12	7		T30	2		T144	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	882	1			T1	6		T28	12		T114	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T153	10		T197	12		T231	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T29	11		T30	2		T138	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	4		T71	9		T244	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T37	3		T70	14		T72	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T11	15		T144	5		T32	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T28	4		T71	5		T31	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T192	2		T155	9		T170	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T234	6		T157	12		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T4	3		T11	4		T70	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T5	1		T29	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T6	10		T31	1		T156	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T136	5		T226	8		T248	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T243	15		T227	1		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T28	3		T143	5		T24	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T11	13		T150	15		T160	11

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T181	4		T177	1		T230	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T6	5		T243	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T176	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T16	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T143	1		T144	11		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T11	13		T73	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T70	9		T140	7		T177	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T28	14		T178	1		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T108	1		T143	1		T145	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T12	1		T30	1		T144	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	1		T28	11		T136	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T192	1		T153	1		T197	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1617	1			T1	1		T2	3		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T108	1		T69	1		T71	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T30	2		T70	15		T72	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T8	1		T11	16		T28	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T37	5		T71	1		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	4		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T28	4		T31	7		T234	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T4	6		T8	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	7		T5	1		T29	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	4		T219	1		T70	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16912	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T181	3		T177	10		T230	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T6	10		T243	15		T216	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T176	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T16	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T143	5		T144	8		T33	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	13		T239	6		T150	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T70	8		T140	4		T177	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T28	16		T155	1		T34	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T143	13		T146	16		T150	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	7		T30	2		T144	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T28	12		T136	10		T220	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T153	10		T197	12		T160	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T1	6		T29	11		T30	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T71	9		T231	6		T159	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T70	14		T72	5		T32	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	15		T28	4		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T37	3		T71	5		T153	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T192	2		T170	24		T232	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T28	4		T31	4		T234	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	3		T155	9		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	1		T5	1		T29	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	4		T70	8		T31	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T28	3		T24	4		T32	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T144	9		T33	2		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T137	1		T155	2		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T70	9		T143	14		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T28	18		T178	1		T34	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T108	1		T146	18		T308	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T12	8		T30	3		T144	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1215	1			T1	7		T2	3		T8	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T153	11		T197	13		T140	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T6	1		T29	12		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	5		T108	1		T69	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T30	2		T37	4		T70	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T8	1		T11	16		T182	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T28	6		T71	6		T31	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	2		T192	3		T155	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T234	7		T157	13		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T4	8		T8	1		T11	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	7		T5	2		T29	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	11		T219	1		T31	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T136	6		T226	9		T248	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T243	16		T249	1		T277	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17118	1			T3	34		T4	240		T6	117
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T11	14		T73	1		T150	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T144	10		T33	1		T242	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T142	9		T239	5		T13	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T70	8		T145	7		T140	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T28	12		T34	4		T232	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T146	7		T169	16		T224	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T144	12		T223	16		T160	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1330	1			T28	10		T38	32		T39	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T140	20		T142	11		T231	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T29	10		T234	2		T169	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T71	11		T244	9		T241	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T37	4		T70	14		T72	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T11	15		T144	1		T32	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T28	2		T31	5		T198	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	2		T192	4		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T234	5		T157	12		T171	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T4	1		T11	3		T70	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	1		T29	11		T47	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	4		T31	3		T156	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T136	17		T226	10		T248	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T249	1		T277	11		T309	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T227	8		T310	11		T311	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T11	12		T150	2		T160	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T181	4		T177	11		T230	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T6	11		T243	16		T216	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T176	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T16	3		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T143	6		T144	9		T33	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	14		T73	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T70	9		T140	5		T177	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T28	18		T178	1		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T108	1		T143	14		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	8		T30	3		T144	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T8	1		T28	13		T136	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T192	1		T153	11		T197	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1274	1			T1	7		T2	3		T6	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T108	1		T69	1		T71	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T30	2		T70	15		T72	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T8	1		T11	16		T28	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T37	4		T71	6		T153	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T3	2		T182	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T28	6		T31	6		T234	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T4	8		T8	1		T108	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T3	7		T5	2		T29	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T11	5		T219	1		T70	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17055	1			T3	34		T4	240		T6	117
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T181	3		T230	3		T226	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T6	4		T221	11		T277	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T144	10		T33	1		T242	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	12		T142	9		T239	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T70	8		T140	6		T141	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T28	12		T34	4		T236	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T145	7		T146	7		T169	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	12		T232	11		T223	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T28	10		T136	11		T156	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T140	20		T142	11		T160	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T29	10		T38	32		T39	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T71	11		T231	9		T87	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T70	14		T72	4		T32	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T11	15		T144	1		T32	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T37	4		T253	7		T88	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	2		T192	4		T232	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T28	2		T31	5		T234	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T4	1		T155	9		T235	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	1		T29	11		T47	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T11	3		T70	8		T31	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21730

1

T1

7

T2

3

T3

43

auto[1]

auto[0]

4164

1

T3

3

T4

1

T6

4