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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.82 99.07 96.67 100.00 100.00 98.83 98.33 91.84


Total test records in report: 917
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T790 /workspace/coverage/default/21.adc_ctrl_filters_polled.1245172166 Jul 07 06:01:17 PM PDT 24 Jul 07 06:04:29 PM PDT 24 330720099367 ps
T791 /workspace/coverage/default/44.adc_ctrl_filters_both.3506824218 Jul 07 06:04:37 PM PDT 24 Jul 07 06:14:20 PM PDT 24 505396017325 ps
T792 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4167179778 Jul 07 05:59:55 PM PDT 24 Jul 07 05:59:57 PM PDT 24 382471183 ps
T51 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1768727776 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:37 PM PDT 24 571376172 ps
T793 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3142255488 Jul 07 06:00:01 PM PDT 24 Jul 07 06:00:03 PM PDT 24 471433002 ps
T134 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3372246829 Jul 07 05:59:46 PM PDT 24 Jul 07 05:59:48 PM PDT 24 435838380 ps
T44 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2214786904 Jul 07 05:59:53 PM PDT 24 Jul 07 05:59:55 PM PDT 24 2423254006 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1468928969 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:32 PM PDT 24 495163830 ps
T48 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1771069325 Jul 07 05:59:51 PM PDT 24 Jul 07 06:00:14 PM PDT 24 8686273985 ps
T45 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3313463978 Jul 07 05:59:36 PM PDT 24 Jul 07 06:01:09 PM PDT 24 44174768516 ps
T794 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2433417449 Jul 07 05:59:59 PM PDT 24 Jul 07 06:00:00 PM PDT 24 329010269 ps
T795 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3963323583 Jul 07 05:59:54 PM PDT 24 Jul 07 05:59:56 PM PDT 24 509334159 ps
T52 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.21688143 Jul 07 05:59:38 PM PDT 24 Jul 07 05:59:40 PM PDT 24 665897618 ps
T118 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1941261493 Jul 07 05:59:27 PM PDT 24 Jul 07 05:59:31 PM PDT 24 800272508 ps
T64 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.371958467 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:49 PM PDT 24 375528325 ps
T46 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1319855571 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:55 PM PDT 24 22966131696 ps
T78 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3767841817 Jul 07 05:59:44 PM PDT 24 Jul 07 05:59:46 PM PDT 24 403157317 ps
T796 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4032134855 Jul 07 05:59:32 PM PDT 24 Jul 07 05:59:33 PM PDT 24 320477364 ps
T135 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.484641845 Jul 07 05:59:30 PM PDT 24 Jul 07 05:59:32 PM PDT 24 541843978 ps
T49 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3933530983 Jul 07 05:59:33 PM PDT 24 Jul 07 05:59:41 PM PDT 24 4412154942 ps
T56 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.374906291 Jul 07 05:59:43 PM PDT 24 Jul 07 05:59:46 PM PDT 24 764452573 ps
T128 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1846561824 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:36 PM PDT 24 502517989 ps
T57 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2359405789 Jul 07 05:59:43 PM PDT 24 Jul 07 05:59:45 PM PDT 24 392549062 ps
T797 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1164658213 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:38 PM PDT 24 345831525 ps
T50 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3923942564 Jul 07 05:59:45 PM PDT 24 Jul 07 05:59:54 PM PDT 24 8388767588 ps
T129 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3839108597 Jul 07 05:59:30 PM PDT 24 Jul 07 05:59:32 PM PDT 24 2715453681 ps
T798 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.62274883 Jul 07 05:59:59 PM PDT 24 Jul 07 06:00:01 PM PDT 24 351874956 ps
T59 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.539654851 Jul 07 05:59:32 PM PDT 24 Jul 07 05:59:40 PM PDT 24 8668916782 ps
T799 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1758537452 Jul 07 05:59:52 PM PDT 24 Jul 07 05:59:53 PM PDT 24 421316313 ps
T58 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1421136761 Jul 07 05:59:32 PM PDT 24 Jul 07 05:59:35 PM PDT 24 889530415 ps
T800 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1027745882 Jul 07 05:59:43 PM PDT 24 Jul 07 05:59:45 PM PDT 24 426930803 ps
T119 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.719206184 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:37 PM PDT 24 1284216008 ps
T62 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.743003795 Jul 07 05:59:48 PM PDT 24 Jul 07 06:00:09 PM PDT 24 8407836068 ps
T65 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2221449769 Jul 07 05:59:41 PM PDT 24 Jul 07 05:59:44 PM PDT 24 4781735054 ps
T130 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1740714366 Jul 07 06:00:07 PM PDT 24 Jul 07 06:00:11 PM PDT 24 2527007201 ps
T801 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3292098295 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:09 PM PDT 24 429500466 ps
T802 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2572137319 Jul 07 05:59:49 PM PDT 24 Jul 07 05:59:50 PM PDT 24 308231641 ps
T131 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1316294933 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:37 PM PDT 24 346657554 ps
T803 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4159001137 Jul 07 05:59:38 PM PDT 24 Jul 07 05:59:40 PM PDT 24 454853223 ps
T804 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.882600850 Jul 07 05:59:34 PM PDT 24 Jul 07 05:59:37 PM PDT 24 567575769 ps
T805 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3029705009 Jul 07 05:59:51 PM PDT 24 Jul 07 05:59:53 PM PDT 24 838019605 ps
T63 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1774362302 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:49 PM PDT 24 611728898 ps
T132 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3256491937 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 493531612 ps
T806 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3743205544 Jul 07 05:59:56 PM PDT 24 Jul 07 05:59:57 PM PDT 24 457610071 ps
T807 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2399516091 Jul 07 05:59:42 PM PDT 24 Jul 07 05:59:44 PM PDT 24 403169269 ps
T808 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3240249934 Jul 07 05:59:28 PM PDT 24 Jul 07 05:59:30 PM PDT 24 827229651 ps
T809 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2389499992 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:38 PM PDT 24 621015954 ps
T120 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1196004965 Jul 07 05:59:46 PM PDT 24 Jul 07 05:59:47 PM PDT 24 341892103 ps
T810 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.514028098 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:33 PM PDT 24 563813658 ps
T811 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3072803661 Jul 07 05:59:54 PM PDT 24 Jul 07 05:59:56 PM PDT 24 516503712 ps
T121 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.459673484 Jul 07 05:59:50 PM PDT 24 Jul 07 05:59:51 PM PDT 24 437181948 ps
T812 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.7912945 Jul 07 05:59:41 PM PDT 24 Jul 07 06:00:05 PM PDT 24 8877061594 ps
T133 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1227407384 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:41 PM PDT 24 4831070572 ps
T813 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3774871463 Jul 07 06:00:05 PM PDT 24 Jul 07 06:00:07 PM PDT 24 385589667 ps
T814 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3039972959 Jul 07 05:59:51 PM PDT 24 Jul 07 05:59:54 PM PDT 24 581951651 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2608106114 Jul 07 05:59:29 PM PDT 24 Jul 07 05:59:47 PM PDT 24 10895206530 ps
T815 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1452102833 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:59 PM PDT 24 4948616525 ps
T816 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.547748044 Jul 07 05:59:51 PM PDT 24 Jul 07 05:59:55 PM PDT 24 4566007512 ps
T817 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.121642 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:02 PM PDT 24 365254170 ps
T818 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.38987297 Jul 07 05:59:34 PM PDT 24 Jul 07 05:59:36 PM PDT 24 697607291 ps
T819 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.510026825 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:09 PM PDT 24 364153226 ps
T820 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4014242667 Jul 07 05:59:42 PM PDT 24 Jul 07 05:59:43 PM PDT 24 831531111 ps
T821 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3872564710 Jul 07 05:59:48 PM PDT 24 Jul 07 05:59:52 PM PDT 24 5104469785 ps
T822 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.707694510 Jul 07 05:59:46 PM PDT 24 Jul 07 05:59:49 PM PDT 24 2132601290 ps
T823 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3464913870 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 344968782 ps
T824 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2263656154 Jul 07 05:59:42 PM PDT 24 Jul 07 05:59:44 PM PDT 24 295799337 ps
T123 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1357753097 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:38 PM PDT 24 1294736225 ps
T66 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4183158723 Jul 07 05:59:41 PM PDT 24 Jul 07 05:59:53 PM PDT 24 8310364194 ps
T825 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2067212398 Jul 07 05:59:56 PM PDT 24 Jul 07 05:59:58 PM PDT 24 518134642 ps
T826 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2864497507 Jul 07 05:59:50 PM PDT 24 Jul 07 05:59:52 PM PDT 24 512580907 ps
T827 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3095226980 Jul 07 05:59:51 PM PDT 24 Jul 07 05:59:54 PM PDT 24 5070036422 ps
T828 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2321888160 Jul 07 05:59:49 PM PDT 24 Jul 07 05:59:51 PM PDT 24 497619168 ps
T829 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3113715382 Jul 07 05:59:51 PM PDT 24 Jul 07 05:59:55 PM PDT 24 443451317 ps
T830 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2607374601 Jul 07 05:59:39 PM PDT 24 Jul 07 05:59:40 PM PDT 24 434492642 ps
T831 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.356128145 Jul 07 05:59:46 PM PDT 24 Jul 07 05:59:48 PM PDT 24 5001760942 ps
T832 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4077499205 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:39 PM PDT 24 2828371580 ps
T833 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.248253965 Jul 07 05:59:39 PM PDT 24 Jul 07 05:59:54 PM PDT 24 4287099649 ps
T834 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3495641277 Jul 07 05:59:52 PM PDT 24 Jul 07 05:59:54 PM PDT 24 525529759 ps
T124 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2307907667 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:32 PM PDT 24 354397038 ps
T835 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2971905482 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:49 PM PDT 24 607644241 ps
T836 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1012362888 Jul 07 05:59:39 PM PDT 24 Jul 07 06:00:00 PM PDT 24 5324181066 ps
T837 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1097830463 Jul 07 05:59:38 PM PDT 24 Jul 07 05:59:46 PM PDT 24 2309057011 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1937771270 Jul 07 05:59:46 PM PDT 24 Jul 07 05:59:48 PM PDT 24 4397225989 ps
T839 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4246660410 Jul 07 05:59:25 PM PDT 24 Jul 07 05:59:27 PM PDT 24 459095059 ps
T840 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3448723728 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:33 PM PDT 24 528142767 ps
T125 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4038737080 Jul 07 05:59:33 PM PDT 24 Jul 07 05:59:38 PM PDT 24 1060730444 ps
T841 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1129437215 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:49 PM PDT 24 473573975 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3899825836 Jul 07 05:59:32 PM PDT 24 Jul 07 05:59:35 PM PDT 24 938794440 ps
T842 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.145298155 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:38 PM PDT 24 410222357 ps
T843 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1631826801 Jul 07 05:59:49 PM PDT 24 Jul 07 05:59:51 PM PDT 24 438530580 ps
T844 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.454794892 Jul 07 05:59:54 PM PDT 24 Jul 07 05:59:55 PM PDT 24 362103014 ps
T845 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.812311942 Jul 07 06:00:07 PM PDT 24 Jul 07 06:00:09 PM PDT 24 486314409 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1520766348 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:53 PM PDT 24 31284069512 ps
T847 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2563159205 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:49 PM PDT 24 435146621 ps
T848 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2653197887 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:35 PM PDT 24 4774697536 ps
T849 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.691115396 Jul 07 06:00:07 PM PDT 24 Jul 07 06:00:10 PM PDT 24 456684403 ps
T850 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3176277471 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 315641467 ps
T851 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3438470389 Jul 07 05:59:55 PM PDT 24 Jul 07 05:59:56 PM PDT 24 329342810 ps
T852 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1666918716 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 487125573 ps
T853 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.215441472 Jul 07 05:59:32 PM PDT 24 Jul 07 05:59:33 PM PDT 24 579296951 ps
T854 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2643449640 Jul 07 05:59:54 PM PDT 24 Jul 07 05:59:56 PM PDT 24 423258564 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2655898684 Jul 07 05:59:30 PM PDT 24 Jul 07 05:59:34 PM PDT 24 537456360 ps
T856 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1331865669 Jul 07 05:59:52 PM PDT 24 Jul 07 06:00:03 PM PDT 24 4483000857 ps
T857 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2807074867 Jul 07 05:59:41 PM PDT 24 Jul 07 05:59:42 PM PDT 24 509575570 ps
T858 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3443352465 Jul 07 05:59:34 PM PDT 24 Jul 07 05:59:35 PM PDT 24 566710502 ps
T859 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.73689611 Jul 07 05:59:54 PM PDT 24 Jul 07 05:59:55 PM PDT 24 406093220 ps
T860 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2292070547 Jul 07 05:59:53 PM PDT 24 Jul 07 05:59:54 PM PDT 24 361723216 ps
T861 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2390012263 Jul 07 05:59:49 PM PDT 24 Jul 07 05:59:51 PM PDT 24 502147981 ps
T862 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.150653869 Jul 07 05:59:43 PM PDT 24 Jul 07 05:59:44 PM PDT 24 504510448 ps
T863 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2258607028 Jul 07 05:59:45 PM PDT 24 Jul 07 05:59:47 PM PDT 24 360208380 ps
T864 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2083650091 Jul 07 05:59:50 PM PDT 24 Jul 07 05:59:51 PM PDT 24 396698483 ps
T865 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2235696676 Jul 07 05:59:36 PM PDT 24 Jul 07 05:59:38 PM PDT 24 541624438 ps
T866 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4075298944 Jul 07 05:59:29 PM PDT 24 Jul 07 05:59:32 PM PDT 24 343274557 ps
T867 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2761211037 Jul 07 05:59:56 PM PDT 24 Jul 07 05:59:58 PM PDT 24 389233579 ps
T868 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.830252655 Jul 07 05:59:46 PM PDT 24 Jul 07 05:59:48 PM PDT 24 394874479 ps
T869 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.341474422 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:49 PM PDT 24 518899508 ps
T870 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3670241004 Jul 07 05:59:38 PM PDT 24 Jul 07 05:59:46 PM PDT 24 4606789231 ps
T871 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.900229434 Jul 07 05:59:29 PM PDT 24 Jul 07 05:59:30 PM PDT 24 547788107 ps
T872 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1711540847 Jul 07 06:00:01 PM PDT 24 Jul 07 06:00:03 PM PDT 24 499767803 ps
T873 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4072438854 Jul 07 05:59:29 PM PDT 24 Jul 07 05:59:32 PM PDT 24 687666911 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3874124063 Jul 07 05:59:43 PM PDT 24 Jul 07 05:59:44 PM PDT 24 336593289 ps
T875 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3517698034 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 287433839 ps
T876 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3385826410 Jul 07 05:59:57 PM PDT 24 Jul 07 05:59:59 PM PDT 24 489774561 ps
T877 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3014083852 Jul 07 05:59:55 PM PDT 24 Jul 07 05:59:56 PM PDT 24 343490188 ps
T878 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.495511384 Jul 07 05:59:47 PM PDT 24 Jul 07 05:59:48 PM PDT 24 451192657 ps
T879 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.304634011 Jul 07 05:59:31 PM PDT 24 Jul 07 06:00:06 PM PDT 24 51789600421 ps
T880 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.197822467 Jul 07 05:59:27 PM PDT 24 Jul 07 05:59:30 PM PDT 24 3580670259 ps
T881 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2380920372 Jul 07 06:00:08 PM PDT 24 Jul 07 06:00:10 PM PDT 24 426071783 ps
T882 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.809613015 Jul 07 05:59:56 PM PDT 24 Jul 07 05:59:59 PM PDT 24 2407054500 ps
T883 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.504998669 Jul 07 05:59:32 PM PDT 24 Jul 07 05:59:37 PM PDT 24 4279990358 ps
T884 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3657783099 Jul 07 05:59:47 PM PDT 24 Jul 07 06:00:00 PM PDT 24 4427784668 ps
T885 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3303308406 Jul 07 05:59:41 PM PDT 24 Jul 07 05:59:44 PM PDT 24 606009731 ps
T886 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2485084266 Jul 07 05:59:41 PM PDT 24 Jul 07 05:59:42 PM PDT 24 526211887 ps
T887 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2758433128 Jul 07 05:59:43 PM PDT 24 Jul 07 05:59:45 PM PDT 24 652278539 ps
T888 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.169349589 Jul 07 05:59:55 PM PDT 24 Jul 07 05:59:56 PM PDT 24 486969608 ps
T889 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3887226623 Jul 07 05:59:33 PM PDT 24 Jul 07 05:59:36 PM PDT 24 637027780 ps
T890 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3029745546 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:36 PM PDT 24 296173885 ps
T891 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4023019440 Jul 07 05:59:40 PM PDT 24 Jul 07 05:59:41 PM PDT 24 342219621 ps
T892 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.46316764 Jul 07 06:00:03 PM PDT 24 Jul 07 06:00:04 PM PDT 24 479535919 ps
T893 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3547580595 Jul 07 05:59:44 PM PDT 24 Jul 07 05:59:50 PM PDT 24 2364251934 ps
T894 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1254110729 Jul 07 05:59:31 PM PDT 24 Jul 07 05:59:32 PM PDT 24 425828292 ps
T895 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.319661234 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:01 PM PDT 24 314705260 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1944325628 Jul 07 05:59:27 PM PDT 24 Jul 07 05:59:30 PM PDT 24 503951360 ps
T127 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.635330601 Jul 07 05:59:37 PM PDT 24 Jul 07 05:59:38 PM PDT 24 469709806 ps
T897 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1343351247 Jul 07 05:59:34 PM PDT 24 Jul 07 05:59:38 PM PDT 24 644594711 ps
T898 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1117712118 Jul 07 05:59:53 PM PDT 24 Jul 07 05:59:55 PM PDT 24 584888320 ps
T899 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4286909311 Jul 07 06:00:00 PM PDT 24 Jul 07 06:00:02 PM PDT 24 443651122 ps
T900 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4231651800 Jul 07 05:59:55 PM PDT 24 Jul 07 05:59:57 PM PDT 24 326352944 ps
T901 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1769326955 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:48 PM PDT 24 4413608676 ps
T902 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4003160164 Jul 07 05:59:49 PM PDT 24 Jul 07 05:59:50 PM PDT 24 585300778 ps
T903 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.464207152 Jul 07 05:59:34 PM PDT 24 Jul 07 05:59:37 PM PDT 24 478706795 ps
T904 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3869064034 Jul 07 05:59:48 PM PDT 24 Jul 07 05:59:51 PM PDT 24 4608270822 ps
T905 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.396916989 Jul 07 05:59:50 PM PDT 24 Jul 07 05:59:51 PM PDT 24 438637946 ps
T906 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1627642979 Jul 07 05:59:35 PM PDT 24 Jul 07 05:59:39 PM PDT 24 2602156865 ps
T907 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2061524724 Jul 07 05:59:42 PM PDT 24 Jul 07 05:59:44 PM PDT 24 349433361 ps
T908 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3897662707 Jul 07 06:00:03 PM PDT 24 Jul 07 06:00:04 PM PDT 24 438787498 ps
T909 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2784170013 Jul 07 05:59:33 PM PDT 24 Jul 07 05:59:34 PM PDT 24 350946191 ps
T910 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3042516597 Jul 07 05:59:39 PM PDT 24 Jul 07 05:59:42 PM PDT 24 387776451 ps
T911 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3675310009 Jul 07 05:59:53 PM PDT 24 Jul 07 05:59:54 PM PDT 24 369263977 ps
T912 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3390311482 Jul 07 05:59:39 PM PDT 24 Jul 07 06:00:03 PM PDT 24 8388717845 ps
T913 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3731036332 Jul 07 05:59:44 PM PDT 24 Jul 07 05:59:48 PM PDT 24 2725657012 ps
T914 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2475416246 Jul 07 05:59:59 PM PDT 24 Jul 07 06:00:01 PM PDT 24 386886584 ps
T915 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.987321411 Jul 07 05:59:55 PM PDT 24 Jul 07 06:00:08 PM PDT 24 8426785640 ps
T334 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1041307735 Jul 07 05:59:53 PM PDT 24 Jul 07 05:59:57 PM PDT 24 4884977044 ps
T335 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.399713292 Jul 07 05:59:27 PM PDT 24 Jul 07 05:59:32 PM PDT 24 4470353760 ps
T916 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3159228702 Jul 07 05:59:27 PM PDT 24 Jul 07 05:59:28 PM PDT 24 660168335 ps
T917 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3158804201 Jul 07 05:59:33 PM PDT 24 Jul 07 05:59:41 PM PDT 24 2307438750 ps

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.2361147847
Short name T4
Test name
Test status
Simulation time 236908636683 ps
CPU time 538.05 seconds
Started Jul 07 06:01:54 PM PDT 24
Finished Jul 07 06:10:53 PM PDT 24
Peak memory 210496 kb
Host smart-9d96a434-754e-4947-bd16-1d9169577882
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361147847 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.2361147847
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1155201961
Short name T11
Test name
Test status
Simulation time 513901042942 ps
CPU time 1210.46 seconds
Started Jul 07 06:03:52 PM PDT 24
Finished Jul 07 06:24:03 PM PDT 24
Peak memory 201852 kb
Host smart-3be84c6d-facf-40be-8c94-6f97abf5948d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155201961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1155201961
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.1244496290
Short name T30
Test name
Test status
Simulation time 63650041813 ps
CPU time 34.01 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:01:30 PM PDT 24
Peak memory 210228 kb
Host smart-3f51b201-3b18-4030-b182-52ee96cda521
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244496290 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.1244496290
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.2431970749
Short name T28
Test name
Test status
Simulation time 449968860741 ps
CPU time 193.11 seconds
Started Jul 07 06:02:27 PM PDT 24
Finished Jul 07 06:05:40 PM PDT 24
Peak memory 212520 kb
Host smart-e48b728f-1c31-468c-82a1-ed49766fbb7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431970749 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.2431970749
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2446895187
Short name T144
Test name
Test status
Simulation time 497924608336 ps
CPU time 140.25 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:02:52 PM PDT 24
Peak memory 201888 kb
Host smart-3a504d39-0564-486c-8ac9-899714af4fa0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446895187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2446895187
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.880410713
Short name T14
Test name
Test status
Simulation time 248099116007 ps
CPU time 175.52 seconds
Started Jul 07 06:00:29 PM PDT 24
Finished Jul 07 06:03:25 PM PDT 24
Peak memory 210480 kb
Host smart-f60442b9-6c50-4400-8c04-317b633db49c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880410713 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.880410713
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.1861193313
Short name T155
Test name
Test status
Simulation time 484367959025 ps
CPU time 398.86 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:07:10 PM PDT 24
Peak memory 201992 kb
Host smart-c8dc6dd8-98f0-4a6b-9800-a9284246ebac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861193313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.1861193313
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3747358072
Short name T140
Test name
Test status
Simulation time 508365383894 ps
CPU time 1177.24 seconds
Started Jul 07 06:01:28 PM PDT 24
Finished Jul 07 06:21:05 PM PDT 24
Peak memory 201916 kb
Host smart-65712611-8626-491c-8cc1-aa247d77cb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747358072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3747358072
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.276979878
Short name T143
Test name
Test status
Simulation time 500170239832 ps
CPU time 143.12 seconds
Started Jul 07 06:01:57 PM PDT 24
Finished Jul 07 06:04:20 PM PDT 24
Peak memory 201856 kb
Host smart-7ffb373a-2583-48b1-8a17-f70fcd98f9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276979878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.276979878
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.374906291
Short name T56
Test name
Test status
Simulation time 764452573 ps
CPU time 2.74 seconds
Started Jul 07 05:59:43 PM PDT 24
Finished Jul 07 05:59:46 PM PDT 24
Peak memory 201784 kb
Host smart-fbf4410d-a5c1-4c97-8e11-8c7ee8bd2a45
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374906291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.374906291
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.3876444703
Short name T171
Test name
Test status
Simulation time 536957497198 ps
CPU time 276.2 seconds
Started Jul 07 06:02:20 PM PDT 24
Finished Jul 07 06:06:56 PM PDT 24
Peak memory 201912 kb
Host smart-bc230f2a-f7ff-494e-a7c8-c743e0848374
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876444703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.3876444703
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3984258919
Short name T53
Test name
Test status
Simulation time 8235126784 ps
CPU time 19.63 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:00:55 PM PDT 24
Peak memory 218212 kb
Host smart-64213d6a-3815-477c-803c-03215c999c77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984258919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3984258919
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.286864282
Short name T232
Test name
Test status
Simulation time 327668016813 ps
CPU time 190.76 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:03:56 PM PDT 24
Peak memory 201892 kb
Host smart-e649cc31-4a18-4a22-bf37-4b3620cb0b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286864282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.286864282
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.794563943
Short name T159
Test name
Test status
Simulation time 495892352558 ps
CPU time 122.72 seconds
Started Jul 07 06:04:51 PM PDT 24
Finished Jul 07 06:06:54 PM PDT 24
Peak memory 201760 kb
Host smart-5b915fe0-0dac-4d02-8804-d2283e198c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794563943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.794563943
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.1213432970
Short name T31
Test name
Test status
Simulation time 573923508608 ps
CPU time 124.02 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:03:01 PM PDT 24
Peak memory 210492 kb
Host smart-38869b44-7cfb-4444-8f2b-afd19e8df27c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213432970 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.1213432970
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1319855571
Short name T46
Test name
Test status
Simulation time 22966131696 ps
CPU time 22.92 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 201840 kb
Host smart-85263c48-d04e-4a4d-96ba-7bdb86d5189c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319855571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1319855571
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.1384891287
Short name T240
Test name
Test status
Simulation time 484350994156 ps
CPU time 345.72 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:06:33 PM PDT 24
Peak memory 201884 kb
Host smart-1fd4b4ce-41f7-46d1-9a35-c675b96b4287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384891287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.1384891287
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2120940598
Short name T160
Test name
Test status
Simulation time 509532257631 ps
CPU time 1026.92 seconds
Started Jul 07 06:05:09 PM PDT 24
Finished Jul 07 06:22:16 PM PDT 24
Peak memory 201888 kb
Host smart-21c4d301-58ce-49b9-bc2c-9ce8051b5229
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120940598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2120940598
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4021654198
Short name T245
Test name
Test status
Simulation time 327548667391 ps
CPU time 378.45 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:06:50 PM PDT 24
Peak memory 201880 kb
Host smart-bd71a704-4b95-40af-8586-d503c5862226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021654198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4021654198
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.2542997716
Short name T38
Test name
Test status
Simulation time 411475221712 ps
CPU time 232.36 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:04:47 PM PDT 24
Peak memory 201828 kb
Host smart-d9160970-31a4-4d29-b89f-cccfb6848196
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542997716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.2542997716
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.3571152347
Short name T226
Test name
Test status
Simulation time 520311692832 ps
CPU time 1170.87 seconds
Started Jul 07 06:02:28 PM PDT 24
Finished Jul 07 06:21:59 PM PDT 24
Peak memory 201864 kb
Host smart-5cbc767b-e957-4e5f-bd73-1d44cb61e7b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571152347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gat
ing.3571152347
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.812333144
Short name T275
Test name
Test status
Simulation time 352178699252 ps
CPU time 782.47 seconds
Started Jul 07 06:05:04 PM PDT 24
Finished Jul 07 06:18:07 PM PDT 24
Peak memory 201832 kb
Host smart-e26df280-fa28-49bc-b6ed-3a85fe2f3615
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812333144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.812333144
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3520896686
Short name T70
Test name
Test status
Simulation time 502915447990 ps
CPU time 613.88 seconds
Started Jul 07 06:02:29 PM PDT 24
Finished Jul 07 06:12:44 PM PDT 24
Peak memory 201892 kb
Host smart-ca0bca47-2aa8-411b-9f36-9a40f93d6689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520896686 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3520896686
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.497481579
Short name T215
Test name
Test status
Simulation time 504585066988 ps
CPU time 1207.76 seconds
Started Jul 07 06:01:54 PM PDT 24
Finished Jul 07 06:22:03 PM PDT 24
Peak memory 201812 kb
Host smart-747da0ed-690d-4c92-a608-d0e3e5f8d830
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497481579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all.
497481579
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.4222932711
Short name T268
Test name
Test status
Simulation time 542234461053 ps
CPU time 1314.98 seconds
Started Jul 07 06:05:05 PM PDT 24
Finished Jul 07 06:27:01 PM PDT 24
Peak memory 201972 kb
Host smart-d94c13aa-84f9-409a-b6a7-fcf072688419
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222932711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.4222932711
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.1079962778
Short name T177
Test name
Test status
Simulation time 492666471306 ps
CPU time 920 seconds
Started Jul 07 06:01:01 PM PDT 24
Finished Jul 07 06:16:22 PM PDT 24
Peak memory 201896 kb
Host smart-4ce70bdf-c10f-4d4a-8217-69ded1df4c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079962778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.1079962778
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2335615000
Short name T255
Test name
Test status
Simulation time 555722010008 ps
CPU time 336.88 seconds
Started Jul 07 06:05:15 PM PDT 24
Finished Jul 07 06:10:53 PM PDT 24
Peak memory 201960 kb
Host smart-41e4c0d2-1a66-421e-882a-b58b82e92dfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335615000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2335615000
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3202201461
Short name T32
Test name
Test status
Simulation time 185894492700 ps
CPU time 215.68 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:04:34 PM PDT 24
Peak memory 211628 kb
Host smart-0119550f-2440-42b3-8a3d-345ea507332f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202201461 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3202201461
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.2039774796
Short name T250
Test name
Test status
Simulation time 358906335469 ps
CPU time 787.64 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:13:46 PM PDT 24
Peak memory 201948 kb
Host smart-23e9714e-ad2e-4eda-a9f3-d55142802331
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039774796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.2039774796
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.178414699
Short name T269
Test name
Test status
Simulation time 522384889235 ps
CPU time 1210.39 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:20:52 PM PDT 24
Peak memory 201968 kb
Host smart-d9d80fc9-f54d-4584-bd28-f79e5e17651f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178414699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.178414699
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2192170459
Short name T381
Test name
Test status
Simulation time 342353314 ps
CPU time 1.27 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:00:53 PM PDT 24
Peak memory 201928 kb
Host smart-61cdcf34-e2b0-4314-91d2-0d606cc1a3c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192170459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2192170459
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.1771069325
Short name T48
Test name
Test status
Simulation time 8686273985 ps
CPU time 22.66 seconds
Started Jul 07 05:59:51 PM PDT 24
Finished Jul 07 06:00:14 PM PDT 24
Peak memory 201852 kb
Host smart-421385d5-c2b2-486d-85c9-baca030461bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771069325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.1771069325
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.1504375287
Short name T34
Test name
Test status
Simulation time 25859393768 ps
CPU time 74.55 seconds
Started Jul 07 06:02:46 PM PDT 24
Finished Jul 07 06:04:01 PM PDT 24
Peak memory 210580 kb
Host smart-04c2a970-70d7-4667-9d15-1865504fd88f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504375287 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.1504375287
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.250476984
Short name T282
Test name
Test status
Simulation time 379267352805 ps
CPU time 893.93 seconds
Started Jul 07 06:01:49 PM PDT 24
Finished Jul 07 06:16:43 PM PDT 24
Peak memory 201972 kb
Host smart-63d7682d-12c9-4871-a360-4b1548f517d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250476984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_
wakeup.250476984
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.2931222778
Short name T81
Test name
Test status
Simulation time 163492871014 ps
CPU time 364.93 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:07:04 PM PDT 24
Peak memory 201912 kb
Host smart-625ee3e2-f23c-4edd-9036-f7852ed025ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931222778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.2931222778
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.2317523729
Short name T234
Test name
Test status
Simulation time 448209569482 ps
CPU time 1038.4 seconds
Started Jul 07 06:03:16 PM PDT 24
Finished Jul 07 06:20:35 PM PDT 24
Peak memory 201920 kb
Host smart-2c0d06ee-a5f7-4ff7-8346-6d5bb85277b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317523729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.2317523729
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.1771248921
Short name T263
Test name
Test status
Simulation time 520880567940 ps
CPU time 1109.56 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:20:01 PM PDT 24
Peak memory 201920 kb
Host smart-a2814ce9-e0ab-48e7-ad79-53bf3c3adf09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771248921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.1771248921
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.2191676391
Short name T229
Test name
Test status
Simulation time 182441754291 ps
CPU time 104.47 seconds
Started Jul 07 06:04:55 PM PDT 24
Finished Jul 07 06:06:40 PM PDT 24
Peak memory 202004 kb
Host smart-fd498800-62fb-4eda-b435-bcaf99aea7fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191676391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.2191676391
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2171425891
Short name T176
Test name
Test status
Simulation time 499816729731 ps
CPU time 308.8 seconds
Started Jul 07 06:03:26 PM PDT 24
Finished Jul 07 06:08:35 PM PDT 24
Peak memory 201908 kb
Host smart-87784642-a006-4f1f-b1ee-9944c71cd865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171425891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2171425891
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1315704101
Short name T202
Test name
Test status
Simulation time 295914335399 ps
CPU time 992.93 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:17:33 PM PDT 24
Peak memory 202164 kb
Host smart-f43ddf65-b609-46cd-ba71-7f164171697d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315704101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1315704101
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.622478065
Short name T253
Test name
Test status
Simulation time 169328205800 ps
CPU time 99.76 seconds
Started Jul 07 06:02:18 PM PDT 24
Finished Jul 07 06:03:58 PM PDT 24
Peak memory 201936 kb
Host smart-ed7c947b-2d04-48af-a3be-68ae2e4fac50
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622478065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_
wakeup.622478065
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.3649412131
Short name T16
Test name
Test status
Simulation time 478556233907 ps
CPU time 225.95 seconds
Started Jul 07 06:03:29 PM PDT 24
Finished Jul 07 06:07:15 PM PDT 24
Peak memory 210536 kb
Host smart-ae0b20e3-f91e-45dc-a9eb-f92ad8899169
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649412131 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.3649412131
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.2509274679
Short name T21
Test name
Test status
Simulation time 98593829350 ps
CPU time 185.65 seconds
Started Jul 07 06:04:08 PM PDT 24
Finished Jul 07 06:07:14 PM PDT 24
Peak memory 218544 kb
Host smart-d5962062-8768-49c3-b96a-36c1a3de7d36
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509274679 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.2509274679
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.3839108597
Short name T129
Test name
Test status
Simulation time 2715453681 ps
CPU time 1.56 seconds
Started Jul 07 05:59:30 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201616 kb
Host smart-9eef17cc-99d7-46d0-83a4-48e174be1cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839108597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.3839108597
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.350402456
Short name T327
Test name
Test status
Simulation time 181939400005 ps
CPU time 392.97 seconds
Started Jul 07 06:02:18 PM PDT 24
Finished Jul 07 06:08:52 PM PDT 24
Peak memory 201904 kb
Host smart-a7ee26b0-763b-4936-ba13-a35b52e1db1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350402456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.350402456
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.1612519276
Short name T241
Test name
Test status
Simulation time 342638303335 ps
CPU time 770.68 seconds
Started Jul 07 06:04:07 PM PDT 24
Finished Jul 07 06:16:58 PM PDT 24
Peak memory 201916 kb
Host smart-898c4528-9b4e-4dbf-9263-fd333a2f6f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612519276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.1612519276
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.3032997128
Short name T227
Test name
Test status
Simulation time 507316271380 ps
CPU time 836.6 seconds
Started Jul 07 06:04:32 PM PDT 24
Finished Jul 07 06:18:29 PM PDT 24
Peak memory 201892 kb
Host smart-44b0c3f2-c8a9-4c9b-bda8-6cc38cf83d8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032997128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gat
ing.3032997128
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.1565843073
Short name T287
Test name
Test status
Simulation time 291148829911 ps
CPU time 117.99 seconds
Started Jul 07 06:05:25 PM PDT 24
Finished Jul 07 06:07:24 PM PDT 24
Peak memory 210536 kb
Host smart-b9dc21f7-a07e-4114-b6b9-b2dd60049876
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565843073 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.1565843073
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.802545940
Short name T208
Test name
Test status
Simulation time 515030534290 ps
CPU time 1451.48 seconds
Started Jul 07 06:01:13 PM PDT 24
Finished Jul 07 06:25:25 PM PDT 24
Peak memory 202208 kb
Host smart-8eb30b04-dfb4-4994-9729-df76ca593cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802545940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all.
802545940
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1572673279
Short name T266
Test name
Test status
Simulation time 340810007739 ps
CPU time 181.57 seconds
Started Jul 07 06:02:51 PM PDT 24
Finished Jul 07 06:05:53 PM PDT 24
Peak memory 201916 kb
Host smart-d8310e7a-ac37-4aef-8b43-c68b595c8677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572673279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1572673279
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.588621160
Short name T284
Test name
Test status
Simulation time 533112566272 ps
CPU time 614.6 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:10:59 PM PDT 24
Peak memory 201912 kb
Host smart-f9708613-b5dd-4f9b-a39f-d24e7c978cb5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588621160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gatin
g.588621160
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.736938678
Short name T205
Test name
Test status
Simulation time 126089046290 ps
CPU time 416.52 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:07:57 PM PDT 24
Peak memory 202048 kb
Host smart-f8f6ceac-4317-4dec-bb95-7000c7df4577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736938678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.736938678
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2139241992
Short name T252
Test name
Test status
Simulation time 356706226530 ps
CPU time 779.52 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:13:57 PM PDT 24
Peak memory 201948 kb
Host smart-10f9f8eb-d233-4ac8-9c6d-18b4c8b66d26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139241992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2139241992
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.501137543
Short name T89
Test name
Test status
Simulation time 97923976918 ps
CPU time 190.79 seconds
Started Jul 07 06:02:57 PM PDT 24
Finished Jul 07 06:06:08 PM PDT 24
Peak memory 218600 kb
Host smart-1e3051a8-8d16-4e18-b1de-b90828fe63f6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501137543 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.501137543
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2729110932
Short name T299
Test name
Test status
Simulation time 163494702740 ps
CPU time 70.52 seconds
Started Jul 07 06:03:13 PM PDT 24
Finished Jul 07 06:04:23 PM PDT 24
Peak memory 201932 kb
Host smart-8a8ea840-a4f7-4119-a35d-8e5e33a2a2bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729110932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2729110932
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.317666037
Short name T216
Test name
Test status
Simulation time 493076344571 ps
CPU time 1035.57 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:17:58 PM PDT 24
Peak memory 201888 kb
Host smart-0fb446a6-40de-4af2-b943-7c66cfc64619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317666037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.317666037
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.1280633230
Short name T213
Test name
Test status
Simulation time 84505865780 ps
CPU time 421.57 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:07:40 PM PDT 24
Peak memory 202268 kb
Host smart-44381bd4-c7ad-420d-a604-ff5a7015697c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280633230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.1280633230
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.2192342921
Short name T196
Test name
Test status
Simulation time 485169808324 ps
CPU time 263.82 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:05:12 PM PDT 24
Peak memory 201872 kb
Host smart-f9584c7c-3a68-4b49-b5cb-6ee3e075751c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192342921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.2192342921
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.1248506700
Short name T322
Test name
Test status
Simulation time 331550850559 ps
CPU time 202.13 seconds
Started Jul 07 06:02:13 PM PDT 24
Finished Jul 07 06:05:36 PM PDT 24
Peak memory 201900 kb
Host smart-6fdc4fd7-54d5-4a29-aa52-8a5d5df91192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248506700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.1248506700
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.4003057731
Short name T295
Test name
Test status
Simulation time 499173005394 ps
CPU time 1142.08 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:21:21 PM PDT 24
Peak memory 201836 kb
Host smart-74c9db91-b157-4cbb-b9f9-02650dbb413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003057731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.4003057731
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.640763558
Short name T336
Test name
Test status
Simulation time 172293201732 ps
CPU time 550.79 seconds
Started Jul 07 06:05:08 PM PDT 24
Finished Jul 07 06:14:20 PM PDT 24
Peak memory 210452 kb
Host smart-17e1d900-a613-42bd-9f2a-e059e9025209
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640763558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all.
640763558
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.933655450
Short name T18
Test name
Test status
Simulation time 256211089838 ps
CPU time 195.87 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:04:05 PM PDT 24
Peak memory 210232 kb
Host smart-a8e94de9-469b-417c-9f7f-1b02f2bfcde8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933655450 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.933655450
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.886162128
Short name T237
Test name
Test status
Simulation time 524563185595 ps
CPU time 215.19 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:04:36 PM PDT 24
Peak memory 201924 kb
Host smart-f61c416c-1f9a-4033-8175-9f68cb2b4cd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886162128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_
wakeup.886162128
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1877257065
Short name T96
Test name
Test status
Simulation time 88990996900 ps
CPU time 477.1 seconds
Started Jul 07 06:01:46 PM PDT 24
Finished Jul 07 06:09:44 PM PDT 24
Peak memory 202204 kb
Host smart-f95f6bbe-4ba9-4ed8-a780-5ccb7f0ebf42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877257065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1877257065
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3301590282
Short name T204
Test name
Test status
Simulation time 550638151797 ps
CPU time 172.94 seconds
Started Jul 07 06:02:27 PM PDT 24
Finished Jul 07 06:05:20 PM PDT 24
Peak memory 218740 kb
Host smart-dd7d4b36-d6a1-4d51-9e19-1acc50ef7065
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301590282 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3301590282
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.399713292
Short name T335
Test name
Test status
Simulation time 4470353760 ps
CPU time 4.39 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201748 kb
Host smart-427045a4-86be-4671-b3bd-4e98772a03c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399713292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.399713292
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.2653197887
Short name T848
Test name
Test status
Simulation time 4774697536 ps
CPU time 4.12 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:35 PM PDT 24
Peak memory 201872 kb
Host smart-3b0d9dd2-3c0d-4e91-81d2-91b5e5fe2956
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653197887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.2653197887
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3334990277
Short name T228
Test name
Test status
Simulation time 34567235039 ps
CPU time 70.84 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:01:43 PM PDT 24
Peak memory 210216 kb
Host smart-80d22028-6b6b-428d-af74-1de015ab3bd1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334990277 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3334990277
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.2255312273
Short name T249
Test name
Test status
Simulation time 542036131788 ps
CPU time 1264.61 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:21:54 PM PDT 24
Peak memory 201972 kb
Host smart-0754a852-00a9-4c9d-ac30-6bc2f543d91d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255312273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.2255312273
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1096823259
Short name T341
Test name
Test status
Simulation time 121608543455 ps
CPU time 421.47 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:07:59 PM PDT 24
Peak memory 202268 kb
Host smart-e0eafcca-46ec-4327-b6bd-b476264c6a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1096823259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1096823259
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.3278422599
Short name T316
Test name
Test status
Simulation time 331910816858 ps
CPU time 189.66 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:04:07 PM PDT 24
Peak memory 201796 kb
Host smart-7a946e2d-db8a-430c-bac2-86e6b463d6f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278422599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.3278422599
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.44907286
Short name T328
Test name
Test status
Simulation time 323770327915 ps
CPU time 726.29 seconds
Started Jul 07 06:01:01 PM PDT 24
Finished Jul 07 06:13:07 PM PDT 24
Peak memory 201856 kb
Host smart-82afc766-9067-4eb8-9fcf-5f71c74ec4a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44907286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.44907286
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.4258571732
Short name T211
Test name
Test status
Simulation time 74506563510 ps
CPU time 312.32 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:06:11 PM PDT 24
Peak memory 202232 kb
Host smart-a4a17d0a-b403-4c19-bb1c-21fc6810567d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258571732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.4258571732
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.1815489053
Short name T276
Test name
Test status
Simulation time 393954416137 ps
CPU time 308.58 seconds
Started Jul 07 06:01:05 PM PDT 24
Finished Jul 07 06:06:14 PM PDT 24
Peak memory 201968 kb
Host smart-d91fe26d-688b-49f5-b1f3-46d4349d4883
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815489053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters
_wakeup.1815489053
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2152691987
Short name T320
Test name
Test status
Simulation time 485090400804 ps
CPU time 1174.33 seconds
Started Jul 07 06:00:27 PM PDT 24
Finished Jul 07 06:20:02 PM PDT 24
Peak memory 201888 kb
Host smart-3dc6d612-de1d-4111-bf49-03f8e7c7d1d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152691987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2152691987
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2128355395
Short name T294
Test name
Test status
Simulation time 328302610750 ps
CPU time 193.38 seconds
Started Jul 07 06:01:16 PM PDT 24
Finished Jul 07 06:04:30 PM PDT 24
Peak memory 201964 kb
Host smart-ad1ea152-833f-472a-8c28-ff5bd73c10bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128355395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2128355395
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3638328024
Short name T259
Test name
Test status
Simulation time 525002633326 ps
CPU time 961.96 seconds
Started Jul 07 06:01:36 PM PDT 24
Finished Jul 07 06:17:39 PM PDT 24
Peak memory 202252 kb
Host smart-47f26ae2-4cda-4d68-8401-3614ee2ea7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638328024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3638328024
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1207717906
Short name T254
Test name
Test status
Simulation time 494405058890 ps
CPU time 1112.94 seconds
Started Jul 07 06:01:44 PM PDT 24
Finished Jul 07 06:20:17 PM PDT 24
Peak memory 201948 kb
Host smart-8b9f9f34-f797-429a-bfaf-f2be087ae812
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207717906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1207717906
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3373394360
Short name T209
Test name
Test status
Simulation time 74617323394 ps
CPU time 290.27 seconds
Started Jul 07 06:02:08 PM PDT 24
Finished Jul 07 06:06:59 PM PDT 24
Peak memory 202268 kb
Host smart-b06358fa-71b4-4742-a311-1d24be6a886e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373394360 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3373394360
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.3167894810
Short name T340
Test name
Test status
Simulation time 183238419762 ps
CPU time 464.59 seconds
Started Jul 07 06:02:21 PM PDT 24
Finished Jul 07 06:10:06 PM PDT 24
Peak memory 210500 kb
Host smart-98c2f046-2dea-4a00-bead-551f60377262
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167894810 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.3167894810
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.4290907556
Short name T251
Test name
Test status
Simulation time 455579750136 ps
CPU time 966.94 seconds
Started Jul 07 06:02:52 PM PDT 24
Finished Jul 07 06:18:59 PM PDT 24
Peak memory 201892 kb
Host smart-d3566241-84af-4513-a562-cdba2eb8584f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290907556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.4290907556
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1571420117
Short name T207
Test name
Test status
Simulation time 343285854560 ps
CPU time 1075.48 seconds
Started Jul 07 06:04:27 PM PDT 24
Finished Jul 07 06:22:23 PM PDT 24
Peak memory 210408 kb
Host smart-c71f86ab-9085-4b69-98af-cb81e71df7eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571420117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1571420117
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.92189363
Short name T303
Test name
Test status
Simulation time 352142292363 ps
CPU time 398.24 seconds
Started Jul 07 06:04:47 PM PDT 24
Finished Jul 07 06:11:26 PM PDT 24
Peak memory 201896 kb
Host smart-e3b1ebb6-19de-4bcb-be5f-186c2d47aadb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92189363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_w
akeup.92189363
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1158843062
Short name T146
Test name
Test status
Simulation time 580580870778 ps
CPU time 258.62 seconds
Started Jul 07 06:04:45 PM PDT 24
Finished Jul 07 06:09:05 PM PDT 24
Peak memory 201896 kb
Host smart-1bfb6b79-11a1-4386-9d44-ce69530f8e36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158843062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1158843062
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.4258382235
Short name T13
Test name
Test status
Simulation time 123998144297 ps
CPU time 128.6 seconds
Started Jul 07 06:05:08 PM PDT 24
Finished Jul 07 06:07:17 PM PDT 24
Peak memory 210440 kb
Host smart-24cb41cb-16d9-4c3d-89ff-564e4652c596
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258382235 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.4258382235
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.545429454
Short name T298
Test name
Test status
Simulation time 490968287578 ps
CPU time 201.77 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:04:10 PM PDT 24
Peak memory 201880 kb
Host smart-23262976-0978-49fc-8d6b-16b265fc062b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545429454 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.545429454
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1941261493
Short name T118
Test name
Test status
Simulation time 800272508 ps
CPU time 3.92 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:31 PM PDT 24
Peak memory 201660 kb
Host smart-0f4b43ff-49b1-4aef-a737-a0974f8438a1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941261493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1941261493
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.3240249934
Short name T808
Test name
Test status
Simulation time 827229651 ps
CPU time 1.14 seconds
Started Jul 07 05:59:28 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 201400 kb
Host smart-c5015eff-66b0-4c91-94eb-4ba854636ed8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240249934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.3240249934
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.215441472
Short name T853
Test name
Test status
Simulation time 579296951 ps
CPU time 1.19 seconds
Started Jul 07 05:59:32 PM PDT 24
Finished Jul 07 05:59:33 PM PDT 24
Peak memory 201512 kb
Host smart-fe2d5a24-9cd4-4044-bb45-69874db63ee6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215441472 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.215441472
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.2307907667
Short name T124
Test name
Test status
Simulation time 354397038 ps
CPU time 0.94 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201536 kb
Host smart-77c7a84e-2a6d-47ea-84b7-c4863455bb19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307907667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.2307907667
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.900229434
Short name T871
Test name
Test status
Simulation time 547788107 ps
CPU time 0.92 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 201364 kb
Host smart-684cb784-5ca8-4168-a303-04b52530b77a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900229434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.900229434
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.197822467
Short name T880
Test name
Test status
Simulation time 3580670259 ps
CPU time 2.99 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 201816 kb
Host smart-657caa90-b5b1-4afd-9691-2c721b03407b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197822467 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.197822467
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.1944325628
Short name T896
Test name
Test status
Simulation time 503951360 ps
CPU time 3.63 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:30 PM PDT 24
Peak memory 211032 kb
Host smart-95fa6fde-ec3a-4b5c-8e81-8434e72dbeb5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944325628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.1944325628
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4072438854
Short name T873
Test name
Test status
Simulation time 687666911 ps
CPU time 2.87 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201652 kb
Host smart-b783225d-1747-46f0-a366-e91db8975cdc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072438854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4072438854
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.304634011
Short name T879
Test name
Test status
Simulation time 51789600421 ps
CPU time 35.44 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 06:00:06 PM PDT 24
Peak memory 201888 kb
Host smart-13415f6e-e77c-425a-a956-58352a8ece75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304634011 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_b
ash.304634011
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3159228702
Short name T916
Test name
Test status
Simulation time 660168335 ps
CPU time 1.5 seconds
Started Jul 07 05:59:27 PM PDT 24
Finished Jul 07 05:59:28 PM PDT 24
Peak memory 201492 kb
Host smart-3bc0c733-7e7f-4474-a888-a6a0f6aec43d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159228702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3159228702
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.2784170013
Short name T909
Test name
Test status
Simulation time 350946191 ps
CPU time 1.02 seconds
Started Jul 07 05:59:33 PM PDT 24
Finished Jul 07 05:59:34 PM PDT 24
Peak memory 201560 kb
Host smart-2b86190c-8cc5-41ab-af3a-cc575f725212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784170013 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.2784170013
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.1254110729
Short name T894
Test name
Test status
Simulation time 425828292 ps
CPU time 1.05 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201484 kb
Host smart-57732f9c-f76a-4abc-9970-c679da2ae298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254110729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.1254110729
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.4246660410
Short name T839
Test name
Test status
Simulation time 459095059 ps
CPU time 1.08 seconds
Started Jul 07 05:59:25 PM PDT 24
Finished Jul 07 05:59:27 PM PDT 24
Peak memory 201408 kb
Host smart-3f6ea802-b7f2-4a68-a039-4b90d7f72bca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246660410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.4246660410
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.2655898684
Short name T855
Test name
Test status
Simulation time 537456360 ps
CPU time 3.52 seconds
Started Jul 07 05:59:30 PM PDT 24
Finished Jul 07 05:59:34 PM PDT 24
Peak memory 217648 kb
Host smart-230896f5-2803-4b3b-b280-51d22abbf27e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655898684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.2655898684
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.371958467
Short name T64
Test name
Test status
Simulation time 375528325 ps
CPU time 1.37 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 201560 kb
Host smart-4e477d7d-76fd-4f2c-a541-ee4555b94f3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371958467 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.371958467
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.830252655
Short name T868
Test name
Test status
Simulation time 394874479 ps
CPU time 1.32 seconds
Started Jul 07 05:59:46 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201520 kb
Host smart-dab27aa4-8105-4120-b8fd-58b2da37803a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830252655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.830252655
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2399516091
Short name T807
Test name
Test status
Simulation time 403169269 ps
CPU time 1.12 seconds
Started Jul 07 05:59:42 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201400 kb
Host smart-2bf53726-4e87-46c6-925f-7b9b76ee72b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399516091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2399516091
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.3547580595
Short name T893
Test name
Test status
Simulation time 2364251934 ps
CPU time 5.91 seconds
Started Jul 07 05:59:44 PM PDT 24
Finished Jul 07 05:59:50 PM PDT 24
Peak memory 201632 kb
Host smart-843d3aa2-c977-48f5-b27b-859584033aa4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547580595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.3547580595
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2263656154
Short name T824
Test name
Test status
Simulation time 295799337 ps
CPU time 1.84 seconds
Started Jul 07 05:59:42 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201660 kb
Host smart-23c7a46a-9c1d-4622-9258-bbd14233d1eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263656154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2263656154
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3390311482
Short name T912
Test name
Test status
Simulation time 8388717845 ps
CPU time 23.72 seconds
Started Jul 07 05:59:39 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 201840 kb
Host smart-4216acf2-46c6-489e-bb19-bea430b4d6ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390311482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3390311482
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.3767841817
Short name T78
Test name
Test status
Simulation time 403157317 ps
CPU time 1.88 seconds
Started Jul 07 05:59:44 PM PDT 24
Finished Jul 07 05:59:46 PM PDT 24
Peak memory 201552 kb
Host smart-cb01f538-96f1-46c0-a7fc-a75350e6ace4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767841817 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.3767841817
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.2258607028
Short name T863
Test name
Test status
Simulation time 360208380 ps
CPU time 1.14 seconds
Started Jul 07 05:59:45 PM PDT 24
Finished Jul 07 05:59:47 PM PDT 24
Peak memory 201512 kb
Host smart-5dd1d519-fa87-4884-a7ca-0e0c7977cba5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258607028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.2258607028
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.2061524724
Short name T907
Test name
Test status
Simulation time 349433361 ps
CPU time 1.54 seconds
Started Jul 07 05:59:42 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201440 kb
Host smart-5253d49a-ea34-4b06-a3f4-2e205dca453a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061524724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.2061524724
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.3872564710
Short name T821
Test name
Test status
Simulation time 5104469785 ps
CPU time 3.98 seconds
Started Jul 07 05:59:48 PM PDT 24
Finished Jul 07 05:59:52 PM PDT 24
Peak memory 201756 kb
Host smart-f8688220-3426-43f9-9925-6b5200ae4b5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872564710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.3872564710
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3923942564
Short name T50
Test name
Test status
Simulation time 8388767588 ps
CPU time 7.95 seconds
Started Jul 07 05:59:45 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 201792 kb
Host smart-aabb8975-89f7-4efd-96df-dfde7a97e124
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923942564 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3923942564
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.4014242667
Short name T820
Test name
Test status
Simulation time 831531111 ps
CPU time 0.89 seconds
Started Jul 07 05:59:42 PM PDT 24
Finished Jul 07 05:59:43 PM PDT 24
Peak memory 201488 kb
Host smart-29222847-669e-41ef-bfc2-8a22c3ed5ecc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014242667 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.4014242667
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.3874124063
Short name T874
Test name
Test status
Simulation time 336593289 ps
CPU time 0.93 seconds
Started Jul 07 05:59:43 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201504 kb
Host smart-d2f94f6e-2099-488f-a5b2-09986e42330b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874124063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.3874124063
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.341474422
Short name T869
Test name
Test status
Simulation time 518899508 ps
CPU time 0.96 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 201372 kb
Host smart-e5a06e7c-b2a5-4875-ae36-83e9471fa539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341474422 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.341474422
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.707694510
Short name T822
Test name
Test status
Simulation time 2132601290 ps
CPU time 3.13 seconds
Started Jul 07 05:59:46 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 201420 kb
Host smart-dc3da835-b6b9-4049-b0ba-6c82ead7c31a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707694510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_c
trl_same_csr_outstanding.707694510
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2321888160
Short name T828
Test name
Test status
Simulation time 497619168 ps
CPU time 2.1 seconds
Started Jul 07 05:59:49 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201764 kb
Host smart-f8f0d6a5-a6b8-4980-9b5c-ed1fed4c0ca2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321888160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2321888160
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.356128145
Short name T831
Test name
Test status
Simulation time 5001760942 ps
CPU time 2.23 seconds
Started Jul 07 05:59:46 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201836 kb
Host smart-097427c2-ec1e-4db1-babd-e27feee9e9a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356128145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_in
tg_err.356128145
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.495511384
Short name T878
Test name
Test status
Simulation time 451192657 ps
CPU time 1.11 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201552 kb
Host smart-d0c7be2e-252d-4885-b13d-cc3875a244ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=495511384 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.495511384
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.1196004965
Short name T120
Test name
Test status
Simulation time 341892103 ps
CPU time 0.9 seconds
Started Jul 07 05:59:46 PM PDT 24
Finished Jul 07 05:59:47 PM PDT 24
Peak memory 201520 kb
Host smart-f2da0bf6-e70e-4c3f-a5f1-9a648e21fccc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196004965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.1196004965
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.2572137319
Short name T802
Test name
Test status
Simulation time 308231641 ps
CPU time 1.04 seconds
Started Jul 07 05:59:49 PM PDT 24
Finished Jul 07 05:59:50 PM PDT 24
Peak memory 201440 kb
Host smart-0835a786-91ed-4539-8e6c-ea92aedc08f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572137319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.2572137319
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.3869064034
Short name T904
Test name
Test status
Simulation time 4608270822 ps
CPU time 3.13 seconds
Started Jul 07 05:59:48 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201856 kb
Host smart-7dde7fce-6ce1-4325-9da7-bf92642bb803
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869064034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.3869064034
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.1774362302
Short name T63
Test name
Test status
Simulation time 611728898 ps
CPU time 1.78 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 201760 kb
Host smart-2d2fe228-88ff-4b8e-a3cb-d88e61c5038e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774362302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.1774362302
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3029705009
Short name T805
Test name
Test status
Simulation time 838019605 ps
CPU time 1.13 seconds
Started Jul 07 05:59:51 PM PDT 24
Finished Jul 07 05:59:53 PM PDT 24
Peak memory 201540 kb
Host smart-d217ca21-20cc-43b5-acf5-54d77888a1c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029705009 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3029705009
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.2390012263
Short name T861
Test name
Test status
Simulation time 502147981 ps
CPU time 1.91 seconds
Started Jul 07 05:59:49 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201476 kb
Host smart-7e4bb596-ce47-4ff5-b02b-9ccde1ecb3d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390012263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.2390012263
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.1129437215
Short name T841
Test name
Test status
Simulation time 473573975 ps
CPU time 1.8 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 201408 kb
Host smart-dfc93ab2-1aa0-4b81-9f37-28dde96ba27c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129437215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.1129437215
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.1937771270
Short name T838
Test name
Test status
Simulation time 4397225989 ps
CPU time 2.04 seconds
Started Jul 07 05:59:46 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201836 kb
Host smart-9d51a06e-3029-403a-8666-dc24117007a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937771270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.1937771270
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.2971905482
Short name T835
Test name
Test status
Simulation time 607644241 ps
CPU time 2.23 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 202084 kb
Host smart-163bdf47-f78e-4f1e-aece-bdd276f74b04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971905482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.2971905482
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.3095226980
Short name T827
Test name
Test status
Simulation time 5070036422 ps
CPU time 2.71 seconds
Started Jul 07 05:59:51 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 201884 kb
Host smart-9a661702-eeff-4966-ad72-fb770faf38a5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095226980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.3095226980
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.4003160164
Short name T902
Test name
Test status
Simulation time 585300778 ps
CPU time 1.31 seconds
Started Jul 07 05:59:49 PM PDT 24
Finished Jul 07 05:59:50 PM PDT 24
Peak memory 201580 kb
Host smart-260a30ab-0ca3-4832-91c9-5e8f43a3c845
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003160164 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.4003160164
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.3372246829
Short name T134
Test name
Test status
Simulation time 435838380 ps
CPU time 1.03 seconds
Started Jul 07 05:59:46 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201764 kb
Host smart-0168ca85-3144-40df-8552-44b14509bd74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372246829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.3372246829
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.2563159205
Short name T847
Test name
Test status
Simulation time 435146621 ps
CPU time 1.76 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:49 PM PDT 24
Peak memory 201364 kb
Host smart-acbb6dcd-d531-4307-8b71-2a2f8e8d14cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563159205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.2563159205
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.1452102833
Short name T815
Test name
Test status
Simulation time 4948616525 ps
CPU time 10.96 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 05:59:59 PM PDT 24
Peak memory 201876 kb
Host smart-79d29ea8-7136-4b9c-9c4b-fd344423a926
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452102833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.1452102833
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3039972959
Short name T814
Test name
Test status
Simulation time 581951651 ps
CPU time 2.72 seconds
Started Jul 07 05:59:51 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 217620 kb
Host smart-26ad9109-fac7-4a87-9691-80868e8476fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039972959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3039972959
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3657783099
Short name T884
Test name
Test status
Simulation time 4427784668 ps
CPU time 12.75 seconds
Started Jul 07 05:59:47 PM PDT 24
Finished Jul 07 06:00:00 PM PDT 24
Peak memory 201844 kb
Host smart-1bc81947-cf5e-4ac8-b492-deb1ab55431b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657783099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3657783099
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.454794892
Short name T844
Test name
Test status
Simulation time 362103014 ps
CPU time 1.28 seconds
Started Jul 07 05:59:54 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 201580 kb
Host smart-0d0b4a44-8614-49e2-be16-1c8b9c0dd954
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454794892 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.454794892
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.3495641277
Short name T834
Test name
Test status
Simulation time 525529759 ps
CPU time 1.06 seconds
Started Jul 07 05:59:52 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 201500 kb
Host smart-54e0acb2-630d-46bb-a196-8577da95c265
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495641277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.3495641277
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.2083650091
Short name T864
Test name
Test status
Simulation time 396698483 ps
CPU time 0.82 seconds
Started Jul 07 05:59:50 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201428 kb
Host smart-ae19aae6-df1a-4b94-916c-4bd416fdc2b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083650091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.2083650091
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.1331865669
Short name T856
Test name
Test status
Simulation time 4483000857 ps
CPU time 10.43 seconds
Started Jul 07 05:59:52 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 201820 kb
Host smart-836a82df-a6b5-4d09-9ce2-27e081e9456a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331865669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.1331865669
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.1631826801
Short name T843
Test name
Test status
Simulation time 438530580 ps
CPU time 1.93 seconds
Started Jul 07 05:59:49 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 217616 kb
Host smart-a16d5f79-1ee0-4871-9189-f267472ea28a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631826801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.1631826801
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.743003795
Short name T62
Test name
Test status
Simulation time 8407836068 ps
CPU time 20.04 seconds
Started Jul 07 05:59:48 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 201724 kb
Host smart-80afeb2a-b44d-49ab-a95a-1400ce7b27b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743003795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.743003795
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.2864497507
Short name T826
Test name
Test status
Simulation time 512580907 ps
CPU time 1.52 seconds
Started Jul 07 05:59:50 PM PDT 24
Finished Jul 07 05:59:52 PM PDT 24
Peak memory 201568 kb
Host smart-6db0c9aa-045d-44b1-914d-0a1ebd07a0b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864497507 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.2864497507
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.459673484
Short name T121
Test name
Test status
Simulation time 437181948 ps
CPU time 1.04 seconds
Started Jul 07 05:59:50 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201488 kb
Host smart-992098b7-2dee-4e05-911e-357f215d058e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459673484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.459673484
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.396916989
Short name T905
Test name
Test status
Simulation time 438637946 ps
CPU time 0.9 seconds
Started Jul 07 05:59:50 PM PDT 24
Finished Jul 07 05:59:51 PM PDT 24
Peak memory 201436 kb
Host smart-cd0c9444-0f1c-4431-8e62-72113114af08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396916989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.396916989
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.2214786904
Short name T44
Test name
Test status
Simulation time 2423254006 ps
CPU time 1.74 seconds
Started Jul 07 05:59:53 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 201624 kb
Host smart-e042fd86-0616-4706-bbed-8681a250fff9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214786904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.2214786904
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3113715382
Short name T829
Test name
Test status
Simulation time 443451317 ps
CPU time 3.29 seconds
Started Jul 07 05:59:51 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 209952 kb
Host smart-69403a2d-a077-4b16-a050-c261e602398b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113715382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3113715382
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1041307735
Short name T334
Test name
Test status
Simulation time 4884977044 ps
CPU time 3.53 seconds
Started Jul 07 05:59:53 PM PDT 24
Finished Jul 07 05:59:57 PM PDT 24
Peak memory 201708 kb
Host smart-d2fbf0b1-665c-40bd-825d-12d12e11fd80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041307735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1041307735
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.3014083852
Short name T877
Test name
Test status
Simulation time 343490188 ps
CPU time 1.31 seconds
Started Jul 07 05:59:55 PM PDT 24
Finished Jul 07 05:59:56 PM PDT 24
Peak memory 201536 kb
Host smart-3db9700a-69ca-4965-a5ef-942f33c8eae8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014083852 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.3014083852
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.3256491937
Short name T132
Test name
Test status
Simulation time 493531612 ps
CPU time 1.39 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 201480 kb
Host smart-480fec14-eaff-4ba5-ad0c-a92d9e96ef07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256491937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.3256491937
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.4167179778
Short name T792
Test name
Test status
Simulation time 382471183 ps
CPU time 1.58 seconds
Started Jul 07 05:59:55 PM PDT 24
Finished Jul 07 05:59:57 PM PDT 24
Peak memory 201324 kb
Host smart-bc2ece2d-2c13-4cf1-8c84-5fd006fccd96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167179778 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.4167179778
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1740714366
Short name T130
Test name
Test status
Simulation time 2527007201 ps
CPU time 2.55 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:11 PM PDT 24
Peak memory 201604 kb
Host smart-cd3539f7-efdb-403e-ae15-bedd0c4d638e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740714366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1740714366
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1117712118
Short name T898
Test name
Test status
Simulation time 584888320 ps
CPU time 2.25 seconds
Started Jul 07 05:59:53 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 201724 kb
Host smart-017ae9db-6a5e-480c-a709-a8ef03ab2cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117712118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1117712118
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.547748044
Short name T816
Test name
Test status
Simulation time 4566007512 ps
CPU time 4.27 seconds
Started Jul 07 05:59:51 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 201876 kb
Host smart-a5b6aacc-98ca-4216-bfa8-56dd8193d7fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547748044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_in
tg_err.547748044
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.3743205544
Short name T806
Test name
Test status
Simulation time 457610071 ps
CPU time 1.27 seconds
Started Jul 07 05:59:56 PM PDT 24
Finished Jul 07 05:59:57 PM PDT 24
Peak memory 201560 kb
Host smart-b335b5b3-afd7-47ce-9e5a-3003c1d822e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743205544 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.3743205544
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2067212398
Short name T825
Test name
Test status
Simulation time 518134642 ps
CPU time 1.53 seconds
Started Jul 07 05:59:56 PM PDT 24
Finished Jul 07 05:59:58 PM PDT 24
Peak memory 201504 kb
Host smart-8dc9113d-ac0a-40bb-9798-ba6b523f2df6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067212398 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2067212398
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2292070547
Short name T860
Test name
Test status
Simulation time 361723216 ps
CPU time 0.75 seconds
Started Jul 07 05:59:53 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 201416 kb
Host smart-701c2d46-e18d-46b2-95d0-d31888152095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292070547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2292070547
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.809613015
Short name T882
Test name
Test status
Simulation time 2407054500 ps
CPU time 2.6 seconds
Started Jul 07 05:59:56 PM PDT 24
Finished Jul 07 05:59:59 PM PDT 24
Peak memory 201664 kb
Host smart-2ab3ad52-b742-4311-be14-e31aa94e1fa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809613015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_c
trl_same_csr_outstanding.809613015
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.691115396
Short name T849
Test name
Test status
Simulation time 456684403 ps
CPU time 1.95 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 201716 kb
Host smart-6e2cd318-df76-46ef-adea-86e50bdbac84
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691115396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.691115396
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.987321411
Short name T915
Test name
Test status
Simulation time 8426785640 ps
CPU time 12.46 seconds
Started Jul 07 05:59:55 PM PDT 24
Finished Jul 07 06:00:08 PM PDT 24
Peak memory 201784 kb
Host smart-37186a47-c333-4d24-9e01-6bae6dcb20e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987321411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.987321411
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3899825836
Short name T126
Test name
Test status
Simulation time 938794440 ps
CPU time 2.64 seconds
Started Jul 07 05:59:32 PM PDT 24
Finished Jul 07 05:59:35 PM PDT 24
Peak memory 201760 kb
Host smart-52ef4837-869a-4641-96f9-444bce302800
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899825836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3899825836
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1520766348
Short name T846
Test name
Test status
Simulation time 31284069512 ps
CPU time 22.3 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:53 PM PDT 24
Peak memory 201780 kb
Host smart-c0ffdd4b-51d9-440c-8693-edb3c72f75ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520766348 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1520766348
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.38987297
Short name T818
Test name
Test status
Simulation time 697607291 ps
CPU time 1.41 seconds
Started Jul 07 05:59:34 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 201492 kb
Host smart-9f2fde74-56e8-4f38-9c4c-bb1488daf356
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38987297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_res
et.38987297
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.882600850
Short name T804
Test name
Test status
Simulation time 567575769 ps
CPU time 2.37 seconds
Started Jul 07 05:59:34 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201568 kb
Host smart-d56cbfdc-71ea-4707-af24-ef3d48f4b023
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882600850 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.882600850
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1468928969
Short name T117
Test name
Test status
Simulation time 495163830 ps
CPU time 1.01 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201476 kb
Host smart-659c5b0d-f4b4-411a-8916-d09be3a4be50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468928969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1468928969
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.3448723728
Short name T840
Test name
Test status
Simulation time 528142767 ps
CPU time 1.89 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:33 PM PDT 24
Peak memory 201436 kb
Host smart-97c105a7-3e43-4cce-b652-f30df2c99e38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448723728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.3448723728
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3158804201
Short name T917
Test name
Test status
Simulation time 2307438750 ps
CPU time 8.27 seconds
Started Jul 07 05:59:33 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 201608 kb
Host smart-fd554138-f488-4288-ad28-aa201d19122a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158804201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3158804201
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1343351247
Short name T897
Test name
Test status
Simulation time 644594711 ps
CPU time 3.65 seconds
Started Jul 07 05:59:34 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201804 kb
Host smart-0dd0bde4-bfcf-4af7-b78a-33eb5349e3f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343351247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1343351247
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.504998669
Short name T883
Test name
Test status
Simulation time 4279990358 ps
CPU time 4.23 seconds
Started Jul 07 05:59:32 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201824 kb
Host smart-f8ec0f39-3f5f-49c0-aa48-34e6412614ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504998669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.504998669
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.2643449640
Short name T854
Test name
Test status
Simulation time 423258564 ps
CPU time 0.95 seconds
Started Jul 07 05:59:54 PM PDT 24
Finished Jul 07 05:59:56 PM PDT 24
Peak memory 201424 kb
Host smart-377d878c-5640-4273-aaf9-d6c76eaa43c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643449640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.2643449640
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3292098295
Short name T801
Test name
Test status
Simulation time 429500466 ps
CPU time 0.87 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 201404 kb
Host smart-e776eed3-58f9-428d-b3e2-6950a4c0a59e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292098295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3292098295
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.4231651800
Short name T900
Test name
Test status
Simulation time 326352944 ps
CPU time 1.01 seconds
Started Jul 07 05:59:55 PM PDT 24
Finished Jul 07 05:59:57 PM PDT 24
Peak memory 201356 kb
Host smart-c902bee2-b263-41da-802e-a3e587c4512a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231651800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.4231651800
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2380920372
Short name T881
Test name
Test status
Simulation time 426071783 ps
CPU time 0.94 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:10 PM PDT 24
Peak memory 201404 kb
Host smart-c8db179b-6a46-4755-87e6-0db0022aaec4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380920372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2380920372
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.73689611
Short name T859
Test name
Test status
Simulation time 406093220 ps
CPU time 0.87 seconds
Started Jul 07 05:59:54 PM PDT 24
Finished Jul 07 05:59:55 PM PDT 24
Peak memory 201404 kb
Host smart-09a73772-718c-4342-a645-3b23d1c4a48e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73689611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.73689611
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.510026825
Short name T819
Test name
Test status
Simulation time 364153226 ps
CPU time 0.87 seconds
Started Jul 07 06:00:08 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 201404 kb
Host smart-15e5c427-770d-422c-915f-3377d97c19fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510026825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.510026825
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.3675310009
Short name T911
Test name
Test status
Simulation time 369263977 ps
CPU time 0.85 seconds
Started Jul 07 05:59:53 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 201340 kb
Host smart-e49ef021-922a-4a80-8904-cc8ae4583d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675310009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.3675310009
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.812311942
Short name T845
Test name
Test status
Simulation time 486314409 ps
CPU time 1.19 seconds
Started Jul 07 06:00:07 PM PDT 24
Finished Jul 07 06:00:09 PM PDT 24
Peak memory 201400 kb
Host smart-238b73f6-46d5-499a-954f-f3a40d6c33e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812311942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.812311942
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.2761211037
Short name T867
Test name
Test status
Simulation time 389233579 ps
CPU time 0.91 seconds
Started Jul 07 05:59:56 PM PDT 24
Finished Jul 07 05:59:58 PM PDT 24
Peak memory 201420 kb
Host smart-57cc5f58-85d8-4a3c-a9b1-322fe66e89b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761211037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.2761211037
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.3963323583
Short name T795
Test name
Test status
Simulation time 509334159 ps
CPU time 1.79 seconds
Started Jul 07 05:59:54 PM PDT 24
Finished Jul 07 05:59:56 PM PDT 24
Peak memory 201440 kb
Host smart-71b1c658-5bba-44e4-ace2-0d2651343f2a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963323583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.3963323583
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.4038737080
Short name T125
Test name
Test status
Simulation time 1060730444 ps
CPU time 4.95 seconds
Started Jul 07 05:59:33 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201996 kb
Host smart-0c9be7e9-76c6-412e-80a4-7480670a51f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038737080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.4038737080
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.2608106114
Short name T122
Test name
Test status
Simulation time 10895206530 ps
CPU time 17.59 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:47 PM PDT 24
Peak memory 201844 kb
Host smart-b6c0f01d-6f29-494c-8f39-ac7528a58b1a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608106114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.2608106114
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.1357753097
Short name T123
Test name
Test status
Simulation time 1294736225 ps
CPU time 2.24 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201508 kb
Host smart-309868bf-0727-4c8d-bf55-a5fe71c10402
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357753097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.1357753097
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.1768727776
Short name T51
Test name
Test status
Simulation time 571376172 ps
CPU time 1.11 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201564 kb
Host smart-e2cfa1ab-67f9-4087-8a09-e5cf6d1a99f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768727776 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.1768727776
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.484641845
Short name T135
Test name
Test status
Simulation time 541843978 ps
CPU time 1.86 seconds
Started Jul 07 05:59:30 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 201440 kb
Host smart-7627283e-8718-413f-8d0e-5cad5da54c0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484641845 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.484641845
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.4032134855
Short name T796
Test name
Test status
Simulation time 320477364 ps
CPU time 0.99 seconds
Started Jul 07 05:59:32 PM PDT 24
Finished Jul 07 05:59:33 PM PDT 24
Peak memory 201412 kb
Host smart-5dffa1e0-f70e-4c60-b592-6a471e80aff9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032134855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.4032134855
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4077499205
Short name T832
Test name
Test status
Simulation time 2828371580 ps
CPU time 2.42 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:39 PM PDT 24
Peak memory 201572 kb
Host smart-b04ff410-d8c0-479f-9e84-99da08a2a834
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077499205 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4077499205
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.4075298944
Short name T866
Test name
Test status
Simulation time 343274557 ps
CPU time 2.74 seconds
Started Jul 07 05:59:29 PM PDT 24
Finished Jul 07 05:59:32 PM PDT 24
Peak memory 210972 kb
Host smart-1a069194-f73c-442f-9367-ae97011271d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075298944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.4075298944
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.539654851
Short name T59
Test name
Test status
Simulation time 8668916782 ps
CPU time 7.58 seconds
Started Jul 07 05:59:32 PM PDT 24
Finished Jul 07 05:59:40 PM PDT 24
Peak memory 201824 kb
Host smart-c4ab23b4-a184-483f-a49a-e2cdb5d8021e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539654851 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.539654851
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.3072803661
Short name T811
Test name
Test status
Simulation time 516503712 ps
CPU time 0.95 seconds
Started Jul 07 05:59:54 PM PDT 24
Finished Jul 07 05:59:56 PM PDT 24
Peak memory 201420 kb
Host smart-d23b12c6-c765-47b5-8432-d4c8094edb68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072803661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.3072803661
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3438470389
Short name T851
Test name
Test status
Simulation time 329342810 ps
CPU time 0.81 seconds
Started Jul 07 05:59:55 PM PDT 24
Finished Jul 07 05:59:56 PM PDT 24
Peak memory 201428 kb
Host smart-6ef16033-4422-4f4d-aa9f-da26856e072f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438470389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3438470389
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.169349589
Short name T888
Test name
Test status
Simulation time 486969608 ps
CPU time 0.95 seconds
Started Jul 07 05:59:55 PM PDT 24
Finished Jul 07 05:59:56 PM PDT 24
Peak memory 201428 kb
Host smart-141148db-6bbc-48aa-a472-b32c1261fc41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169349589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.169349589
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.1758537452
Short name T799
Test name
Test status
Simulation time 421316313 ps
CPU time 1.16 seconds
Started Jul 07 05:59:52 PM PDT 24
Finished Jul 07 05:59:53 PM PDT 24
Peak memory 201404 kb
Host smart-a8eaa584-3683-4e40-ab81-2ed6b3976b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758537452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.1758537452
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1666918716
Short name T852
Test name
Test status
Simulation time 487125573 ps
CPU time 0.95 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201432 kb
Host smart-9036ea60-948c-4c25-94cc-e6cd480d0758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666918716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1666918716
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.62274883
Short name T798
Test name
Test status
Simulation time 351874956 ps
CPU time 1.09 seconds
Started Jul 07 05:59:59 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201408 kb
Host smart-d639e51f-45fc-4f0c-89fd-39ba1204e11a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62274883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.62274883
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.319661234
Short name T895
Test name
Test status
Simulation time 314705260 ps
CPU time 0.83 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201364 kb
Host smart-6cabee4e-af05-4e9a-8980-a8a62a107cb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319661234 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.319661234
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1711540847
Short name T872
Test name
Test status
Simulation time 499767803 ps
CPU time 0.94 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 201444 kb
Host smart-23feb3a2-1f9a-4928-9235-45c533f34f49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711540847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1711540847
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.3385826410
Short name T876
Test name
Test status
Simulation time 489774561 ps
CPU time 1.78 seconds
Started Jul 07 05:59:57 PM PDT 24
Finished Jul 07 05:59:59 PM PDT 24
Peak memory 201404 kb
Host smart-396f5826-7610-4647-93a0-d6d4c4188ef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385826410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.3385826410
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.4286909311
Short name T899
Test name
Test status
Simulation time 443651122 ps
CPU time 1.48 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:02 PM PDT 24
Peak memory 201348 kb
Host smart-45cb976e-3e69-4da3-9a79-50dc2a8c55ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286909311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.4286909311
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.3887226623
Short name T889
Test name
Test status
Simulation time 637027780 ps
CPU time 2.69 seconds
Started Jul 07 05:59:33 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 201716 kb
Host smart-56e83bd5-022d-4c25-9131-7152bddff8e7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887226623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alia
sing.3887226623
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.3313463978
Short name T45
Test name
Test status
Simulation time 44174768516 ps
CPU time 92.38 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 06:01:09 PM PDT 24
Peak memory 201792 kb
Host smart-99b5eba5-18a3-4a56-91ef-5a572397f459
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313463978 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.3313463978
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.719206184
Short name T119
Test name
Test status
Simulation time 1284216008 ps
CPU time 0.93 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201504 kb
Host smart-949ee25d-eef5-4d9f-b957-e687ab6c5535
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719206184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_re
set.719206184
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.514028098
Short name T810
Test name
Test status
Simulation time 563813658 ps
CPU time 1.28 seconds
Started Jul 07 05:59:31 PM PDT 24
Finished Jul 07 05:59:33 PM PDT 24
Peak memory 201540 kb
Host smart-564ab739-329b-4571-b6d7-9be0a70c3fed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514028098 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.514028098
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.635330601
Short name T127
Test name
Test status
Simulation time 469709806 ps
CPU time 0.91 seconds
Started Jul 07 05:59:37 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201476 kb
Host smart-85c27155-f3d5-49c0-9967-a8c7d9d4f885
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635330601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.635330601
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3029745546
Short name T890
Test name
Test status
Simulation time 296173885 ps
CPU time 1.27 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 201412 kb
Host smart-7e88ccc6-149e-4e75-8889-c9a65ab7e6c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029745546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3029745546
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1227407384
Short name T133
Test name
Test status
Simulation time 4831070572 ps
CPU time 6.13 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 201824 kb
Host smart-5749bbe1-ba60-4606-a0da-e5242e721aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227407384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1227407384
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.1421136761
Short name T58
Test name
Test status
Simulation time 889530415 ps
CPU time 2.67 seconds
Started Jul 07 05:59:32 PM PDT 24
Finished Jul 07 05:59:35 PM PDT 24
Peak memory 210248 kb
Host smart-fc8d943f-d63c-47a3-bf53-df2194866968
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421136761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.1421136761
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3933530983
Short name T49
Test name
Test status
Simulation time 4412154942 ps
CPU time 7.68 seconds
Started Jul 07 05:59:33 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 201772 kb
Host smart-9f163092-1c52-47e4-8f1c-6d02baa3b68c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933530983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3933530983
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.121642
Short name T817
Test name
Test status
Simulation time 365254170 ps
CPU time 1.47 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:02 PM PDT 24
Peak memory 201448 kb
Host smart-5ca50df5-7466-4852-b1b0-34a75228f7f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.121642
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.2475416246
Short name T914
Test name
Test status
Simulation time 386886584 ps
CPU time 1.61 seconds
Started Jul 07 05:59:59 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201428 kb
Host smart-ddb79c86-3a92-4ffb-950f-6d4b18ad0d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475416246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.2475416246
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.46316764
Short name T892
Test name
Test status
Simulation time 479535919 ps
CPU time 1.26 seconds
Started Jul 07 06:00:03 PM PDT 24
Finished Jul 07 06:00:04 PM PDT 24
Peak memory 201404 kb
Host smart-bb056d1b-ea95-4c4e-a143-acb12cec23f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46316764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.46316764
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2433417449
Short name T794
Test name
Test status
Simulation time 329010269 ps
CPU time 0.83 seconds
Started Jul 07 05:59:59 PM PDT 24
Finished Jul 07 06:00:00 PM PDT 24
Peak memory 201408 kb
Host smart-4110d34a-428d-4907-86c0-a640aeb78dc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433417449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2433417449
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.3897662707
Short name T908
Test name
Test status
Simulation time 438787498 ps
CPU time 0.89 seconds
Started Jul 07 06:00:03 PM PDT 24
Finished Jul 07 06:00:04 PM PDT 24
Peak memory 201408 kb
Host smart-af2498c1-2ab6-48f6-94c9-69a718e23d94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897662707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.3897662707
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3176277471
Short name T850
Test name
Test status
Simulation time 315641467 ps
CPU time 0.88 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201428 kb
Host smart-992dff68-b79c-4420-8a25-f4eea879ee2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176277471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3176277471
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3142255488
Short name T793
Test name
Test status
Simulation time 471433002 ps
CPU time 1.2 seconds
Started Jul 07 06:00:01 PM PDT 24
Finished Jul 07 06:00:03 PM PDT 24
Peak memory 201360 kb
Host smart-560cb726-6f9c-4c54-879d-1c10b1c41c93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142255488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3142255488
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.3464913870
Short name T823
Test name
Test status
Simulation time 344968782 ps
CPU time 1.35 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201348 kb
Host smart-a59363cf-60ae-4b05-af89-f40d29d01ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464913870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.3464913870
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3517698034
Short name T875
Test name
Test status
Simulation time 287433839 ps
CPU time 1.33 seconds
Started Jul 07 06:00:00 PM PDT 24
Finished Jul 07 06:00:01 PM PDT 24
Peak memory 201408 kb
Host smart-6456184b-21a0-4245-973f-83675a374e64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517698034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3517698034
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3774871463
Short name T813
Test name
Test status
Simulation time 385589667 ps
CPU time 0.85 seconds
Started Jul 07 06:00:05 PM PDT 24
Finished Jul 07 06:00:07 PM PDT 24
Peak memory 201408 kb
Host smart-7c41b958-ea96-48ad-87a3-1b0e2dbdefb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774871463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3774871463
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.2389499992
Short name T809
Test name
Test status
Simulation time 621015954 ps
CPU time 1.66 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201840 kb
Host smart-d62f8527-a806-4044-927b-6e12cc540f32
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389499992 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.2389499992
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.1316294933
Short name T131
Test name
Test status
Simulation time 346657554 ps
CPU time 1.16 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201480 kb
Host smart-ef49dffb-f444-42a0-95c8-194bf00403d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316294933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.1316294933
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3443352465
Short name T858
Test name
Test status
Simulation time 566710502 ps
CPU time 0.83 seconds
Started Jul 07 05:59:34 PM PDT 24
Finished Jul 07 05:59:35 PM PDT 24
Peak memory 201436 kb
Host smart-2611b507-fd3a-42fd-b814-fc628e924543
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443352465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3443352465
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.1097830463
Short name T837
Test name
Test status
Simulation time 2309057011 ps
CPU time 7.67 seconds
Started Jul 07 05:59:38 PM PDT 24
Finished Jul 07 05:59:46 PM PDT 24
Peak memory 201628 kb
Host smart-ad23c351-f4fc-4b68-9326-52c4955184b3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097830463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.1097830463
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.464207152
Short name T903
Test name
Test status
Simulation time 478706795 ps
CPU time 2.93 seconds
Started Jul 07 05:59:34 PM PDT 24
Finished Jul 07 05:59:37 PM PDT 24
Peak memory 201804 kb
Host smart-a2805468-acce-4ceb-8361-32338fda71dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464207152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.464207152
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.1769326955
Short name T901
Test name
Test status
Simulation time 4413608676 ps
CPU time 11.92 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201812 kb
Host smart-0125e74d-60d9-4c99-9023-6136879e81de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769326955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_in
tg_err.1769326955
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.4159001137
Short name T803
Test name
Test status
Simulation time 454853223 ps
CPU time 1.94 seconds
Started Jul 07 05:59:38 PM PDT 24
Finished Jul 07 05:59:40 PM PDT 24
Peak memory 201544 kb
Host smart-164508c5-28a6-449b-a24f-4aebc9ee91fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159001137 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.4159001137
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.1846561824
Short name T128
Test name
Test status
Simulation time 502517989 ps
CPU time 0.95 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:36 PM PDT 24
Peak memory 201484 kb
Host smart-bbe91d2c-aa05-4777-a2f4-8b4107522d56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846561824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.1846561824
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.1164658213
Short name T797
Test name
Test status
Simulation time 345831525 ps
CPU time 1.46 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201420 kb
Host smart-f1d3a764-2d1a-44ed-a4b9-d8ca996e5321
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164658213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.1164658213
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.1627642979
Short name T906
Test name
Test status
Simulation time 2602156865 ps
CPU time 3.91 seconds
Started Jul 07 05:59:35 PM PDT 24
Finished Jul 07 05:59:39 PM PDT 24
Peak memory 201628 kb
Host smart-8bb62197-67bd-4996-8ef6-60cf6b6a39fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627642979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.1627642979
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3042516597
Short name T910
Test name
Test status
Simulation time 387776451 ps
CPU time 2.65 seconds
Started Jul 07 05:59:39 PM PDT 24
Finished Jul 07 05:59:42 PM PDT 24
Peak memory 201796 kb
Host smart-204064fc-17f1-492c-bef9-07b64f9eb56a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042516597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3042516597
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.7912945
Short name T812
Test name
Test status
Simulation time 8877061594 ps
CPU time 23.6 seconds
Started Jul 07 05:59:41 PM PDT 24
Finished Jul 07 06:00:05 PM PDT 24
Peak memory 201784 kb
Host smart-c55b073e-4f8d-4363-86e2-d63b010b5cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7912945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_intg_
err.7912945
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2758433128
Short name T887
Test name
Test status
Simulation time 652278539 ps
CPU time 1.5 seconds
Started Jul 07 05:59:43 PM PDT 24
Finished Jul 07 05:59:45 PM PDT 24
Peak memory 201732 kb
Host smart-ad54a3ed-1f97-4490-9b80-eee61b6feaac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758433128 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2758433128
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.2485084266
Short name T886
Test name
Test status
Simulation time 526211887 ps
CPU time 1.39 seconds
Started Jul 07 05:59:41 PM PDT 24
Finished Jul 07 05:59:42 PM PDT 24
Peak memory 201496 kb
Host smart-69b933f2-87e1-4bdb-a344-104bdb6e44f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485084266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.2485084266
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.145298155
Short name T842
Test name
Test status
Simulation time 410222357 ps
CPU time 1.63 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201424 kb
Host smart-45220a45-5d85-4f62-8a21-481862fa78b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145298155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.145298155
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.248253965
Short name T833
Test name
Test status
Simulation time 4287099649 ps
CPU time 14.6 seconds
Started Jul 07 05:59:39 PM PDT 24
Finished Jul 07 05:59:54 PM PDT 24
Peak memory 201816 kb
Host smart-d253df6f-1be4-46f1-b718-dd73bfddb33b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248253965 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ct
rl_same_csr_outstanding.248253965
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2235696676
Short name T865
Test name
Test status
Simulation time 541624438 ps
CPU time 1.93 seconds
Started Jul 07 05:59:36 PM PDT 24
Finished Jul 07 05:59:38 PM PDT 24
Peak memory 201792 kb
Host smart-5a4e77fc-854c-4483-86e6-adfe86122338
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235696676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2235696676
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.4183158723
Short name T66
Test name
Test status
Simulation time 8310364194 ps
CPU time 11.94 seconds
Started Jul 07 05:59:41 PM PDT 24
Finished Jul 07 05:59:53 PM PDT 24
Peak memory 201808 kb
Host smart-be755b44-6f31-449d-8bb9-d48aea4f5848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183158723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.4183158723
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.21688143
Short name T52
Test name
Test status
Simulation time 665897618 ps
CPU time 1.32 seconds
Started Jul 07 05:59:38 PM PDT 24
Finished Jul 07 05:59:40 PM PDT 24
Peak memory 201488 kb
Host smart-46cc3ce1-e50a-4377-83e5-f2b1d623da7a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21688143 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.21688143
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.4023019440
Short name T891
Test name
Test status
Simulation time 342219621 ps
CPU time 0.94 seconds
Started Jul 07 05:59:40 PM PDT 24
Finished Jul 07 05:59:41 PM PDT 24
Peak memory 201412 kb
Host smart-a64b6aab-48c8-4daf-8ec8-a690918bc271
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023019440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.4023019440
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2807074867
Short name T857
Test name
Test status
Simulation time 509575570 ps
CPU time 1.25 seconds
Started Jul 07 05:59:41 PM PDT 24
Finished Jul 07 05:59:42 PM PDT 24
Peak memory 201328 kb
Host smart-f169cd7a-4636-4d31-a5ed-80e8be20297f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807074867 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2807074867
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.3731036332
Short name T913
Test name
Test status
Simulation time 2725657012 ps
CPU time 3.92 seconds
Started Jul 07 05:59:44 PM PDT 24
Finished Jul 07 05:59:48 PM PDT 24
Peak memory 201824 kb
Host smart-6196b2a3-f52a-4217-a333-9858848197b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731036332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.3731036332
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.2359405789
Short name T57
Test name
Test status
Simulation time 392549062 ps
CPU time 1.89 seconds
Started Jul 07 05:59:43 PM PDT 24
Finished Jul 07 05:59:45 PM PDT 24
Peak memory 201660 kb
Host smart-957386ab-0aa7-44b8-ad5e-c683f58392ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359405789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.2359405789
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.2221449769
Short name T65
Test name
Test status
Simulation time 4781735054 ps
CPU time 3.6 seconds
Started Jul 07 05:59:41 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201776 kb
Host smart-873ef200-b257-4889-bec6-dfadbc25cb38
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221449769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.2221449769
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1027745882
Short name T800
Test name
Test status
Simulation time 426930803 ps
CPU time 1.9 seconds
Started Jul 07 05:59:43 PM PDT 24
Finished Jul 07 05:59:45 PM PDT 24
Peak memory 201480 kb
Host smart-6272b7c3-b5af-43d5-aa8b-f6e419321536
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027745882 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1027745882
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.150653869
Short name T862
Test name
Test status
Simulation time 504510448 ps
CPU time 0.88 seconds
Started Jul 07 05:59:43 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201540 kb
Host smart-f50cc7be-0efb-441d-b28a-9b43184fe4f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150653869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.150653869
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.2607374601
Short name T830
Test name
Test status
Simulation time 434492642 ps
CPU time 0.87 seconds
Started Jul 07 05:59:39 PM PDT 24
Finished Jul 07 05:59:40 PM PDT 24
Peak memory 201424 kb
Host smart-c98fb1a0-97e1-470d-8593-64059415b117
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607374601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.2607374601
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1012362888
Short name T836
Test name
Test status
Simulation time 5324181066 ps
CPU time 20.45 seconds
Started Jul 07 05:59:39 PM PDT 24
Finished Jul 07 06:00:00 PM PDT 24
Peak memory 201788 kb
Host smart-faf907c2-6794-4821-af0f-95cac318ad92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012362888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1012362888
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.3303308406
Short name T885
Test name
Test status
Simulation time 606009731 ps
CPU time 3.21 seconds
Started Jul 07 05:59:41 PM PDT 24
Finished Jul 07 05:59:44 PM PDT 24
Peak memory 201780 kb
Host smart-42307d16-97c8-488c-8205-d44804a49665
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303308406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.3303308406
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.3670241004
Short name T870
Test name
Test status
Simulation time 4606789231 ps
CPU time 7.15 seconds
Started Jul 07 05:59:38 PM PDT 24
Finished Jul 07 05:59:46 PM PDT 24
Peak memory 201772 kb
Host smart-ccc15e50-432c-42b8-9625-7a8e40c46ef9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670241004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.3670241004
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.1945177695
Short name T701
Test name
Test status
Simulation time 355125914 ps
CPU time 0.81 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:00:27 PM PDT 24
Peak memory 201652 kb
Host smart-c3953d67-fbe9-4ced-be8a-9ec0c4d5f945
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945177695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.1945177695
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2189921505
Short name T536
Test name
Test status
Simulation time 346958693372 ps
CPU time 249.21 seconds
Started Jul 07 06:00:28 PM PDT 24
Finished Jul 07 06:04:37 PM PDT 24
Peak memory 201924 kb
Host smart-651a1dd7-ffa0-45d5-8793-a51bf4cf16d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189921505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2189921505
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.3512805649
Short name T540
Test name
Test status
Simulation time 333795923941 ps
CPU time 764.97 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:13:11 PM PDT 24
Peak memory 201892 kb
Host smart-f86e826f-48a6-4d3b-95ef-62cee84bfc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512805649 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.3512805649
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1273673001
Short name T785
Test name
Test status
Simulation time 486531263089 ps
CPU time 1094.15 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:18:39 PM PDT 24
Peak memory 202156 kb
Host smart-116302ed-2e02-4800-93c2-75fe8f2f9029
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273673001 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1273673001
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3822254957
Short name T556
Test name
Test status
Simulation time 161603489898 ps
CPU time 345.82 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:06:18 PM PDT 24
Peak memory 201908 kb
Host smart-0917eb3f-05f7-41f6-9d17-719385a9d245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822254957 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3822254957
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.2981495842
Short name T739
Test name
Test status
Simulation time 336182201834 ps
CPU time 130.7 seconds
Started Jul 07 06:00:22 PM PDT 24
Finished Jul 07 06:02:33 PM PDT 24
Peak memory 201952 kb
Host smart-b7ffd8d0-cee1-4dc5-8f92-612c2c291e31
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981495842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.2981495842
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.1173296566
Short name T292
Test name
Test status
Simulation time 373427753371 ps
CPU time 52.34 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:01:19 PM PDT 24
Peak memory 201908 kb
Host smart-f3c30256-6681-4151-a1ae-c8e42bf9f95c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173296566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.1173296566
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3638444340
Short name T716
Test name
Test status
Simulation time 611217329227 ps
CPU time 676.69 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:11:43 PM PDT 24
Peak memory 201980 kb
Host smart-f3fa29eb-b693-46da-bfb0-717a4baa7910
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638444340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3638444340
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.3131432400
Short name T343
Test name
Test status
Simulation time 107492050489 ps
CPU time 417.36 seconds
Started Jul 07 06:00:23 PM PDT 24
Finished Jul 07 06:07:21 PM PDT 24
Peak memory 202472 kb
Host smart-e91ca248-78ab-4ca9-869a-9ff057687037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131432400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.3131432400
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.1889661650
Short name T434
Test name
Test status
Simulation time 41097935038 ps
CPU time 87.59 seconds
Started Jul 07 06:00:28 PM PDT 24
Finished Jul 07 06:01:56 PM PDT 24
Peak memory 201712 kb
Host smart-961fe9bd-0ca2-48e6-ae2b-1898ae1e7d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889661650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.1889661650
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.3638746646
Short name T637
Test name
Test status
Simulation time 4358018437 ps
CPU time 2.2 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:00:28 PM PDT 24
Peak memory 201712 kb
Host smart-6a6da484-e07b-4f57-a32d-3ccabf231f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638746646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.3638746646
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.181930169
Short name T67
Test name
Test status
Simulation time 8583914098 ps
CPU time 5.2 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:00:32 PM PDT 24
Peak memory 218188 kb
Host smart-7430faef-965a-441a-a189-cf450b0944af
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181930169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.181930169
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1602358192
Short name T103
Test name
Test status
Simulation time 5660422761 ps
CPU time 4.24 seconds
Started Jul 07 06:00:24 PM PDT 24
Finished Jul 07 06:00:29 PM PDT 24
Peak memory 201696 kb
Host smart-5bbc8180-2530-4f4f-bc6c-fb4a3dd9fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602358192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1602358192
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.3240626102
Short name T157
Test name
Test status
Simulation time 1665798672790 ps
CPU time 3373.58 seconds
Started Jul 07 06:00:25 PM PDT 24
Finished Jul 07 06:56:40 PM PDT 24
Peak memory 212880 kb
Host smart-77b9760a-5b71-4623-9c4d-f96b7b420dd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240626102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
3240626102
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.3249595450
Short name T593
Test name
Test status
Simulation time 477559936 ps
CPU time 0.92 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:00:36 PM PDT 24
Peak memory 201508 kb
Host smart-278c1c1f-09fa-489c-ba8c-ae1ca4b4fdac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249595450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.3249595450
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.642834376
Short name T710
Test name
Test status
Simulation time 161992268320 ps
CPU time 3.85 seconds
Started Jul 07 06:00:30 PM PDT 24
Finished Jul 07 06:00:34 PM PDT 24
Peak memory 201868 kb
Host smart-e51cebb7-f072-4052-b295-f2f78569b34f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642834376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gatin
g.642834376
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2370731368
Short name T712
Test name
Test status
Simulation time 369656709120 ps
CPU time 809.3 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:14:02 PM PDT 24
Peak memory 201936 kb
Host smart-3cda4a35-d545-45b5-a82c-aedcb7ca6921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370731368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2370731368
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.817573689
Short name T257
Test name
Test status
Simulation time 164193893187 ps
CPU time 384.48 seconds
Started Jul 07 06:00:27 PM PDT 24
Finished Jul 07 06:06:52 PM PDT 24
Peak memory 201972 kb
Host smart-d677b7b1-9ee6-40a6-bd86-1efd9b7e3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817573689 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.817573689
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.2942577646
Short name T398
Test name
Test status
Simulation time 164452101362 ps
CPU time 350.77 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:06:29 PM PDT 24
Peak memory 201736 kb
Host smart-714fb868-c561-4259-b292-e97168071df1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942577646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.2942577646
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.3046214881
Short name T308
Test name
Test status
Simulation time 320272022220 ps
CPU time 715.79 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:12:22 PM PDT 24
Peak memory 201892 kb
Host smart-2f3b939b-7135-4e34-918b-9898128836e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046214881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.3046214881
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.2617885006
Short name T522
Test name
Test status
Simulation time 168461274327 ps
CPU time 198.59 seconds
Started Jul 07 06:00:27 PM PDT 24
Finished Jul 07 06:03:46 PM PDT 24
Peak memory 201876 kb
Host smart-0a0ad904-96a0-422f-b6ec-ee5f66c80e37
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617885006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.2617885006
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.3499892438
Short name T236
Test name
Test status
Simulation time 197117079821 ps
CPU time 443.25 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:07:55 PM PDT 24
Peak memory 201856 kb
Host smart-7e21ecc6-d78b-410b-a17e-0795d53226d6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499892438 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.3499892438
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1307534217
Short name T607
Test name
Test status
Simulation time 402311827351 ps
CPU time 889.47 seconds
Started Jul 07 06:00:27 PM PDT 24
Finished Jul 07 06:15:16 PM PDT 24
Peak memory 201888 kb
Host smart-0f291616-9d78-48c3-a2d6-31ecb665b89b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307534217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1307534217
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.421736754
Short name T430
Test name
Test status
Simulation time 84559103141 ps
CPU time 355.31 seconds
Started Jul 07 06:00:29 PM PDT 24
Finished Jul 07 06:06:24 PM PDT 24
Peak memory 202284 kb
Host smart-6a2bb9b5-0217-44c5-8b28-cb0a9f59437a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421736754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.421736754
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.1650025669
Short name T515
Test name
Test status
Simulation time 21350968148 ps
CPU time 5.08 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:00:38 PM PDT 24
Peak memory 201724 kb
Host smart-4eb7094c-5a8c-408d-81f4-a1382a78e98c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650025669 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.1650025669
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2728512897
Short name T347
Test name
Test status
Simulation time 4393097158 ps
CPU time 9.29 seconds
Started Jul 07 06:00:28 PM PDT 24
Finished Jul 07 06:00:38 PM PDT 24
Peak memory 201992 kb
Host smart-1cea671a-25c5-4d65-98b3-4efb1a81e4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728512897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2728512897
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.582958489
Short name T54
Test name
Test status
Simulation time 4109249775 ps
CPU time 3.04 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:00:38 PM PDT 24
Peak memory 217184 kb
Host smart-11e807ff-fde0-4c71-93ef-bde13150c952
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582958489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.582958489
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.4202616785
Short name T355
Test name
Test status
Simulation time 5760565159 ps
CPU time 14.73 seconds
Started Jul 07 06:00:27 PM PDT 24
Finished Jul 07 06:00:42 PM PDT 24
Peak memory 201688 kb
Host smart-c08a7e0d-8b8b-4f47-b0ff-fa45d135a9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202616785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.4202616785
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.971203875
Short name T6
Test name
Test status
Simulation time 408970171911 ps
CPU time 1142.96 seconds
Started Jul 07 06:00:28 PM PDT 24
Finished Jul 07 06:19:31 PM PDT 24
Peak memory 218556 kb
Host smart-3a7c6d08-ea45-4d47-8008-a04145bfa439
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971203875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.971203875
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.2603239695
Short name T642
Test name
Test status
Simulation time 493258787 ps
CPU time 1.85 seconds
Started Jul 07 06:00:46 PM PDT 24
Finished Jul 07 06:00:48 PM PDT 24
Peak memory 201592 kb
Host smart-468f751d-075b-4ab0-bb11-3df35400457a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603239695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.2603239695
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.870172138
Short name T90
Test name
Test status
Simulation time 175998218373 ps
CPU time 209.02 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:04:16 PM PDT 24
Peak memory 201896 kb
Host smart-5c99f0c5-d7cb-4987-8b54-3cb842a7b7a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870172138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gati
ng.870172138
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.657341108
Short name T655
Test name
Test status
Simulation time 164509820826 ps
CPU time 363.07 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:06:52 PM PDT 24
Peak memory 201980 kb
Host smart-5144369d-334d-4bfe-9d1a-54d72666f57b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657341108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.657341108
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.154564169
Short name T743
Test name
Test status
Simulation time 323893760020 ps
CPU time 77.64 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:02:07 PM PDT 24
Peak memory 201892 kb
Host smart-578162ab-8d70-43a8-9e83-93041a6623f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154564169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.154564169
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1029434478
Short name T713
Test name
Test status
Simulation time 329406761546 ps
CPU time 60.89 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:01:47 PM PDT 24
Peak memory 201868 kb
Host smart-deccef2e-6255-4741-939d-a0bbe362e7bc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029434478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1029434478
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3331324330
Short name T8
Test name
Test status
Simulation time 487408180326 ps
CPU time 263.54 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:05:11 PM PDT 24
Peak memory 201932 kb
Host smart-b8ab26dc-9da2-4093-9273-c334e563db22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331324330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3331324330
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.3505499618
Short name T539
Test name
Test status
Simulation time 325171433787 ps
CPU time 461.06 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:08:26 PM PDT 24
Peak memory 201884 kb
Host smart-f65ccec6-9116-4014-bd26-a8d6b639c4b9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505499618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.3505499618
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.3747443366
Short name T572
Test name
Test status
Simulation time 399245271398 ps
CPU time 911.93 seconds
Started Jul 07 06:00:46 PM PDT 24
Finished Jul 07 06:15:58 PM PDT 24
Peak memory 201892 kb
Host smart-d89c3a08-9c75-40b5-a70e-4c12334d2978
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747443366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10
.adc_ctrl_filters_wakeup_fixed.3747443366
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.1466544201
Short name T344
Test name
Test status
Simulation time 25627126849 ps
CPU time 9.11 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:00:55 PM PDT 24
Peak memory 201680 kb
Host smart-46369758-744e-4921-89c6-fe673b6cae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466544201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.1466544201
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.2255749854
Short name T391
Test name
Test status
Simulation time 2784707961 ps
CPU time 2.34 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:00:51 PM PDT 24
Peak memory 201700 kb
Host smart-81d5ba36-c0a1-48d2-9bb2-953527cac6cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255749854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.2255749854
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.1477200769
Short name T587
Test name
Test status
Simulation time 5761638659 ps
CPU time 13.79 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:01:00 PM PDT 24
Peak memory 201656 kb
Host smart-79b50865-a847-4e41-998a-acecdabc37c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477200769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.1477200769
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.2654835379
Short name T170
Test name
Test status
Simulation time 507366400631 ps
CPU time 297.22 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:05:45 PM PDT 24
Peak memory 201796 kb
Host smart-a43d089c-aabf-4373-b508-062de302c8ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654835379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.2654835379
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.621810949
Short name T470
Test name
Test status
Simulation time 418226005 ps
CPU time 0.83 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:00:50 PM PDT 24
Peak memory 201640 kb
Host smart-4b7e9d25-9ab8-40ba-9feb-bed39d0b9bf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621810949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.621810949
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.3062349229
Short name T588
Test name
Test status
Simulation time 167403843979 ps
CPU time 313.2 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:05:59 PM PDT 24
Peak memory 201864 kb
Host smart-e840bb8b-252d-4342-aeef-a8e759db961a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062349229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gat
ing.3062349229
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.2406158683
Short name T629
Test name
Test status
Simulation time 325321257570 ps
CPU time 208.54 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:04:13 PM PDT 24
Peak memory 201976 kb
Host smart-a4a52c5e-be72-474a-9c4e-8c551c561b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406158683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.2406158683
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.1861174539
Short name T528
Test name
Test status
Simulation time 165291977731 ps
CPU time 201.51 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:04:07 PM PDT 24
Peak memory 201904 kb
Host smart-687cf33a-2e58-4594-9803-3925931509c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861174539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.1861174539
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1207066123
Short name T660
Test name
Test status
Simulation time 491015466021 ps
CPU time 459.37 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:08:23 PM PDT 24
Peak memory 201948 kb
Host smart-3f4ab7f1-007d-434c-ba3d-9cbfec2620cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207066123 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1207066123
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2555859353
Short name T731
Test name
Test status
Simulation time 494873928008 ps
CPU time 579.82 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:10:27 PM PDT 24
Peak memory 201864 kb
Host smart-9b150462-b376-46de-9b28-ce8f80a48eec
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555859353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2555859353
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.3893765229
Short name T145
Test name
Test status
Simulation time 176956106553 ps
CPU time 393.3 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:07:19 PM PDT 24
Peak memory 201796 kb
Host smart-ffa7e6bf-51f8-4c7e-a54c-4d9c765f6aad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893765229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.3893765229
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1524120351
Short name T619
Test name
Test status
Simulation time 207189244552 ps
CPU time 163.03 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:03:31 PM PDT 24
Peak memory 201892 kb
Host smart-dbddde4f-c50c-42d9-876c-62dfe75a0389
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524120351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1524120351
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3042248903
Short name T82
Test name
Test status
Simulation time 88817416360 ps
CPU time 447.05 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:08:26 PM PDT 24
Peak memory 202236 kb
Host smart-192a8cd1-8ef1-4db7-9281-7a05d48ad6b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042248903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3042248903
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.41727668
Short name T656
Test name
Test status
Simulation time 28372184157 ps
CPU time 6.18 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:01:00 PM PDT 24
Peak memory 201972 kb
Host smart-e335983d-556f-4229-83be-5274624ad477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41727668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.41727668
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2557777364
Short name T532
Test name
Test status
Simulation time 3822406616 ps
CPU time 4.16 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:01:04 PM PDT 24
Peak memory 201712 kb
Host smart-24190d35-1462-44f4-9387-ec73f166a578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557777364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2557777364
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.503349082
Short name T167
Test name
Test status
Simulation time 5503198659 ps
CPU time 12.61 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:01:01 PM PDT 24
Peak memory 201700 kb
Host smart-4a18f30b-9040-475e-8c80-a9a9ca34001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503349082 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.503349082
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.621433063
Short name T693
Test name
Test status
Simulation time 69564078547 ps
CPU time 164.23 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:03:36 PM PDT 24
Peak memory 201692 kb
Host smart-9eee58b0-5cd7-4bda-8b97-5bb0032bd2e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621433063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
621433063
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.3341414306
Short name T591
Test name
Test status
Simulation time 465641570 ps
CPU time 1.76 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:01:02 PM PDT 24
Peak memory 201512 kb
Host smart-0593eff5-2a14-4c27-bb48-dc012ce03c4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341414306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.3341414306
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.990343333
Short name T332
Test name
Test status
Simulation time 165885452057 ps
CPU time 361.98 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:06:54 PM PDT 24
Peak memory 201956 kb
Host smart-491da2d4-ea88-459d-b476-d1004d41d7cc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990343333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gati
ng.990343333
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.3195918683
Short name T223
Test name
Test status
Simulation time 363912505956 ps
CPU time 411.57 seconds
Started Jul 07 06:00:51 PM PDT 24
Finished Jul 07 06:07:43 PM PDT 24
Peak memory 201924 kb
Host smart-334841a3-4797-49e1-8c07-671ed702c318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195918683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.3195918683
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.1280417749
Short name T431
Test name
Test status
Simulation time 165501726360 ps
CPU time 99.45 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:02:37 PM PDT 24
Peak memory 201976 kb
Host smart-8fa3b80e-eaaa-4abd-b835-18bc29465596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280417749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.1280417749
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.446443985
Short name T402
Test name
Test status
Simulation time 163383500498 ps
CPU time 94.73 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:02:24 PM PDT 24
Peak memory 201892 kb
Host smart-1f293d65-e58b-41f8-b280-6d821b16e408
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=446443985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrup
t_fixed.446443985
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2261974711
Short name T69
Test name
Test status
Simulation time 334534040288 ps
CPU time 771.09 seconds
Started Jul 07 06:00:55 PM PDT 24
Finished Jul 07 06:13:46 PM PDT 24
Peak memory 201960 kb
Host smart-a44fe96f-c56c-4f93-be3c-07350272570a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261974711 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2261974711
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.2798358652
Short name T742
Test name
Test status
Simulation time 165029243461 ps
CPU time 217.69 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:04:30 PM PDT 24
Peak memory 201864 kb
Host smart-a8efe935-654a-41b3-b003-07e97012a34d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798358652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.2798358652
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.680762335
Short name T324
Test name
Test status
Simulation time 175672659909 ps
CPU time 387 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:07:19 PM PDT 24
Peak memory 201872 kb
Host smart-747a165d-5d65-45d8-b372-0206f7a7180c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680762335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_
wakeup.680762335
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.21628079
Short name T377
Test name
Test status
Simulation time 600276511297 ps
CPU time 1455.64 seconds
Started Jul 07 06:00:51 PM PDT 24
Finished Jul 07 06:25:07 PM PDT 24
Peak memory 201892 kb
Host smart-a7936732-5d41-47d0-882d-f40a1611299f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21628079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.a
dc_ctrl_filters_wakeup_fixed.21628079
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.1970084560
Short name T191
Test name
Test status
Simulation time 27150799576 ps
CPU time 15.44 seconds
Started Jul 07 06:00:51 PM PDT 24
Finished Jul 07 06:01:07 PM PDT 24
Peak memory 201720 kb
Host smart-ceaa1e96-fea0-4e62-86c8-20fbdf673080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1970084560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.1970084560
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.2645849362
Short name T674
Test name
Test status
Simulation time 4557502361 ps
CPU time 11.24 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:01:05 PM PDT 24
Peak memory 201708 kb
Host smart-17d30329-7b1b-44a0-b4c7-872f02f21f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645849362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.2645849362
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.748093069
Short name T652
Test name
Test status
Simulation time 6022898305 ps
CPU time 2.3 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:00:52 PM PDT 24
Peak memory 201988 kb
Host smart-154df68b-104e-4088-b5b6-d055b68244f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748093069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.748093069
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.3743748447
Short name T244
Test name
Test status
Simulation time 497684464641 ps
CPU time 614.85 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:11:07 PM PDT 24
Peak memory 201880 kb
Host smart-b90aca91-6043-4fad-9618-5baaacd3a2de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743748447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.3743748447
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.2914184295
Short name T36
Test name
Test status
Simulation time 14179167683 ps
CPU time 47.08 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:01:36 PM PDT 24
Peak memory 202344 kb
Host smart-6a6bdac9-e4e6-47b2-b884-fc454537f87e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914184295 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.2914184295
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.3599290710
Short name T789
Test name
Test status
Simulation time 491633152 ps
CPU time 1.23 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:00:56 PM PDT 24
Peak memory 201668 kb
Host smart-c959e01d-8de3-4b2e-87f4-4860465a59c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599290710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.3599290710
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.3516341783
Short name T80
Test name
Test status
Simulation time 182054167915 ps
CPU time 152.56 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:03:24 PM PDT 24
Peak memory 201896 kb
Host smart-ef11a42e-f4a3-4f95-87ca-8b494029f2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516341783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.3516341783
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.35737674
Short name T756
Test name
Test status
Simulation time 162239180700 ps
CPU time 44.93 seconds
Started Jul 07 06:00:53 PM PDT 24
Finished Jul 07 06:01:38 PM PDT 24
Peak memory 201964 kb
Host smart-b43c5d9e-baac-43a9-987b-1cd97faed2fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35737674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.35737674
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.1406910736
Short name T647
Test name
Test status
Simulation time 327826414265 ps
CPU time 190.26 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:03:59 PM PDT 24
Peak memory 201872 kb
Host smart-5717bb5d-3d00-426f-b9b6-d3d09d78249a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406910736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.1406910736
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1011338883
Short name T183
Test name
Test status
Simulation time 327179179241 ps
CPU time 380.46 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:07:20 PM PDT 24
Peak memory 201728 kb
Host smart-5bdf7fdd-d50c-44fe-b605-3fa03c1d1e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011338883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1011338883
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.4205556327
Short name T366
Test name
Test status
Simulation time 159468265151 ps
CPU time 362.43 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:06:59 PM PDT 24
Peak memory 201772 kb
Host smart-17257be4-799b-4eae-8fba-f6b8a802a850
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205556327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.4205556327
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.468873356
Short name T318
Test name
Test status
Simulation time 547377101408 ps
CPU time 1101.8 seconds
Started Jul 07 06:00:53 PM PDT 24
Finished Jul 07 06:19:15 PM PDT 24
Peak memory 201916 kb
Host smart-bcba7716-990a-4471-bfeb-91e380e4da83
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468873356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_
wakeup.468873356
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.783760402
Short name T650
Test name
Test status
Simulation time 582764950870 ps
CPU time 1206.23 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:20:58 PM PDT 24
Peak memory 201800 kb
Host smart-7ee53e3e-e9bc-4bb7-ad3a-34f1750a8742
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783760402 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.783760402
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2484312701
Short name T597
Test name
Test status
Simulation time 70718970698 ps
CPU time 363.73 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:07:01 PM PDT 24
Peak memory 202256 kb
Host smart-dd93ddb5-4edf-4fd6-aa3d-9496fee26010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484312701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2484312701
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.1083224809
Short name T373
Test name
Test status
Simulation time 44921314127 ps
CPU time 23.14 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:01:12 PM PDT 24
Peak memory 201712 kb
Host smart-8317f405-5603-42d4-948f-1f41a914e854
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083224809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.1083224809
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.2572630383
Short name T732
Test name
Test status
Simulation time 2814575475 ps
CPU time 3.88 seconds
Started Jul 07 06:00:55 PM PDT 24
Finished Jul 07 06:00:59 PM PDT 24
Peak memory 201700 kb
Host smart-a305a325-7d58-491c-92c7-2482e3ad8e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572630383 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.2572630383
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.1191716603
Short name T630
Test name
Test status
Simulation time 5532770359 ps
CPU time 12.77 seconds
Started Jul 07 06:00:52 PM PDT 24
Finished Jul 07 06:01:05 PM PDT 24
Peak memory 201740 kb
Host smart-e32d56b2-973f-497d-885a-856c109f2f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191716603 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.1191716603
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.1471561139
Short name T668
Test name
Test status
Simulation time 96377999722 ps
CPU time 474.81 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:08:44 PM PDT 24
Peak memory 202184 kb
Host smart-c8dd0176-a125-44d1-8cec-75710da766a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471561139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.1471561139
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.4227239344
Short name T88
Test name
Test status
Simulation time 512006630058 ps
CPU time 219.39 seconds
Started Jul 07 06:00:51 PM PDT 24
Finished Jul 07 06:04:31 PM PDT 24
Peak memory 210540 kb
Host smart-4da0d406-19cf-4066-b585-11d163baa38c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227239344 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.4227239344
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.3467967540
Short name T192
Test name
Test status
Simulation time 356307482421 ps
CPU time 139.3 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:03:18 PM PDT 24
Peak memory 201824 kb
Host smart-77ee4534-193a-46be-bfdc-58806628aeff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467967540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.3467967540
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.433147418
Short name T686
Test name
Test status
Simulation time 551475717422 ps
CPU time 325.95 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:06:20 PM PDT 24
Peak memory 201956 kb
Host smart-fadda111-93e9-4180-8ba8-1ba693787585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433147418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.433147418
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.240869376
Short name T598
Test name
Test status
Simulation time 162365716510 ps
CPU time 99.83 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:02:38 PM PDT 24
Peak memory 201892 kb
Host smart-c5a44d3d-3e15-4168-b6cc-10e5bb37adb7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=240869376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.240869376
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.3331011153
Short name T260
Test name
Test status
Simulation time 322906704961 ps
CPU time 195.74 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:04:16 PM PDT 24
Peak memory 201620 kb
Host smart-425a98b4-c7ac-4d6f-92eb-43df725c8d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331011153 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.3331011153
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.451416558
Short name T766
Test name
Test status
Simulation time 166180097878 ps
CPU time 353.61 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:06:51 PM PDT 24
Peak memory 201928 kb
Host smart-b7b29936-019e-4b78-a2c7-01b95feb045f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=451416558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.451416558
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.528403141
Short name T727
Test name
Test status
Simulation time 172960979482 ps
CPU time 94.78 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:02:33 PM PDT 24
Peak memory 201972 kb
Host smart-dbc979a5-6b62-4952-b24f-45f83e0c29c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528403141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.528403141
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.1551628189
Short name T666
Test name
Test status
Simulation time 609594931482 ps
CPU time 1474.39 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:25:33 PM PDT 24
Peak memory 201888 kb
Host smart-7d21a7c4-17c3-4d20-9788-4d2ab8c58227
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551628189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.1551628189
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.60685442
Short name T548
Test name
Test status
Simulation time 108677419476 ps
CPU time 562.11 seconds
Started Jul 07 06:00:53 PM PDT 24
Finished Jul 07 06:10:15 PM PDT 24
Peak memory 202148 kb
Host smart-6886aa55-28de-4fa4-a747-fffda0427f23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60685442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.60685442
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.907131600
Short name T781
Test name
Test status
Simulation time 33072824124 ps
CPU time 39.42 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:01:38 PM PDT 24
Peak memory 201720 kb
Host smart-d670b275-f460-4645-ae8f-f71ca1764365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907131600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.907131600
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.710521643
Short name T646
Test name
Test status
Simulation time 4092896867 ps
CPU time 1.82 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:00:57 PM PDT 24
Peak memory 201640 kb
Host smart-00f2cfde-ef1b-4cc4-bb77-a340cb8e839b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710521643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.710521643
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3410390828
Short name T345
Test name
Test status
Simulation time 5808154180 ps
CPU time 7.2 seconds
Started Jul 07 06:00:51 PM PDT 24
Finished Jul 07 06:00:58 PM PDT 24
Peak memory 201740 kb
Host smart-1879a031-b4d2-43e6-a282-9448efbe2c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410390828 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3410390828
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.59250157
Short name T367
Test name
Test status
Simulation time 484216383 ps
CPU time 1.31 seconds
Started Jul 07 06:01:02 PM PDT 24
Finished Jul 07 06:01:04 PM PDT 24
Peak memory 201676 kb
Host smart-cd8d3439-3699-4a05-b982-8fd49e86cb53
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59250157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.59250157
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3225320364
Short name T218
Test name
Test status
Simulation time 337810087742 ps
CPU time 139.57 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:03:16 PM PDT 24
Peak memory 201908 kb
Host smart-3343d104-d7aa-4373-aa40-357feb8e7765
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225320364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3225320364
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1496629627
Short name T567
Test name
Test status
Simulation time 192988158509 ps
CPU time 306.91 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:06:04 PM PDT 24
Peak memory 201892 kb
Host smart-2c66a353-6644-49ac-81ac-d76720ce6358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496629627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1496629627
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2121676044
Short name T612
Test name
Test status
Simulation time 327130809385 ps
CPU time 599.08 seconds
Started Jul 07 06:01:02 PM PDT 24
Finished Jul 07 06:11:02 PM PDT 24
Peak memory 201876 kb
Host smart-cea95dc3-3007-4e5d-aba9-cda5ae12b25d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121676044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2121676044
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2795907158
Short name T640
Test name
Test status
Simulation time 488156312603 ps
CPU time 1066.4 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:18:40 PM PDT 24
Peak memory 201916 kb
Host smart-c5ee1566-c733-41cf-8109-67607ed2ba23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795907158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2795907158
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.879213361
Short name T450
Test name
Test status
Simulation time 497242923120 ps
CPU time 190.98 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:04:10 PM PDT 24
Peak memory 201956 kb
Host smart-1537d5f7-4fca-4b0a-83db-3942b184be09
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=879213361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.879213361
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.4221623171
Short name T586
Test name
Test status
Simulation time 394963160274 ps
CPU time 932.67 seconds
Started Jul 07 06:00:50 PM PDT 24
Finished Jul 07 06:16:23 PM PDT 24
Peak memory 201868 kb
Host smart-abcb9cf8-3a5d-46d9-8d75-113903f31269
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221623171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.4221623171
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.3281462922
Short name T113
Test name
Test status
Simulation time 34166503850 ps
CPU time 18.99 seconds
Started Jul 07 06:00:55 PM PDT 24
Finished Jul 07 06:01:14 PM PDT 24
Peak memory 201688 kb
Host smart-c073509f-1464-465f-8713-6ba16d6476cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281462922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.3281462922
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.4113905463
Short name T7
Test name
Test status
Simulation time 2825970025 ps
CPU time 7.2 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:01:04 PM PDT 24
Peak memory 201704 kb
Host smart-6b80d0b3-0aab-40f1-9fbe-ab903f3f56c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113905463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.4113905463
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.93192160
Short name T408
Test name
Test status
Simulation time 5838190005 ps
CPU time 4.25 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:01:02 PM PDT 24
Peak memory 201712 kb
Host smart-237b74b5-f1a9-4908-b29f-892a8bc6e28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93192160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.93192160
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.499933284
Short name T71
Test name
Test status
Simulation time 322803335936 ps
CPU time 239.82 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:04:59 PM PDT 24
Peak memory 201900 kb
Host smart-5ca69e33-869f-4066-b3ef-1759be39ffca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499933284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
499933284
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.1029096596
Short name T691
Test name
Test status
Simulation time 78235818326 ps
CPU time 295.23 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:05:53 PM PDT 24
Peak memory 218692 kb
Host smart-ca7d19ab-1863-4184-903a-a2ac4c90d193
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029096596 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.1029096596
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1725685130
Short name T641
Test name
Test status
Simulation time 392861800 ps
CPU time 0.76 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:00:57 PM PDT 24
Peak memory 201664 kb
Host smart-93ac2466-0a7b-4519-95c4-81547a9e3b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725685130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1725685130
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.3444418169
Short name T523
Test name
Test status
Simulation time 571944093364 ps
CPU time 518.22 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:09:36 PM PDT 24
Peak memory 201780 kb
Host smart-28a2a894-7928-4d2e-bd07-77dc74d92e34
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444418169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.3444418169
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.1028466817
Short name T319
Test name
Test status
Simulation time 322508003345 ps
CPU time 220.23 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:04:38 PM PDT 24
Peak memory 201928 kb
Host smart-620456a9-48b3-48ad-a9a0-1604dea8a7d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028466817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.1028466817
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.513675282
Short name T685
Test name
Test status
Simulation time 486992492285 ps
CPU time 243.13 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:05:00 PM PDT 24
Peak memory 201976 kb
Host smart-517d65ba-df4c-4155-9fcf-d9738c05950c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513675282 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.513675282
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2847218619
Short name T531
Test name
Test status
Simulation time 489934181873 ps
CPU time 1065.44 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:18:45 PM PDT 24
Peak memory 201872 kb
Host smart-50c56ee0-1d71-49fd-945e-6333ed6c88d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847218619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2847218619
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2156168623
Short name T283
Test name
Test status
Simulation time 492005837979 ps
CPU time 521.57 seconds
Started Jul 07 06:01:01 PM PDT 24
Finished Jul 07 06:09:43 PM PDT 24
Peak memory 201928 kb
Host smart-26de37d7-e4a5-4176-850e-9cf07cc8cc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156168623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2156168623
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2020801829
Short name T697
Test name
Test status
Simulation time 497764459750 ps
CPU time 187.77 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:04:08 PM PDT 24
Peak memory 201944 kb
Host smart-19f33e83-228f-459e-a9f5-c6ef6fcc81a6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020801829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2020801829
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.4195732840
Short name T483
Test name
Test status
Simulation time 608993881289 ps
CPU time 334.77 seconds
Started Jul 07 06:00:58 PM PDT 24
Finished Jul 07 06:06:33 PM PDT 24
Peak memory 201900 kb
Host smart-e6096274-dfb4-4646-9028-c3a535dfd671
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195732840 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.4195732840
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.571998367
Short name T104
Test name
Test status
Simulation time 98091234548 ps
CPU time 344.32 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:06:41 PM PDT 24
Peak memory 202284 kb
Host smart-c0304666-8853-4e91-b24c-7911ad96dd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571998367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.571998367
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2946626369
Short name T736
Test name
Test status
Simulation time 43932546914 ps
CPU time 99.29 seconds
Started Jul 07 06:00:57 PM PDT 24
Finished Jul 07 06:02:37 PM PDT 24
Peak memory 201696 kb
Host smart-f3785c15-a27d-4eba-b70c-e48a90dcb5e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946626369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2946626369
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.2263131841
Short name T661
Test name
Test status
Simulation time 3647521619 ps
CPU time 8.56 seconds
Started Jul 07 06:00:56 PM PDT 24
Finished Jul 07 06:01:05 PM PDT 24
Peak memory 201704 kb
Host smart-ff7e071c-4c37-44ce-affd-27b46ec2aeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263131841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.2263131841
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.53866412
Short name T397
Test name
Test status
Simulation time 5833966034 ps
CPU time 4.27 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:01:05 PM PDT 24
Peak memory 201684 kb
Host smart-55a56162-5cb3-4a72-a4d0-5c3032f43beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53866412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.53866412
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.2416623503
Short name T667
Test name
Test status
Simulation time 250556723028 ps
CPU time 507.88 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:09:28 PM PDT 24
Peak memory 202196 kb
Host smart-8f12616b-da19-499d-a3d2-c969ebbcd19b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416623503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all
.2416623503
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.855340336
Short name T575
Test name
Test status
Simulation time 450791852 ps
CPU time 1.17 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:01:02 PM PDT 24
Peak memory 201656 kb
Host smart-070c79af-871c-4dcd-88e9-6089b9aee21b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855340336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.855340336
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.2755508361
Short name T248
Test name
Test status
Simulation time 497869676169 ps
CPU time 276.48 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:05:37 PM PDT 24
Peak memory 201892 kb
Host smart-ea789a1f-7a28-4891-b9da-d90a1113bae6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755508361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.2755508361
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.3141253484
Short name T278
Test name
Test status
Simulation time 166243826476 ps
CPU time 96.65 seconds
Started Jul 07 06:01:04 PM PDT 24
Finished Jul 07 06:02:40 PM PDT 24
Peak memory 201900 kb
Host smart-e5132a44-e37b-413f-96f5-e222bc742b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141253484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.3141253484
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.1482619482
Short name T395
Test name
Test status
Simulation time 490675601234 ps
CPU time 606.7 seconds
Started Jul 07 06:01:04 PM PDT 24
Finished Jul 07 06:11:11 PM PDT 24
Peak memory 201856 kb
Host smart-22693a62-67aa-4fd3-9373-b42b3845bcc6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482619482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.1482619482
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.3356478465
Short name T323
Test name
Test status
Simulation time 165237004255 ps
CPU time 100.95 seconds
Started Jul 07 06:00:59 PM PDT 24
Finished Jul 07 06:02:41 PM PDT 24
Peak memory 201908 kb
Host smart-d6aa8537-4193-43aa-8320-adaf42f7b29b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356478465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.3356478465
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4040706997
Short name T147
Test name
Test status
Simulation time 336763777179 ps
CPU time 120.8 seconds
Started Jul 07 06:01:06 PM PDT 24
Finished Jul 07 06:03:07 PM PDT 24
Peak memory 201868 kb
Host smart-94d19ea5-28c1-4b4c-bf68-603cab4dcf50
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040706997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4040706997
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.4147481371
Short name T592
Test name
Test status
Simulation time 599284532479 ps
CPU time 323.76 seconds
Started Jul 07 06:01:04 PM PDT 24
Finished Jul 07 06:06:28 PM PDT 24
Peak memory 201912 kb
Host smart-81b477be-4c39-404c-8c53-734f1b851c6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147481371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.4147481371
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.587486364
Short name T752
Test name
Test status
Simulation time 201329065841 ps
CPU time 222.89 seconds
Started Jul 07 06:01:02 PM PDT 24
Finished Jul 07 06:04:46 PM PDT 24
Peak memory 201888 kb
Host smart-5dd92f1e-3978-4384-8e7d-c9fcfe98da5f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587486364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.587486364
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.2041820476
Short name T465
Test name
Test status
Simulation time 141297759960 ps
CPU time 508.79 seconds
Started Jul 07 06:01:00 PM PDT 24
Finished Jul 07 06:09:29 PM PDT 24
Peak memory 202300 kb
Host smart-e5570943-05ba-42f0-b7eb-735b22d098d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041820476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.2041820476
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.2881456148
Short name T352
Test name
Test status
Simulation time 35837059431 ps
CPU time 40.35 seconds
Started Jul 07 06:01:03 PM PDT 24
Finished Jul 07 06:01:44 PM PDT 24
Peak memory 201624 kb
Host smart-918cf507-109c-4871-88a7-4ea279db5630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881456148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.2881456148
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.2850550749
Short name T466
Test name
Test status
Simulation time 4680910831 ps
CPU time 5.38 seconds
Started Jul 07 06:01:01 PM PDT 24
Finished Jul 07 06:01:07 PM PDT 24
Peak memory 201692 kb
Host smart-7382c2c4-2cf4-4ecd-be76-4dac02fb15bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850550749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.2850550749
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2395260193
Short name T564
Test name
Test status
Simulation time 5737808430 ps
CPU time 14.45 seconds
Started Jul 07 06:01:01 PM PDT 24
Finished Jul 07 06:01:15 PM PDT 24
Peak memory 201700 kb
Host smart-bfb25471-2135-4ecd-a35e-f0b7c4c75096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395260193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2395260193
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.3463117008
Short name T214
Test name
Test status
Simulation time 246801370817 ps
CPU time 1181.91 seconds
Started Jul 07 06:01:04 PM PDT 24
Finished Jul 07 06:20:46 PM PDT 24
Peak memory 210436 kb
Host smart-1c5723a8-559e-47cc-8a5e-57b8319d62c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463117008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.3463117008
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.2940686280
Short name T579
Test name
Test status
Simulation time 162986750496 ps
CPU time 375.15 seconds
Started Jul 07 06:01:03 PM PDT 24
Finished Jul 07 06:07:18 PM PDT 24
Peak memory 217932 kb
Host smart-97e92b42-3245-4177-931a-5def9cfc270e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940686280 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.2940686280
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.1854672511
Short name T403
Test name
Test status
Simulation time 438247734 ps
CPU time 1.67 seconds
Started Jul 07 06:01:09 PM PDT 24
Finished Jul 07 06:01:11 PM PDT 24
Peak memory 201620 kb
Host smart-c1b8d3f9-37d7-4f8a-9b8a-108ce086a5e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854672511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.1854672511
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.1808641213
Short name T267
Test name
Test status
Simulation time 328814892480 ps
CPU time 525.55 seconds
Started Jul 07 06:01:09 PM PDT 24
Finished Jul 07 06:09:55 PM PDT 24
Peak memory 201876 kb
Host smart-227c26aa-e53d-45a1-8d42-c5147c14d2a4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808641213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.1808641213
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.4112730031
Short name T149
Test name
Test status
Simulation time 332506080647 ps
CPU time 163.02 seconds
Started Jul 07 06:01:05 PM PDT 24
Finished Jul 07 06:03:48 PM PDT 24
Peak memory 201892 kb
Host smart-2291171e-de05-4031-92f4-bd7f32a64cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112730031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.4112730031
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.1075659533
Short name T469
Test name
Test status
Simulation time 486838702559 ps
CPU time 296.7 seconds
Started Jul 07 06:01:08 PM PDT 24
Finished Jul 07 06:06:05 PM PDT 24
Peak memory 201920 kb
Host smart-13925e13-05f5-486d-ac12-0d610e115dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075659533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.1075659533
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3549306513
Short name T644
Test name
Test status
Simulation time 334269159018 ps
CPU time 796.09 seconds
Started Jul 07 06:01:06 PM PDT 24
Finished Jul 07 06:14:22 PM PDT 24
Peak memory 201888 kb
Host smart-14c9e482-6089-40b1-b789-7b12608c25fd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549306513 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3549306513
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.2377481912
Short name T568
Test name
Test status
Simulation time 162089092042 ps
CPU time 195.41 seconds
Started Jul 07 06:01:03 PM PDT 24
Finished Jul 07 06:04:18 PM PDT 24
Peak memory 201860 kb
Host smart-de9dad9a-404e-4a2b-8559-1f53cf6e43c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377481912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.2377481912
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.2673173574
Short name T420
Test name
Test status
Simulation time 328667833374 ps
CPU time 686.08 seconds
Started Jul 07 06:01:05 PM PDT 24
Finished Jul 07 06:12:31 PM PDT 24
Peak memory 201924 kb
Host smart-f38c962a-e9de-4356-92e4-9034a1bb036c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673173574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.2673173574
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2800185576
Short name T581
Test name
Test status
Simulation time 597532959792 ps
CPU time 666.04 seconds
Started Jul 07 06:01:04 PM PDT 24
Finished Jul 07 06:12:10 PM PDT 24
Peak memory 201888 kb
Host smart-0ba31b10-374a-4060-b526-df23b58b290c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800185576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2800185576
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2887962703
Short name T360
Test name
Test status
Simulation time 73369925563 ps
CPU time 264.44 seconds
Started Jul 07 06:01:12 PM PDT 24
Finished Jul 07 06:05:36 PM PDT 24
Peak memory 202172 kb
Host smart-1d7f3368-8a2a-43bf-bad4-4bc90c11f6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887962703 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2887962703
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.1989374426
Short name T374
Test name
Test status
Simulation time 45762321680 ps
CPU time 10.14 seconds
Started Jul 07 06:01:06 PM PDT 24
Finished Jul 07 06:01:16 PM PDT 24
Peak memory 201704 kb
Host smart-987fe010-7a20-4c78-af09-e715b12981cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989374426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.1989374426
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.67134951
Short name T720
Test name
Test status
Simulation time 4543304488 ps
CPU time 10.97 seconds
Started Jul 07 06:01:06 PM PDT 24
Finished Jul 07 06:01:17 PM PDT 24
Peak memory 201692 kb
Host smart-0877597c-e555-4d58-8614-4ff3021bb957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67134951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.67134951
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1216327220
Short name T109
Test name
Test status
Simulation time 5799362810 ps
CPU time 13.23 seconds
Started Jul 07 06:01:05 PM PDT 24
Finished Jul 07 06:01:18 PM PDT 24
Peak memory 201664 kb
Host smart-f20ce792-9ef5-43a6-bc08-b75ce80d0439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216327220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1216327220
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.4140323444
Short name T181
Test name
Test status
Simulation time 168011666846 ps
CPU time 92.94 seconds
Started Jul 07 06:01:12 PM PDT 24
Finished Jul 07 06:02:45 PM PDT 24
Peak memory 201996 kb
Host smart-018c17c1-fb04-4b48-ae1c-133d67e09717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140323444 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.4140323444
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.572795448
Short name T654
Test name
Test status
Simulation time 494737440 ps
CPU time 0.88 seconds
Started Jul 07 06:01:14 PM PDT 24
Finished Jul 07 06:01:15 PM PDT 24
Peak memory 201652 kb
Host smart-662d6a36-8d0d-450e-94a4-8179383f16d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572795448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.572795448
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2057535797
Short name T273
Test name
Test status
Simulation time 495144678471 ps
CPU time 427.89 seconds
Started Jul 07 06:01:09 PM PDT 24
Finished Jul 07 06:08:17 PM PDT 24
Peak memory 202236 kb
Host smart-6d1a115a-2f81-4d5c-8d3e-0c43f20e810c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057535797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2057535797
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.3300545773
Short name T573
Test name
Test status
Simulation time 494235581455 ps
CPU time 580.97 seconds
Started Jul 07 06:01:13 PM PDT 24
Finished Jul 07 06:10:55 PM PDT 24
Peak memory 201904 kb
Host smart-c9d24678-b497-4e3d-ba32-9f0ec484340e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300545773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.3300545773
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.1519753263
Short name T524
Test name
Test status
Simulation time 163418998221 ps
CPU time 94.13 seconds
Started Jul 07 06:01:08 PM PDT 24
Finished Jul 07 06:02:42 PM PDT 24
Peak memory 201900 kb
Host smart-bcb493bc-a5ba-4b74-93d0-8536a0bb9c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519753263 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.1519753263
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3057155779
Short name T583
Test name
Test status
Simulation time 165261333506 ps
CPU time 345.39 seconds
Started Jul 07 06:01:09 PM PDT 24
Finished Jul 07 06:06:54 PM PDT 24
Peak memory 201896 kb
Host smart-a990001a-638a-414c-b557-212a66cfdcc0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057155779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3057155779
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.155414854
Short name T312
Test name
Test status
Simulation time 165550221749 ps
CPU time 196.78 seconds
Started Jul 07 06:01:14 PM PDT 24
Finished Jul 07 06:04:32 PM PDT 24
Peak memory 201984 kb
Host smart-2bd3f452-907f-4abf-bd31-6611e749fc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155414854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.155414854
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.2527436920
Short name T706
Test name
Test status
Simulation time 488850154177 ps
CPU time 235.58 seconds
Started Jul 07 06:01:11 PM PDT 24
Finished Jul 07 06:05:07 PM PDT 24
Peak memory 201912 kb
Host smart-df9af9ac-8f45-40d7-ba1e-c7ad384c4080
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527436920 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.2527436920
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.1978815613
Short name T85
Test name
Test status
Simulation time 485922240940 ps
CPU time 104.52 seconds
Started Jul 07 06:01:13 PM PDT 24
Finished Jul 07 06:02:58 PM PDT 24
Peak memory 201916 kb
Host smart-ac429fe2-3cdb-4d7a-acfd-3569f476fdcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978815613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.1978815613
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1885317539
Short name T106
Test name
Test status
Simulation time 617728518970 ps
CPU time 387.35 seconds
Started Jul 07 06:01:13 PM PDT 24
Finished Jul 07 06:07:40 PM PDT 24
Peak memory 201856 kb
Host smart-9fc9cea4-4166-45de-9727-5a1f878d77e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885317539 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1885317539
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.4031076389
Short name T634
Test name
Test status
Simulation time 69828090176 ps
CPU time 252.56 seconds
Started Jul 07 06:01:09 PM PDT 24
Finished Jul 07 06:05:22 PM PDT 24
Peak memory 202220 kb
Host smart-f28fad13-65c9-40a7-8413-1cf93d1bcfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031076389 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.4031076389
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.407495032
Short name T437
Test name
Test status
Simulation time 30044745336 ps
CPU time 37.03 seconds
Started Jul 07 06:01:15 PM PDT 24
Finished Jul 07 06:01:52 PM PDT 24
Peak memory 201568 kb
Host smart-d806ca55-204f-4bb6-b94c-2da04b40abfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407495032 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.407495032
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1259535733
Short name T188
Test name
Test status
Simulation time 3666557590 ps
CPU time 2.9 seconds
Started Jul 07 06:01:08 PM PDT 24
Finished Jul 07 06:01:11 PM PDT 24
Peak memory 201680 kb
Host smart-fed2bda0-2a5c-4857-b046-0bdf7e5fd6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259535733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1259535733
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.562853048
Short name T380
Test name
Test status
Simulation time 5520120916 ps
CPU time 7.33 seconds
Started Jul 07 06:01:14 PM PDT 24
Finished Jul 07 06:01:22 PM PDT 24
Peak memory 201700 kb
Host smart-5ad6bd6f-1b4e-46ce-83f9-e7f66a361311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562853048 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.562853048
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.2770456748
Short name T325
Test name
Test status
Simulation time 370474100454 ps
CPU time 56.23 seconds
Started Jul 07 06:01:10 PM PDT 24
Finished Jul 07 06:02:06 PM PDT 24
Peak memory 201884 kb
Host smart-1aa9bcc8-f538-45d1-82c5-1f2ca3a092fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770456748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all
.2770456748
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.2383095878
Short name T288
Test name
Test status
Simulation time 132068689603 ps
CPU time 35.56 seconds
Started Jul 07 06:01:13 PM PDT 24
Finished Jul 07 06:01:49 PM PDT 24
Peak memory 210220 kb
Host smart-eb268e1b-8674-4e84-b235-9ee19ac37561
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383095878 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.2383095878
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.1527396109
Short name T475
Test name
Test status
Simulation time 388232329 ps
CPU time 0.89 seconds
Started Jul 07 06:00:33 PM PDT 24
Finished Jul 07 06:00:35 PM PDT 24
Peak memory 201696 kb
Host smart-a3ae59fe-b795-4acf-8bb1-b4c85028ed97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527396109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.1527396109
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1486537374
Short name T632
Test name
Test status
Simulation time 329402421724 ps
CPU time 384.76 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:07:00 PM PDT 24
Peak memory 201872 kb
Host smart-2ae1406d-adfe-4587-8d5a-32fd1289fb91
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486537374 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1486537374
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.608704386
Short name T178
Test name
Test status
Simulation time 325938048912 ps
CPU time 188.96 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:03:36 PM PDT 24
Peak memory 201940 kb
Host smart-80d1295b-eb98-4c87-bc0a-3d49db2a753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608704386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.608704386
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1875154866
Short name T728
Test name
Test status
Simulation time 491146754566 ps
CPU time 1147.91 seconds
Started Jul 07 06:00:30 PM PDT 24
Finished Jul 07 06:19:39 PM PDT 24
Peak memory 201960 kb
Host smart-8213702f-d9df-4889-b407-37cff226a73f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875154866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1875154866
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1869536866
Short name T624
Test name
Test status
Simulation time 388766779113 ps
CPU time 818.5 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:14:14 PM PDT 24
Peak memory 201820 kb
Host smart-a56ba152-5db4-427c-8959-62a220367062
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869536866 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1869536866
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.1962459044
Short name T413
Test name
Test status
Simulation time 194168757627 ps
CPU time 467.41 seconds
Started Jul 07 06:00:26 PM PDT 24
Finished Jul 07 06:08:14 PM PDT 24
Peak memory 201884 kb
Host smart-5d1b10ba-9b22-4f8b-a7af-c625dae4d602
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962459044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.1962459044
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.539425992
Short name T354
Test name
Test status
Simulation time 84517022409 ps
CPU time 302.23 seconds
Started Jul 07 06:00:33 PM PDT 24
Finished Jul 07 06:05:36 PM PDT 24
Peak memory 202240 kb
Host smart-ae013cac-f66e-4e0d-9b0c-a9f88aed4723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539425992 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.539425992
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.857492232
Short name T787
Test name
Test status
Simulation time 39365813755 ps
CPU time 10.89 seconds
Started Jul 07 06:00:29 PM PDT 24
Finished Jul 07 06:00:41 PM PDT 24
Peak memory 201736 kb
Host smart-7dffb9a1-2e21-4d1c-9f39-87828ebd1882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857492232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.857492232
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.360068548
Short name T419
Test name
Test status
Simulation time 5470251987 ps
CPU time 12.85 seconds
Started Jul 07 06:00:30 PM PDT 24
Finished Jul 07 06:00:43 PM PDT 24
Peak memory 201720 kb
Host smart-a0f4372a-503f-49c6-b837-5c98880e76ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360068548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.360068548
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.500039009
Short name T68
Test name
Test status
Simulation time 4212492677 ps
CPU time 9.82 seconds
Started Jul 07 06:00:34 PM PDT 24
Finished Jul 07 06:00:44 PM PDT 24
Peak memory 217116 kb
Host smart-13e54840-26df-4b88-ae7c-4efad6a5fcf1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500039009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.500039009
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.3216121138
Short name T432
Test name
Test status
Simulation time 5824970282 ps
CPU time 3.84 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:00:35 PM PDT 24
Peak memory 201704 kb
Host smart-51c641cb-92a1-42ea-b309-e77a8c934e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216121138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.3216121138
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.2227674340
Short name T280
Test name
Test status
Simulation time 328218294063 ps
CPU time 763 seconds
Started Jul 07 06:00:29 PM PDT 24
Finished Jul 07 06:13:12 PM PDT 24
Peak memory 201884 kb
Host smart-ea8d1fd1-9923-450c-88fa-822f94cd5f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227674340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
2227674340
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.2590508352
Short name T538
Test name
Test status
Simulation time 496882596 ps
CPU time 0.87 seconds
Started Jul 07 06:01:15 PM PDT 24
Finished Jul 07 06:01:16 PM PDT 24
Peak memory 201632 kb
Host smart-993f0c4d-c932-4432-ba49-804d81e90d47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590508352 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.2590508352
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.1015880616
Short name T175
Test name
Test status
Simulation time 593869562999 ps
CPU time 352.73 seconds
Started Jul 07 06:01:12 PM PDT 24
Finished Jul 07 06:07:05 PM PDT 24
Peak memory 201836 kb
Host smart-5fba6ab2-2c6e-4f2c-8a3c-bddd499f6ff6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015880616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gat
ing.1015880616
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.3943045111
Short name T29
Test name
Test status
Simulation time 352410551929 ps
CPU time 217.23 seconds
Started Jul 07 06:01:16 PM PDT 24
Finished Jul 07 06:04:53 PM PDT 24
Peak memory 201816 kb
Host smart-e917795c-f935-4653-9896-0da2ed434468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943045111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.3943045111
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.1661496334
Short name T749
Test name
Test status
Simulation time 167874301548 ps
CPU time 104.63 seconds
Started Jul 07 06:01:16 PM PDT 24
Finished Jul 07 06:03:01 PM PDT 24
Peak memory 201808 kb
Host smart-88a65df7-a339-4aab-9480-658122818223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661496334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.1661496334
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.3463123473
Short name T495
Test name
Test status
Simulation time 327825388532 ps
CPU time 383.03 seconds
Started Jul 07 06:01:11 PM PDT 24
Finished Jul 07 06:07:34 PM PDT 24
Peak memory 202160 kb
Host smart-ff0920d4-c7ba-4af3-8f94-8befe46a3c5a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463123473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.3463123473
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.803428921
Short name T786
Test name
Test status
Simulation time 166822422322 ps
CPU time 197.01 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:04:35 PM PDT 24
Peak memory 201924 kb
Host smart-23f7a554-73b8-44f3-ae8a-afbeb48dac78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803428921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.803428921
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1195828212
Short name T715
Test name
Test status
Simulation time 329015245423 ps
CPU time 188.63 seconds
Started Jul 07 06:01:16 PM PDT 24
Finished Jul 07 06:04:25 PM PDT 24
Peak memory 201856 kb
Host smart-2a5740d0-4569-4d3c-afaa-4dd58659e212
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195828212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1195828212
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.1082140307
Short name T606
Test name
Test status
Simulation time 187861139686 ps
CPU time 64.91 seconds
Started Jul 07 06:01:16 PM PDT 24
Finished Jul 07 06:02:21 PM PDT 24
Peak memory 201916 kb
Host smart-4b08fb58-e692-45f6-a15d-a7b9e13210bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082140307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.1082140307
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1084734463
Short name T383
Test name
Test status
Simulation time 605802114717 ps
CPU time 703.19 seconds
Started Jul 07 06:01:14 PM PDT 24
Finished Jul 07 06:12:58 PM PDT 24
Peak memory 201944 kb
Host smart-c34e85ab-335d-4c37-b138-5110e28681e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084734463 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1084734463
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.617798610
Short name T163
Test name
Test status
Simulation time 118059104524 ps
CPU time 649.02 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:12:06 PM PDT 24
Peak memory 202232 kb
Host smart-73c30337-7602-4e2f-b446-5e3e0a5d5715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617798610 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.617798610
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.591692276
Short name T709
Test name
Test status
Simulation time 24371275562 ps
CPU time 24.64 seconds
Started Jul 07 06:01:16 PM PDT 24
Finished Jul 07 06:01:41 PM PDT 24
Peak memory 201700 kb
Host smart-e834e7d0-be86-4c7f-9c86-f510d9bba83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591692276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.591692276
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1450201804
Short name T733
Test name
Test status
Simulation time 4211081410 ps
CPU time 10.86 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:01:28 PM PDT 24
Peak memory 201716 kb
Host smart-1126ce41-b12e-4d94-a74a-375f913401fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450201804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1450201804
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.1644793546
Short name T488
Test name
Test status
Simulation time 5940264514 ps
CPU time 4.34 seconds
Started Jul 07 06:01:15 PM PDT 24
Finished Jul 07 06:01:20 PM PDT 24
Peak memory 201560 kb
Host smart-6bbe4c2e-7b5f-4536-8720-3c7a1c59fcc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644793546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.1644793546
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.2614276579
Short name T3
Test name
Test status
Simulation time 110073850882 ps
CPU time 123.55 seconds
Started Jul 07 06:01:15 PM PDT 24
Finished Jul 07 06:03:19 PM PDT 24
Peak memory 210208 kb
Host smart-fe2aec95-6231-4aa1-9671-46b58536eadc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614276579 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.2614276579
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.3968533365
Short name T468
Test name
Test status
Simulation time 386971603 ps
CPU time 1.48 seconds
Started Jul 07 06:01:23 PM PDT 24
Finished Jul 07 06:01:24 PM PDT 24
Peak memory 201656 kb
Host smart-5ba7ac9c-8082-4e2f-a116-ca0a02b7b9f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968533365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.3968533365
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.1801536112
Short name T723
Test name
Test status
Simulation time 179628878419 ps
CPU time 101.74 seconds
Started Jul 07 06:01:21 PM PDT 24
Finished Jul 07 06:03:04 PM PDT 24
Peak memory 201900 kb
Host smart-d45800c5-b8f4-44d8-a4de-313de1be7dcb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801536112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.1801536112
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.2386938799
Short name T238
Test name
Test status
Simulation time 163450054640 ps
CPU time 365.05 seconds
Started Jul 07 06:01:20 PM PDT 24
Finished Jul 07 06:07:25 PM PDT 24
Peak memory 201908 kb
Host smart-c73f8eea-94a7-4d42-b7bf-fb8d9dcd5716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386938799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.2386938799
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2907624556
Short name T93
Test name
Test status
Simulation time 495479734513 ps
CPU time 1163.07 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:20:41 PM PDT 24
Peak memory 201868 kb
Host smart-ca82b829-f1d2-42c3-8946-5802a8332a43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907624556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2907624556
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1245172166
Short name T790
Test name
Test status
Simulation time 330720099367 ps
CPU time 191.11 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:04:29 PM PDT 24
Peak memory 201912 kb
Host smart-5faa4556-76d9-4792-8e6e-da3645c38aaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245172166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1245172166
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1943122223
Short name T698
Test name
Test status
Simulation time 323052051940 ps
CPU time 318.8 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:06:36 PM PDT 24
Peak memory 201900 kb
Host smart-a846adf0-2d34-4917-9d44-04bddec1ac94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943122223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1943122223
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3157481560
Short name T767
Test name
Test status
Simulation time 385539028935 ps
CPU time 948.11 seconds
Started Jul 07 06:01:20 PM PDT 24
Finished Jul 07 06:17:09 PM PDT 24
Peak memory 201980 kb
Host smart-4b233112-01cb-4440-85f0-e2d56cc1175e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157481560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3157481560
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3424452950
Short name T39
Test name
Test status
Simulation time 403484240316 ps
CPU time 223.79 seconds
Started Jul 07 06:01:17 PM PDT 24
Finished Jul 07 06:05:01 PM PDT 24
Peak memory 201872 kb
Host smart-d8bb2057-525c-45bc-bc46-1871f367289b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424452950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3424452950
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.222700643
Short name T342
Test name
Test status
Simulation time 132911453088 ps
CPU time 498.96 seconds
Started Jul 07 06:01:21 PM PDT 24
Finished Jul 07 06:09:40 PM PDT 24
Peak memory 202240 kb
Host smart-5b525cae-dbbe-44b1-9550-0543a5353bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222700643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.222700643
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.197919544
Short name T703
Test name
Test status
Simulation time 42833961838 ps
CPU time 92.52 seconds
Started Jul 07 06:01:23 PM PDT 24
Finished Jul 07 06:02:55 PM PDT 24
Peak memory 201704 kb
Host smart-c0c01ad8-99e0-46b9-9a83-716671e9ce3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197919544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.197919544
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2217518908
Short name T116
Test name
Test status
Simulation time 3250387982 ps
CPU time 4.59 seconds
Started Jul 07 06:01:22 PM PDT 24
Finished Jul 07 06:01:27 PM PDT 24
Peak memory 201696 kb
Host smart-15777816-6773-462e-b2d6-ce995e78377c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217518908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2217518908
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.4232250821
Short name T636
Test name
Test status
Simulation time 6000720397 ps
CPU time 13 seconds
Started Jul 07 06:01:19 PM PDT 24
Finished Jul 07 06:01:32 PM PDT 24
Peak memory 201708 kb
Host smart-b634b8c5-fcb7-4b43-81ae-cde1c9a536a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232250821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.4232250821
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.3792746039
Short name T543
Test name
Test status
Simulation time 5517139687 ps
CPU time 3.79 seconds
Started Jul 07 06:01:23 PM PDT 24
Finished Jul 07 06:01:27 PM PDT 24
Peak memory 201708 kb
Host smart-68c9e9f1-8088-434d-bbbc-8d8b11e2035d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792746039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.3792746039
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.3586113803
Short name T519
Test name
Test status
Simulation time 443518687059 ps
CPU time 98 seconds
Started Jul 07 06:01:21 PM PDT 24
Finished Jul 07 06:03:00 PM PDT 24
Peak memory 202028 kb
Host smart-88b802bd-b961-473d-a0e7-1a1fcee182e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586113803 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.3586113803
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2822301484
Short name T489
Test name
Test status
Simulation time 379547495 ps
CPU time 1.42 seconds
Started Jul 07 06:01:29 PM PDT 24
Finished Jul 07 06:01:31 PM PDT 24
Peak memory 201592 kb
Host smart-935724ff-6d0c-47c3-92a9-b4dcf05b398f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822301484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2822301484
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1302693746
Short name T265
Test name
Test status
Simulation time 181748421633 ps
CPU time 310.2 seconds
Started Jul 07 06:01:27 PM PDT 24
Finished Jul 07 06:06:37 PM PDT 24
Peak memory 201940 kb
Host smart-599f51f6-7d35-4df4-9b8e-33566bdd067e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302693746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1302693746
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3919971973
Short name T705
Test name
Test status
Simulation time 331397497806 ps
CPU time 775.81 seconds
Started Jul 07 06:01:22 PM PDT 24
Finished Jul 07 06:14:18 PM PDT 24
Peak memory 201892 kb
Host smart-78706e17-4a63-4f23-afe0-6f8d2e2e0698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919971973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3919971973
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2572849119
Short name T415
Test name
Test status
Simulation time 487615186772 ps
CPU time 293.56 seconds
Started Jul 07 06:01:24 PM PDT 24
Finished Jul 07 06:06:18 PM PDT 24
Peak memory 201872 kb
Host smart-6e639172-83c1-4fc8-892f-c19bbfea8ac0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572849119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2572849119
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1481186715
Short name T441
Test name
Test status
Simulation time 492601255684 ps
CPU time 511.82 seconds
Started Jul 07 06:01:26 PM PDT 24
Finished Jul 07 06:09:58 PM PDT 24
Peak memory 201992 kb
Host smart-10e99d69-b1d7-4d39-8821-b475571612e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481186715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1481186715
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.3328679549
Short name T648
Test name
Test status
Simulation time 158964168218 ps
CPU time 93.62 seconds
Started Jul 07 06:01:22 PM PDT 24
Finished Jul 07 06:02:55 PM PDT 24
Peak memory 201908 kb
Host smart-fec93f8e-219c-4fa5-a5c7-69b2dfa920d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328679549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.3328679549
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.4071606681
Short name T496
Test name
Test status
Simulation time 354084386727 ps
CPU time 814.22 seconds
Started Jul 07 06:01:27 PM PDT 24
Finished Jul 07 06:15:02 PM PDT 24
Peak memory 201928 kb
Host smart-2f8180a3-bbde-4d9a-b42e-a538d11fc91d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071606681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.4071606681
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.869501670
Short name T761
Test name
Test status
Simulation time 396451654660 ps
CPU time 260.49 seconds
Started Jul 07 06:01:26 PM PDT 24
Finished Jul 07 06:05:47 PM PDT 24
Peak memory 201884 kb
Host smart-777b0584-2332-4711-ac8d-adbbf9601066
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869501670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.869501670
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.1161245380
Short name T750
Test name
Test status
Simulation time 112357957097 ps
CPU time 388.54 seconds
Started Jul 07 06:01:29 PM PDT 24
Finished Jul 07 06:07:58 PM PDT 24
Peak memory 202116 kb
Host smart-ea237230-83c8-4820-8d74-6646da2f0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161245380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.1161245380
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.221320109
Short name T503
Test name
Test status
Simulation time 23990064744 ps
CPU time 15.46 seconds
Started Jul 07 06:01:30 PM PDT 24
Finished Jul 07 06:01:45 PM PDT 24
Peak memory 201644 kb
Host smart-7619d2d9-142e-4cc2-b545-be323aefe788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221320109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.221320109
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.577306773
Short name T589
Test name
Test status
Simulation time 5041903904 ps
CPU time 6.01 seconds
Started Jul 07 06:01:29 PM PDT 24
Finished Jul 07 06:01:35 PM PDT 24
Peak memory 201664 kb
Host smart-356ea99d-a326-4178-9052-867205d1c781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577306773 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.577306773
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.2911020810
Short name T111
Test name
Test status
Simulation time 5814263147 ps
CPU time 13.38 seconds
Started Jul 07 06:01:27 PM PDT 24
Finished Jul 07 06:01:41 PM PDT 24
Peak memory 201736 kb
Host smart-eb7b7f72-c0d6-4c05-8d8d-dce4b4bea572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911020810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.2911020810
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.624566775
Short name T372
Test name
Test status
Simulation time 58805998250 ps
CPU time 19.58 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:01:50 PM PDT 24
Peak memory 201696 kb
Host smart-c1a76f1c-c1ea-4beb-8818-c116caf16b57
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624566775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all.
624566775
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.2849912564
Short name T19
Test name
Test status
Simulation time 38529168650 ps
CPU time 92.67 seconds
Started Jul 07 06:01:27 PM PDT 24
Finished Jul 07 06:02:59 PM PDT 24
Peak memory 210528 kb
Host smart-ac42e60c-ef17-4c12-a4e9-fbd8c9b54119
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849912564 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.2849912564
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.3466867911
Short name T547
Test name
Test status
Simulation time 339921336 ps
CPU time 0.75 seconds
Started Jul 07 06:01:34 PM PDT 24
Finished Jul 07 06:01:35 PM PDT 24
Peak memory 201684 kb
Host smart-f0638b3b-55a2-4459-a113-722d3b3ee39b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466867911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.3466867911
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2203142819
Short name T584
Test name
Test status
Simulation time 163524563074 ps
CPU time 87.37 seconds
Started Jul 07 06:01:30 PM PDT 24
Finished Jul 07 06:02:58 PM PDT 24
Peak memory 201840 kb
Host smart-e893ebe9-6d28-4215-a64a-16c3feefcea6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203142819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2203142819
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.2577896944
Short name T751
Test name
Test status
Simulation time 498183151130 ps
CPU time 1105.76 seconds
Started Jul 07 06:01:32 PM PDT 24
Finished Jul 07 06:19:58 PM PDT 24
Peak memory 201916 kb
Host smart-dae6129f-ce91-402b-ad16-d56878d9e76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577896944 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.2577896944
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.903736748
Short name T353
Test name
Test status
Simulation time 168730007653 ps
CPU time 379.84 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:07:51 PM PDT 24
Peak memory 201852 kb
Host smart-dd1a2e46-3051-456d-85b9-ab9abe3416ff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=903736748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrup
t_fixed.903736748
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.3819760799
Short name T576
Test name
Test status
Simulation time 167420388236 ps
CPU time 376.29 seconds
Started Jul 07 06:01:30 PM PDT 24
Finished Jul 07 06:07:46 PM PDT 24
Peak memory 201944 kb
Host smart-42926563-e989-407a-b01f-7fb3a37ee9f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819760799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.3819760799
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.1448651431
Short name T9
Test name
Test status
Simulation time 492505896675 ps
CPU time 298.91 seconds
Started Jul 07 06:01:34 PM PDT 24
Finished Jul 07 06:06:34 PM PDT 24
Peak memory 201852 kb
Host smart-2b7b85ba-f9e2-45d5-9685-3e5ff28895e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448651431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.1448651431
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.1629401736
Short name T142
Test name
Test status
Simulation time 531625616989 ps
CPU time 73.71 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:02:45 PM PDT 24
Peak memory 201868 kb
Host smart-d40ba051-fbfd-4087-beb4-c438648f4ec1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629401736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.1629401736
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.412626945
Short name T484
Test name
Test status
Simulation time 409936894768 ps
CPU time 851.1 seconds
Started Jul 07 06:01:33 PM PDT 24
Finished Jul 07 06:15:44 PM PDT 24
Peak memory 201900 kb
Host smart-ddaa7bfa-1991-4366-851c-b0d7fb15a61f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412626945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.
adc_ctrl_filters_wakeup_fixed.412626945
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.627128981
Short name T94
Test name
Test status
Simulation time 108536841347 ps
CPU time 374.94 seconds
Started Jul 07 06:01:32 PM PDT 24
Finished Jul 07 06:07:47 PM PDT 24
Peak memory 202100 kb
Host smart-33d81b5c-948c-4fd4-b0e5-0f6aff609c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627128981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.627128981
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1671777484
Short name T486
Test name
Test status
Simulation time 37252138418 ps
CPU time 8.18 seconds
Started Jul 07 06:01:30 PM PDT 24
Finished Jul 07 06:01:39 PM PDT 24
Peak memory 201724 kb
Host smart-fe99cea3-49cf-449e-9fbe-58106d5afd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671777484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1671777484
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.2526761035
Short name T535
Test name
Test status
Simulation time 5082578173 ps
CPU time 1.51 seconds
Started Jul 07 06:01:34 PM PDT 24
Finished Jul 07 06:01:36 PM PDT 24
Peak memory 201700 kb
Host smart-0e09bd62-df38-4d2a-b4b1-a5a91c3f1efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526761035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.2526761035
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.2418532428
Short name T445
Test name
Test status
Simulation time 5974046474 ps
CPU time 6.43 seconds
Started Jul 07 06:01:27 PM PDT 24
Finished Jul 07 06:01:33 PM PDT 24
Peak memory 201712 kb
Host smart-02fd3232-5c68-4a0b-bc8d-3d8e61dcbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418532428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.2418532428
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.2054086785
Short name T463
Test name
Test status
Simulation time 170881888933 ps
CPU time 401.38 seconds
Started Jul 07 06:01:33 PM PDT 24
Finished Jul 07 06:08:14 PM PDT 24
Peak memory 201780 kb
Host smart-c3cccb19-43ac-4e9e-9725-742a38be0fb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054086785 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all
.2054086785
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.4158504198
Short name T307
Test name
Test status
Simulation time 465050183028 ps
CPU time 174.33 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:04:26 PM PDT 24
Peak memory 202056 kb
Host smart-92293452-2d8c-49e7-a6f0-d02f40cb36e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158504198 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.4158504198
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.3487374027
Short name T61
Test name
Test status
Simulation time 499620104 ps
CPU time 0.88 seconds
Started Jul 07 06:01:36 PM PDT 24
Finished Jul 07 06:01:37 PM PDT 24
Peak memory 201648 kb
Host smart-0bf064d5-dcae-4082-a9a9-35c2cb7a6715
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487374027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.3487374027
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.226011626
Short name T594
Test name
Test status
Simulation time 163284996865 ps
CPU time 344.17 seconds
Started Jul 07 06:01:38 PM PDT 24
Finished Jul 07 06:07:22 PM PDT 24
Peak memory 201936 kb
Host smart-4816de81-bdd4-4391-b929-8e93d6276bf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226011626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gati
ng.226011626
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1940628550
Short name T264
Test name
Test status
Simulation time 166796340986 ps
CPU time 403.87 seconds
Started Jul 07 06:01:33 PM PDT 24
Finished Jul 07 06:08:17 PM PDT 24
Peak memory 201960 kb
Host smart-f044451d-51b0-44ee-a787-398af7344f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940628550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1940628550
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.837935246
Short name T595
Test name
Test status
Simulation time 157617284917 ps
CPU time 182.18 seconds
Started Jul 07 06:01:29 PM PDT 24
Finished Jul 07 06:04:32 PM PDT 24
Peak memory 201808 kb
Host smart-5660e2a2-bf47-4019-9870-9f435d25fc1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=837935246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrup
t_fixed.837935246
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2084551685
Short name T509
Test name
Test status
Simulation time 164727226494 ps
CPU time 39.27 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:02:10 PM PDT 24
Peak memory 201932 kb
Host smart-1d7a425d-562e-414b-bf3a-1dfee971fe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084551685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2084551685
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.4230642107
Short name T617
Test name
Test status
Simulation time 325303217683 ps
CPU time 623.87 seconds
Started Jul 07 06:01:31 PM PDT 24
Finished Jul 07 06:11:56 PM PDT 24
Peak memory 202148 kb
Host smart-ab8bd7cc-b31a-4ba8-bfa5-c95c9d1664b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230642107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.4230642107
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.334845987
Short name T301
Test name
Test status
Simulation time 199974630556 ps
CPU time 112.13 seconds
Started Jul 07 06:01:38 PM PDT 24
Finished Jul 07 06:03:31 PM PDT 24
Peak memory 201936 kb
Host smart-a0b0585b-e9dd-4770-9760-566145f30496
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334845987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.334845987
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.4259231305
Short name T610
Test name
Test status
Simulation time 206113289601 ps
CPU time 94.46 seconds
Started Jul 07 06:01:40 PM PDT 24
Finished Jul 07 06:03:15 PM PDT 24
Peak memory 201828 kb
Host smart-655be969-8abc-4444-b659-2b8c0b61e1f0
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259231305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24
.adc_ctrl_filters_wakeup_fixed.4259231305
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4203789233
Short name T200
Test name
Test status
Simulation time 123079101655 ps
CPU time 708.23 seconds
Started Jul 07 06:01:34 PM PDT 24
Finished Jul 07 06:13:23 PM PDT 24
Peak memory 202284 kb
Host smart-f2ae93a8-eb0d-4226-86f7-4f3f305a8812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203789233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4203789233
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.4125944080
Short name T618
Test name
Test status
Simulation time 39348590509 ps
CPU time 77.63 seconds
Started Jul 07 06:01:40 PM PDT 24
Finished Jul 07 06:02:58 PM PDT 24
Peak memory 201708 kb
Host smart-d8285f02-dd0c-4b36-aa19-284c8d8ad76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125944080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.4125944080
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.1205914627
Short name T368
Test name
Test status
Simulation time 5248253492 ps
CPU time 4.04 seconds
Started Jul 07 06:01:42 PM PDT 24
Finished Jul 07 06:01:46 PM PDT 24
Peak memory 201656 kb
Host smart-ab21f20e-833a-49b4-95f9-122a84f86284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205914627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.1205914627
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2003918
Short name T440
Test name
Test status
Simulation time 5868334721 ps
CPU time 14.35 seconds
Started Jul 07 06:01:34 PM PDT 24
Finished Jul 07 06:01:49 PM PDT 24
Peak memory 201708 kb
Host smart-669a5269-8323-4096-a961-f4af88ccc270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2003918
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.4234820479
Short name T24
Test name
Test status
Simulation time 152873454067 ps
CPU time 651.45 seconds
Started Jul 07 06:01:37 PM PDT 24
Finished Jul 07 06:12:29 PM PDT 24
Peak memory 202252 kb
Host smart-04a1a181-cb07-4572-8e80-3eb26edde267
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234820479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.4234820479
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.2878429934
Short name T517
Test name
Test status
Simulation time 72088658939 ps
CPU time 135.65 seconds
Started Jul 07 06:01:37 PM PDT 24
Finished Jul 07 06:03:53 PM PDT 24
Peak memory 210476 kb
Host smart-e5a1e6d9-582b-42fd-adcf-ab19e2bbd995
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878429934 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.2878429934
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.44720911
Short name T490
Test name
Test status
Simulation time 398620777 ps
CPU time 0.87 seconds
Started Jul 07 06:01:39 PM PDT 24
Finished Jul 07 06:01:40 PM PDT 24
Peak memory 201676 kb
Host smart-9f2ee24f-de01-467d-bad5-4d53b75269a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44720911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.44720911
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2721243409
Short name T740
Test name
Test status
Simulation time 163145631282 ps
CPU time 174.4 seconds
Started Jul 07 06:01:42 PM PDT 24
Finished Jul 07 06:04:37 PM PDT 24
Peak memory 201844 kb
Host smart-de80f864-1353-4de3-a813-14623a6a0b0d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721243409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2721243409
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2608295899
Short name T224
Test name
Test status
Simulation time 166608439508 ps
CPU time 376.84 seconds
Started Jul 07 06:01:44 PM PDT 24
Finished Jul 07 06:08:01 PM PDT 24
Peak memory 201912 kb
Host smart-8000c9f5-c820-48d2-97ef-4d0ccbf79f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608295899 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2608295899
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.61535713
Short name T274
Test name
Test status
Simulation time 486950292314 ps
CPU time 92.62 seconds
Started Jul 07 06:01:35 PM PDT 24
Finished Jul 07 06:03:08 PM PDT 24
Peak memory 201916 kb
Host smart-3f1ac76a-6703-4c6b-8c7c-29e7ad5c53fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61535713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.61535713
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.3099074836
Short name T574
Test name
Test status
Simulation time 327615028128 ps
CPU time 202.13 seconds
Started Jul 07 06:01:40 PM PDT 24
Finished Jul 07 06:05:02 PM PDT 24
Peak memory 201868 kb
Host smart-91b6fdb8-d7d2-439c-aa03-5f0396256e51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099074836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.3099074836
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.1669494872
Short name T393
Test name
Test status
Simulation time 169299655668 ps
CPU time 23.97 seconds
Started Jul 07 06:01:34 PM PDT 24
Finished Jul 07 06:01:58 PM PDT 24
Peak memory 201972 kb
Host smart-5cded156-aeb6-485d-86e0-e8f10f746615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669494872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.1669494872
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.804688304
Short name T98
Test name
Test status
Simulation time 323761583524 ps
CPU time 577.11 seconds
Started Jul 07 06:01:40 PM PDT 24
Finished Jul 07 06:11:17 PM PDT 24
Peak memory 201948 kb
Host smart-013540fe-634b-4a21-ab56-352461679836
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=804688304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fixe
d.804688304
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1276906560
Short name T309
Test name
Test status
Simulation time 358915120344 ps
CPU time 435.07 seconds
Started Jul 07 06:01:37 PM PDT 24
Finished Jul 07 06:08:52 PM PDT 24
Peak memory 202176 kb
Host smart-db8cba8c-31aa-4908-a9b0-31a54f9fb82b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276906560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1276906560
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.4100096685
Short name T500
Test name
Test status
Simulation time 398890659454 ps
CPU time 56.22 seconds
Started Jul 07 06:01:39 PM PDT 24
Finished Jul 07 06:02:36 PM PDT 24
Peak memory 201876 kb
Host smart-e8be9afc-63e0-459f-b52d-19ce96b9b846
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100096685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.4100096685
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.1841696882
Short name T537
Test name
Test status
Simulation time 112386050896 ps
CPU time 444.91 seconds
Started Jul 07 06:01:42 PM PDT 24
Finished Jul 07 06:09:07 PM PDT 24
Peak memory 202084 kb
Host smart-94d4d668-a92e-4d00-b42a-aca16e587156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841696882 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.1841696882
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2126045749
Short name T609
Test name
Test status
Simulation time 27927381955 ps
CPU time 66.03 seconds
Started Jul 07 06:01:38 PM PDT 24
Finished Jul 07 06:02:45 PM PDT 24
Peak memory 201708 kb
Host smart-689645af-b86b-417b-8ca4-cbae41f9d861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126045749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2126045749
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.546275480
Short name T608
Test name
Test status
Simulation time 5065144141 ps
CPU time 12.42 seconds
Started Jul 07 06:01:41 PM PDT 24
Finished Jul 07 06:01:53 PM PDT 24
Peak memory 201708 kb
Host smart-1f0a5854-1c5f-4f2f-9b24-d5e83036ff92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=546275480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.546275480
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.526166249
Short name T482
Test name
Test status
Simulation time 5779237768 ps
CPU time 4.08 seconds
Started Jul 07 06:01:36 PM PDT 24
Finished Jul 07 06:01:40 PM PDT 24
Peak memory 201696 kb
Host smart-79d1eb93-682d-45f6-9b8b-1b8c5be99a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526166249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.526166249
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2763171525
Short name T33
Test name
Test status
Simulation time 43054967752 ps
CPU time 91.95 seconds
Started Jul 07 06:01:41 PM PDT 24
Finished Jul 07 06:03:13 PM PDT 24
Peak memory 210608 kb
Host smart-5200c49d-9bda-49b2-b95a-10f803f6da33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763171525 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2763171525
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1912916266
Short name T525
Test name
Test status
Simulation time 521581026 ps
CPU time 1.19 seconds
Started Jul 07 06:01:48 PM PDT 24
Finished Jul 07 06:01:50 PM PDT 24
Peak memory 201584 kb
Host smart-be240bd1-2aa6-4e16-bb2d-cff66a833ac4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912916266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1912916266
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.2230828984
Short name T97
Test name
Test status
Simulation time 538882105414 ps
CPU time 1145.72 seconds
Started Jul 07 06:01:43 PM PDT 24
Finished Jul 07 06:20:49 PM PDT 24
Peak memory 201972 kb
Host smart-38ada256-43a2-4b9e-926f-43061fc9022b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230828984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.2230828984
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.1778685375
Short name T456
Test name
Test status
Simulation time 164282270708 ps
CPU time 372.13 seconds
Started Jul 07 06:01:44 PM PDT 24
Finished Jul 07 06:07:56 PM PDT 24
Peak memory 201912 kb
Host smart-dcd2b465-6b6f-45d7-b8c6-ea8f36e04723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778685375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.1778685375
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.3108166915
Short name T401
Test name
Test status
Simulation time 496470983809 ps
CPU time 177.88 seconds
Started Jul 07 06:01:45 PM PDT 24
Finished Jul 07 06:04:43 PM PDT 24
Peak memory 201784 kb
Host smart-462ef449-d533-48bd-b505-0a52a071138d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108166915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.3108166915
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3221900177
Short name T476
Test name
Test status
Simulation time 323070193396 ps
CPU time 189.24 seconds
Started Jul 07 06:01:43 PM PDT 24
Finished Jul 07 06:04:52 PM PDT 24
Peak memory 201968 kb
Host smart-b8f62516-712c-4193-9d62-76be8fecf26f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221900177 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3221900177
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.965773468
Short name T351
Test name
Test status
Simulation time 325836020088 ps
CPU time 469.72 seconds
Started Jul 07 06:01:42 PM PDT 24
Finished Jul 07 06:09:32 PM PDT 24
Peak memory 202144 kb
Host smart-0d8e8518-f578-42ec-8d4d-5a085fd66980
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=965773468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fixe
d.965773468
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.202310634
Short name T184
Test name
Test status
Simulation time 372784579440 ps
CPU time 91.96 seconds
Started Jul 07 06:01:46 PM PDT 24
Finished Jul 07 06:03:18 PM PDT 24
Peak memory 201904 kb
Host smart-55c349f0-3344-4ab9-aebb-af41e362cfda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202310634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_
wakeup.202310634
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.1473207230
Short name T385
Test name
Test status
Simulation time 622473149004 ps
CPU time 1344.11 seconds
Started Jul 07 06:01:47 PM PDT 24
Finished Jul 07 06:24:11 PM PDT 24
Peak memory 201928 kb
Host smart-8917f1c0-2400-4a06-afec-c7b0dfd8b13b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473207230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.1473207230
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2868879474
Short name T460
Test name
Test status
Simulation time 42745999471 ps
CPU time 50.3 seconds
Started Jul 07 06:01:43 PM PDT 24
Finished Jul 07 06:02:33 PM PDT 24
Peak memory 201712 kb
Host smart-2e40e490-33d4-4f7d-85a4-017a2b72bcf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868879474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2868879474
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.3433687544
Short name T590
Test name
Test status
Simulation time 3621875396 ps
CPU time 5.24 seconds
Started Jul 07 06:01:43 PM PDT 24
Finished Jul 07 06:01:48 PM PDT 24
Peak memory 201680 kb
Host smart-dd47ce22-7d2a-4969-ac98-930fb707b95b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433687544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.3433687544
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.678348114
Short name T453
Test name
Test status
Simulation time 5788565880 ps
CPU time 9.58 seconds
Started Jul 07 06:01:44 PM PDT 24
Finished Jul 07 06:01:53 PM PDT 24
Peak memory 201708 kb
Host smart-aad49786-3648-4e27-9986-1a921a13dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678348114 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.678348114
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2216675837
Short name T261
Test name
Test status
Simulation time 209066124336 ps
CPU time 128.78 seconds
Started Jul 07 06:01:45 PM PDT 24
Finished Jul 07 06:03:54 PM PDT 24
Peak memory 201868 kb
Host smart-b699ed73-620d-48da-a21d-9785ad046b76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216675837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2216675837
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2250764015
Short name T20
Test name
Test status
Simulation time 359696126747 ps
CPU time 43.23 seconds
Started Jul 07 06:01:46 PM PDT 24
Finished Jul 07 06:02:30 PM PDT 24
Peak memory 210540 kb
Host smart-49564547-a548-4f41-89b2-2c8b1cd1407e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250764015 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2250764015
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.3302321985
Short name T362
Test name
Test status
Simulation time 490481177 ps
CPU time 1.75 seconds
Started Jul 07 06:01:56 PM PDT 24
Finished Jul 07 06:01:58 PM PDT 24
Peak memory 201512 kb
Host smart-aa71ce7b-eaeb-4f83-bb18-633d2d42414b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302321985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.3302321985
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.2333569076
Short name T662
Test name
Test status
Simulation time 333458931331 ps
CPU time 482.87 seconds
Started Jul 07 06:01:52 PM PDT 24
Finished Jul 07 06:09:55 PM PDT 24
Peak memory 201868 kb
Host smart-acf55147-f02e-4357-a7e0-8687bd061a19
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333569076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.2333569076
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.2355569250
Short name T156
Test name
Test status
Simulation time 346235114254 ps
CPU time 369.47 seconds
Started Jul 07 06:01:54 PM PDT 24
Finished Jul 07 06:08:03 PM PDT 24
Peak memory 201896 kb
Host smart-221bbb0b-32d1-4ddc-821f-ab6f603ddc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355569250 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.2355569250
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2245711162
Short name T220
Test name
Test status
Simulation time 168860339075 ps
CPU time 100 seconds
Started Jul 07 06:01:52 PM PDT 24
Finished Jul 07 06:03:32 PM PDT 24
Peak memory 201888 kb
Host smart-140747b4-82a7-4a12-8baa-c0f68affb5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245711162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2245711162
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.2043030424
Short name T551
Test name
Test status
Simulation time 328144906439 ps
CPU time 759.14 seconds
Started Jul 07 06:01:46 PM PDT 24
Finished Jul 07 06:14:25 PM PDT 24
Peak memory 201848 kb
Host smart-5fa95100-6f17-47db-a6e0-36db6b443077
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043030424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.2043030424
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3517484190
Short name T458
Test name
Test status
Simulation time 161371759720 ps
CPU time 90.84 seconds
Started Jul 07 06:01:46 PM PDT 24
Finished Jul 07 06:03:17 PM PDT 24
Peak memory 201944 kb
Host smart-20490912-06e3-4437-a4a8-ba122cac3d93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517484190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3517484190
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.2814718719
Short name T154
Test name
Test status
Simulation time 335724018101 ps
CPU time 182.28 seconds
Started Jul 07 06:01:52 PM PDT 24
Finished Jul 07 06:04:54 PM PDT 24
Peak memory 201924 kb
Host smart-48e90208-711f-4f7c-8f3f-ff3eb8df067d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814718719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.2814718719
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2298694274
Short name T504
Test name
Test status
Simulation time 195759629480 ps
CPU time 222.35 seconds
Started Jul 07 06:01:51 PM PDT 24
Finished Jul 07 06:05:33 PM PDT 24
Peak memory 202152 kb
Host smart-fa00337c-e8be-4917-8d8a-52240ef9d4b3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298694274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2298694274
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1621697473
Short name T444
Test name
Test status
Simulation time 106452241028 ps
CPU time 415.27 seconds
Started Jul 07 06:01:56 PM PDT 24
Finished Jul 07 06:08:52 PM PDT 24
Peak memory 202156 kb
Host smart-99e84153-442e-4c70-b1ad-ffdd15b1adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621697473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1621697473
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.169940218
Short name T356
Test name
Test status
Simulation time 30646113540 ps
CPU time 63.65 seconds
Started Jul 07 06:01:53 PM PDT 24
Finished Jul 07 06:02:57 PM PDT 24
Peak memory 201708 kb
Host smart-78a4fd06-6bf5-4d8f-adf3-0dc26045266a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169940218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.169940218
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.4212684817
Short name T429
Test name
Test status
Simulation time 3645864887 ps
CPU time 4.65 seconds
Started Jul 07 06:01:53 PM PDT 24
Finished Jul 07 06:01:58 PM PDT 24
Peak memory 201736 kb
Host smart-01558cef-55ba-4e09-b05a-d2951330698b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212684817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.4212684817
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.64135462
Short name T611
Test name
Test status
Simulation time 6158384765 ps
CPU time 15.07 seconds
Started Jul 07 06:01:48 PM PDT 24
Finished Jul 07 06:02:04 PM PDT 24
Peak memory 201708 kb
Host smart-772d3b1b-8cfd-413e-9d9e-fc5142b24712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64135462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.64135462
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.120250635
Short name T22
Test name
Test status
Simulation time 285272516 ps
CPU time 1.16 seconds
Started Jul 07 06:02:08 PM PDT 24
Finished Jul 07 06:02:09 PM PDT 24
Peak memory 201512 kb
Host smart-822e2891-1677-4223-86d1-4ce102aa87aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120250635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.120250635
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.1401618051
Short name T512
Test name
Test status
Simulation time 375109711116 ps
CPU time 228.86 seconds
Started Jul 07 06:02:02 PM PDT 24
Finished Jul 07 06:05:51 PM PDT 24
Peak memory 201964 kb
Host smart-f544d00f-e79d-41f3-8b90-4627742d4b55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401618051 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.1401618051
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.2817277363
Short name T659
Test name
Test status
Simulation time 330476634008 ps
CPU time 197.72 seconds
Started Jul 07 06:02:01 PM PDT 24
Finished Jul 07 06:05:19 PM PDT 24
Peak memory 201924 kb
Host smart-9d38737e-2b10-4aac-96ab-1895d5158c0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817277363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.2817277363
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.1789410063
Short name T768
Test name
Test status
Simulation time 491145319259 ps
CPU time 536.11 seconds
Started Jul 07 06:01:56 PM PDT 24
Finished Jul 07 06:10:52 PM PDT 24
Peak memory 201892 kb
Host smart-a0959126-eec7-4b80-b050-fd51c8edc345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789410063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.1789410063
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3230943904
Short name T757
Test name
Test status
Simulation time 159011467555 ps
CPU time 88.08 seconds
Started Jul 07 06:02:02 PM PDT 24
Finished Jul 07 06:03:30 PM PDT 24
Peak memory 201936 kb
Host smart-a7b72c88-8e38-4e5e-80db-c98c2b9612e1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230943904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3230943904
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.2720908623
Short name T262
Test name
Test status
Simulation time 542090785713 ps
CPU time 1185.53 seconds
Started Jul 07 06:01:57 PM PDT 24
Finished Jul 07 06:21:43 PM PDT 24
Peak memory 201912 kb
Host smart-8a581d7b-d8bd-4012-8b6a-797173353d57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720908623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.2720908623
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.956016998
Short name T631
Test name
Test status
Simulation time 407203360135 ps
CPU time 827.09 seconds
Started Jul 07 06:02:01 PM PDT 24
Finished Jul 07 06:15:48 PM PDT 24
Peak memory 201924 kb
Host smart-55bbcb04-f654-417c-91dd-d31581992077
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956016998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.
adc_ctrl_filters_wakeup_fixed.956016998
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.1870197138
Short name T404
Test name
Test status
Simulation time 134948714122 ps
CPU time 524.96 seconds
Started Jul 07 06:02:00 PM PDT 24
Finished Jul 07 06:10:45 PM PDT 24
Peak memory 202232 kb
Host smart-1328301d-0827-442c-958c-26d62a0f5377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870197138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.1870197138
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.104581615
Short name T480
Test name
Test status
Simulation time 38320767479 ps
CPU time 12.16 seconds
Started Jul 07 06:02:03 PM PDT 24
Finished Jul 07 06:02:16 PM PDT 24
Peak memory 201680 kb
Host smart-1a24d1a8-ba30-4a92-93e8-752e1598c5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104581615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.104581615
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.1745048135
Short name T601
Test name
Test status
Simulation time 3012427538 ps
CPU time 6.63 seconds
Started Jul 07 06:02:01 PM PDT 24
Finished Jul 07 06:02:08 PM PDT 24
Peak memory 201716 kb
Host smart-f18cfdbc-a76c-44a8-8fa7-cabc186487c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745048135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.1745048135
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.2696239357
Short name T533
Test name
Test status
Simulation time 5840636582 ps
CPU time 4.33 seconds
Started Jul 07 06:01:54 PM PDT 24
Finished Jul 07 06:01:58 PM PDT 24
Peak memory 201696 kb
Host smart-26647be5-dade-45da-ab27-c469ef344e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696239357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.2696239357
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2560539426
Short name T230
Test name
Test status
Simulation time 329747115562 ps
CPU time 75.76 seconds
Started Jul 07 06:02:01 PM PDT 24
Finished Jul 07 06:03:17 PM PDT 24
Peak memory 201888 kb
Host smart-f0935a77-5f51-4f81-b393-5383c38278a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560539426 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2560539426
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.2949326973
Short name T99
Test name
Test status
Simulation time 51593254226 ps
CPU time 142.75 seconds
Started Jul 07 06:02:02 PM PDT 24
Finished Jul 07 06:04:25 PM PDT 24
Peak memory 211556 kb
Host smart-dac40980-f134-4aa7-9bc7-be6b52dceb43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949326973 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.2949326973
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.2425457120
Short name T100
Test name
Test status
Simulation time 474658597 ps
CPU time 1.62 seconds
Started Jul 07 06:02:13 PM PDT 24
Finished Jul 07 06:02:15 PM PDT 24
Peak memory 201668 kb
Host smart-9d1158e7-155a-4ca0-a01b-54bd2f883768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425457120 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.2425457120
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1357825664
Short name T502
Test name
Test status
Simulation time 166943253280 ps
CPU time 201.05 seconds
Started Jul 07 06:02:12 PM PDT 24
Finished Jul 07 06:05:33 PM PDT 24
Peak memory 201888 kb
Host smart-021e4ff3-abaf-4d5a-a65b-10716f31d0ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357825664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1357825664
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.4218689132
Short name T198
Test name
Test status
Simulation time 564879719870 ps
CPU time 335.37 seconds
Started Jul 07 06:02:16 PM PDT 24
Finished Jul 07 06:07:52 PM PDT 24
Peak memory 201968 kb
Host smart-1fee12be-a289-493c-80ef-2fb678e6aff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218689132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.4218689132
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.1370157080
Short name T544
Test name
Test status
Simulation time 163453705657 ps
CPU time 190.38 seconds
Started Jul 07 06:02:09 PM PDT 24
Finished Jul 07 06:05:20 PM PDT 24
Peak memory 201840 kb
Host smart-6022f76f-a7a1-4637-b01a-490751f1d96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370157080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.1370157080
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.3555030411
Short name T436
Test name
Test status
Simulation time 164879323714 ps
CPU time 98.23 seconds
Started Jul 07 06:02:06 PM PDT 24
Finished Jul 07 06:03:44 PM PDT 24
Peak memory 201876 kb
Host smart-d830bf4c-7e35-468f-bd78-52e67ea2b9de
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555030411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.3555030411
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.4197576983
Short name T151
Test name
Test status
Simulation time 484419548984 ps
CPU time 1130.18 seconds
Started Jul 07 06:02:08 PM PDT 24
Finished Jul 07 06:20:59 PM PDT 24
Peak memory 201908 kb
Host smart-a4405494-9a36-4684-88db-7561fe9a3a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197576983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.4197576983
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2940278864
Short name T557
Test name
Test status
Simulation time 489854332861 ps
CPU time 1015.68 seconds
Started Jul 07 06:02:05 PM PDT 24
Finished Jul 07 06:19:01 PM PDT 24
Peak memory 201864 kb
Host smart-1411bcfc-34a8-4790-9ff5-c1e4aae8e1b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940278864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2940278864
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1382262266
Short name T333
Test name
Test status
Simulation time 180292349010 ps
CPU time 403.37 seconds
Started Jul 07 06:02:09 PM PDT 24
Finished Jul 07 06:08:52 PM PDT 24
Peak memory 201908 kb
Host smart-47ba2f94-7f8e-4e05-84af-750d9997069d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382262266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1382262266
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.3627536530
Short name T571
Test name
Test status
Simulation time 586343121696 ps
CPU time 1335.27 seconds
Started Jul 07 06:02:06 PM PDT 24
Finished Jul 07 06:24:21 PM PDT 24
Peak memory 201856 kb
Host smart-5b8090d0-8109-4836-9dd8-95bf5ec8d2e9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627536530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.3627536530
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.970796411
Short name T672
Test name
Test status
Simulation time 34962978957 ps
CPU time 37.52 seconds
Started Jul 07 06:02:12 PM PDT 24
Finished Jul 07 06:02:50 PM PDT 24
Peak memory 201704 kb
Host smart-e2dfb703-393a-47fc-a077-5732c3aafa01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970796411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.970796411
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.3897071156
Short name T665
Test name
Test status
Simulation time 3413562152 ps
CPU time 3.25 seconds
Started Jul 07 06:02:08 PM PDT 24
Finished Jul 07 06:02:12 PM PDT 24
Peak memory 201720 kb
Host smart-7710552f-5992-4d8f-8c66-872d024c0dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897071156 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.3897071156
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.3487657583
Short name T700
Test name
Test status
Simulation time 5643202118 ps
CPU time 2.32 seconds
Started Jul 07 06:02:08 PM PDT 24
Finished Jul 07 06:02:10 PM PDT 24
Peak memory 201656 kb
Host smart-30a5ac0a-d264-47e9-a750-c4ff88f763e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487657583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.3487657583
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.4249741941
Short name T286
Test name
Test status
Simulation time 158647389355 ps
CPU time 91.36 seconds
Started Jul 07 06:02:08 PM PDT 24
Finished Jul 07 06:03:39 PM PDT 24
Peak memory 201952 kb
Host smart-fbe9ff5e-1a05-416f-86c5-8a0d9a642a84
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249741941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.4249741941
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.597051556
Short name T578
Test name
Test status
Simulation time 53833277654 ps
CPU time 31.79 seconds
Started Jul 07 06:02:12 PM PDT 24
Finished Jul 07 06:02:44 PM PDT 24
Peak memory 202032 kb
Host smart-466fc54d-8dcc-4624-8bd5-384a021dcd00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597051556 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.597051556
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.4202289982
Short name T417
Test name
Test status
Simulation time 434996131 ps
CPU time 1.55 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:00:39 PM PDT 24
Peak memory 201656 kb
Host smart-36798123-07c9-4ec7-9a09-cb1606be6d6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202289982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.4202289982
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.1800234428
Short name T683
Test name
Test status
Simulation time 164948229972 ps
CPU time 377.29 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:07:00 PM PDT 24
Peak memory 201884 kb
Host smart-03da29fe-72ba-43fd-9f23-863a642dc6da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800234428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gati
ng.1800234428
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3759146276
Short name T258
Test name
Test status
Simulation time 506339652544 ps
CPU time 438.3 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:07:51 PM PDT 24
Peak memory 201904 kb
Host smart-3eaa93a7-63da-4070-9cf1-6d1adb03ded8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759146276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3759146276
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.1479763708
Short name T663
Test name
Test status
Simulation time 485855706340 ps
CPU time 307.45 seconds
Started Jul 07 06:00:33 PM PDT 24
Finished Jul 07 06:05:40 PM PDT 24
Peak memory 201892 kb
Host smart-ba6c9884-1e23-42ce-87f3-ca00d4182535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479763708 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.1479763708
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.2005703361
Short name T86
Test name
Test status
Simulation time 496751520513 ps
CPU time 1040.59 seconds
Started Jul 07 06:00:33 PM PDT 24
Finished Jul 07 06:17:54 PM PDT 24
Peak memory 201828 kb
Host smart-d9405711-4dc5-46cb-acc3-950f18dbc176
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005703361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.2005703361
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.1211913200
Short name T534
Test name
Test status
Simulation time 165514245526 ps
CPU time 187.18 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:03:38 PM PDT 24
Peak memory 201956 kb
Host smart-73f164dd-95b1-436d-9b90-919090848898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211913200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.1211913200
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.112234758
Short name T506
Test name
Test status
Simulation time 496027744286 ps
CPU time 1043.39 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:17:56 PM PDT 24
Peak memory 201864 kb
Host smart-6243298b-2335-4153-bb95-f5491917a4f5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=112234758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.112234758
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2205076878
Short name T169
Test name
Test status
Simulation time 377678160285 ps
CPU time 71.3 seconds
Started Jul 07 06:00:31 PM PDT 24
Finished Jul 07 06:01:42 PM PDT 24
Peak memory 201968 kb
Host smart-08ccd04e-bc4d-4994-9a2d-fdabf8e9100d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205076878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2205076878
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.2139692110
Short name T783
Test name
Test status
Simulation time 403857441711 ps
CPU time 421.31 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:07:34 PM PDT 24
Peak memory 201944 kb
Host smart-8fbbd0a1-6d9d-4637-9abf-586957d5e6b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139692110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.2139692110
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.780187491
Short name T744
Test name
Test status
Simulation time 106823775046 ps
CPU time 372.75 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:06:51 PM PDT 24
Peak memory 202156 kb
Host smart-d5092932-4f4b-4995-8bf2-7182921681e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780187491 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.780187491
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.644525655
Short name T765
Test name
Test status
Simulation time 32914902417 ps
CPU time 76.97 seconds
Started Jul 07 06:00:33 PM PDT 24
Finished Jul 07 06:01:50 PM PDT 24
Peak memory 201700 kb
Host smart-e64d6ff4-6d6a-4c70-a419-1e1b09666f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644525655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.644525655
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1449611578
Short name T682
Test name
Test status
Simulation time 4789274876 ps
CPU time 3.21 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:00:40 PM PDT 24
Peak memory 201708 kb
Host smart-b7a6f226-73ed-45cf-8604-51a11df86b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449611578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1449611578
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3772861998
Short name T55
Test name
Test status
Simulation time 8191390459 ps
CPU time 17.02 seconds
Started Jul 07 06:00:34 PM PDT 24
Finished Jul 07 06:00:51 PM PDT 24
Peak memory 217060 kb
Host smart-de45bab2-05a4-40c0-a77a-492df3a97725
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772861998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3772861998
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.483204272
Short name T442
Test name
Test status
Simulation time 6084186196 ps
CPU time 8.51 seconds
Started Jul 07 06:00:33 PM PDT 24
Finished Jul 07 06:00:42 PM PDT 24
Peak memory 201688 kb
Host smart-bdbc6758-7083-4119-9169-ca0e0a896688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483204272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.483204272
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.3949240267
Short name T526
Test name
Test status
Simulation time 177736167588 ps
CPU time 422.15 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:07:38 PM PDT 24
Peak memory 201896 kb
Host smart-49937a45-131f-474e-bafa-eb7bb5cdf8ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949240267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
3949240267
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.302176017
Short name T105
Test name
Test status
Simulation time 155542930650 ps
CPU time 442.97 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:08:02 PM PDT 24
Peak memory 210580 kb
Host smart-9bb5009a-4e7a-4951-9a3a-e49d238ecf38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302176017 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.302176017
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3937403097
Short name T577
Test name
Test status
Simulation time 499462201 ps
CPU time 1.81 seconds
Started Jul 07 06:02:20 PM PDT 24
Finished Jul 07 06:02:23 PM PDT 24
Peak memory 201616 kb
Host smart-2a458434-214b-4d1d-b93b-17b20dabb26b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937403097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3937403097
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.1096123127
Short name T326
Test name
Test status
Simulation time 342733341977 ps
CPU time 130.15 seconds
Started Jul 07 06:02:12 PM PDT 24
Finished Jul 07 06:04:22 PM PDT 24
Peak memory 201900 kb
Host smart-acdb4437-7026-4680-b50a-4652d4c4bf3a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096123127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.1096123127
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3333143086
Short name T599
Test name
Test status
Simulation time 162928433779 ps
CPU time 139.55 seconds
Started Jul 07 06:02:13 PM PDT 24
Finished Jul 07 06:04:33 PM PDT 24
Peak memory 201912 kb
Host smart-8ce70e58-707b-4810-a02b-713fea629dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333143086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3333143086
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.2615784697
Short name T448
Test name
Test status
Simulation time 488334900037 ps
CPU time 1030.21 seconds
Started Jul 07 06:02:14 PM PDT 24
Finished Jul 07 06:19:24 PM PDT 24
Peak memory 201832 kb
Host smart-83d5eb15-cd12-43fe-8b53-64f71824227e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615784697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.2615784697
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.1722990945
Short name T73
Test name
Test status
Simulation time 163674342860 ps
CPU time 186.07 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:05:25 PM PDT 24
Peak memory 201872 kb
Host smart-47664920-a94a-430a-be24-482b0ea2a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722990945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.1722990945
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3654018592
Short name T681
Test name
Test status
Simulation time 493596773765 ps
CPU time 194.89 seconds
Started Jul 07 06:02:13 PM PDT 24
Finished Jul 07 06:05:28 PM PDT 24
Peak memory 201868 kb
Host smart-230bde16-2f70-4f2f-8391-2471e5a00c16
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654018592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3654018592
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3125304220
Short name T194
Test name
Test status
Simulation time 406679617446 ps
CPU time 216.18 seconds
Started Jul 07 06:02:12 PM PDT 24
Finished Jul 07 06:05:49 PM PDT 24
Peak memory 201888 kb
Host smart-cb84f856-ca40-4dd6-a213-e7b2be415a67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125304220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3125304220
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.2728158748
Short name T206
Test name
Test status
Simulation time 125796291075 ps
CPU time 651.31 seconds
Started Jul 07 06:02:16 PM PDT 24
Finished Jul 07 06:13:08 PM PDT 24
Peak memory 202240 kb
Host smart-42e9c3d3-4a08-4496-a0e8-137acc466637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728158748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.2728158748
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2821814394
Short name T602
Test name
Test status
Simulation time 31358025394 ps
CPU time 68.99 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:03:28 PM PDT 24
Peak memory 201704 kb
Host smart-2a09e437-4ae6-4a87-aff8-a7113e887332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821814394 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2821814394
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3956200052
Short name T688
Test name
Test status
Simulation time 3591592823 ps
CPU time 2.83 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:02:22 PM PDT 24
Peak memory 201672 kb
Host smart-ae021a89-a580-48b6-a2a7-ea5bf2c7e6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956200052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3956200052
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1999376377
Short name T410
Test name
Test status
Simulation time 6166581272 ps
CPU time 2.07 seconds
Started Jul 07 06:02:13 PM PDT 24
Finished Jul 07 06:02:16 PM PDT 24
Peak memory 201716 kb
Host smart-703fc8d3-039d-4f95-8fea-b533e0a33a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999376377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1999376377
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.2554295721
Short name T778
Test name
Test status
Simulation time 165806522178 ps
CPU time 456.44 seconds
Started Jul 07 06:02:22 PM PDT 24
Finished Jul 07 06:09:59 PM PDT 24
Peak memory 202256 kb
Host smart-672b1bfe-f98c-4995-8181-6ceb7f6fa34e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554295721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.2554295721
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.1624747994
Short name T411
Test name
Test status
Simulation time 521819677 ps
CPU time 1.22 seconds
Started Jul 07 06:02:24 PM PDT 24
Finished Jul 07 06:02:26 PM PDT 24
Peak memory 201644 kb
Host smart-4e0e247a-7e26-4555-94c1-75c366a3459b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624747994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.1624747994
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.3113649004
Short name T239
Test name
Test status
Simulation time 164563968131 ps
CPU time 341.77 seconds
Started Jul 07 06:02:22 PM PDT 24
Finished Jul 07 06:08:04 PM PDT 24
Peak memory 201944 kb
Host smart-cb99ba51-c745-4001-b83e-a9767f74e690
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113649004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.3113649004
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.4118060642
Short name T707
Test name
Test status
Simulation time 344245393148 ps
CPU time 191.75 seconds
Started Jul 07 06:02:22 PM PDT 24
Finished Jul 07 06:05:34 PM PDT 24
Peak memory 201868 kb
Host smart-760a15c6-8b19-4846-9620-f319e7c7eea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118060642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.4118060642
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3490206886
Short name T670
Test name
Test status
Simulation time 169881046520 ps
CPU time 404.17 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:09:04 PM PDT 24
Peak memory 201856 kb
Host smart-01c37825-9b40-479d-910f-69aab9521de5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490206886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3490206886
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.4139320225
Short name T388
Test name
Test status
Simulation time 332688650045 ps
CPU time 749.05 seconds
Started Jul 07 06:02:22 PM PDT 24
Finished Jul 07 06:14:51 PM PDT 24
Peak memory 201912 kb
Host smart-d551bb6f-ed05-4c6f-95dc-7ceebb94ddde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139320225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.4139320225
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.512818309
Short name T690
Test name
Test status
Simulation time 501697312783 ps
CPU time 150.6 seconds
Started Jul 07 06:02:23 PM PDT 24
Finished Jul 07 06:04:54 PM PDT 24
Peak memory 201828 kb
Host smart-02bae9b3-db2c-4a48-ad54-2d46d9e0419b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=512818309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fixe
d.512818309
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.3924985
Short name T546
Test name
Test status
Simulation time 608882440923 ps
CPU time 656.74 seconds
Started Jul 07 06:02:23 PM PDT 24
Finished Jul 07 06:13:20 PM PDT 24
Peak memory 201856 kb
Host smart-ac173c77-5bb0-4300-839f-ec6c10660fb5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.ad
c_ctrl_filters_wakeup_fixed.3924985
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.3252124667
Short name T773
Test name
Test status
Simulation time 114565661767 ps
CPU time 455.78 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:09:55 PM PDT 24
Peak memory 202216 kb
Host smart-ddbf70e9-c352-416d-a05d-57b3394c9028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252124667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.3252124667
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1464227038
Short name T74
Test name
Test status
Simulation time 35054581597 ps
CPU time 20.84 seconds
Started Jul 07 06:02:23 PM PDT 24
Finished Jul 07 06:02:44 PM PDT 24
Peak memory 201708 kb
Host smart-43e5cd75-cd6e-4bc8-8454-9b1dba395253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464227038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1464227038
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.3287864015
Short name T555
Test name
Test status
Simulation time 3859832272 ps
CPU time 3.96 seconds
Started Jul 07 06:02:19 PM PDT 24
Finished Jul 07 06:02:23 PM PDT 24
Peak memory 201732 kb
Host smart-ed5b4d85-fee7-4821-b665-02104ca1ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287864015 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.3287864015
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.3632145092
Short name T110
Test name
Test status
Simulation time 5986316538 ps
CPU time 5.33 seconds
Started Jul 07 06:02:21 PM PDT 24
Finished Jul 07 06:02:27 PM PDT 24
Peak memory 201736 kb
Host smart-170da62c-482d-4f0b-accc-274459e81b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632145092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.3632145092
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.2563706553
Short name T774
Test name
Test status
Simulation time 160803931255 ps
CPU time 99.28 seconds
Started Jul 07 06:02:26 PM PDT 24
Finished Jul 07 06:04:06 PM PDT 24
Peak memory 201888 kb
Host smart-c514fb9b-9c09-4946-a9b0-cadad54dc966
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563706553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.2563706553
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.3198203427
Short name T424
Test name
Test status
Simulation time 440609669 ps
CPU time 0.84 seconds
Started Jul 07 06:02:30 PM PDT 24
Finished Jul 07 06:02:31 PM PDT 24
Peak memory 201644 kb
Host smart-9b19fd39-51ce-4475-8a8a-ed63ad2d23f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198203427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.3198203427
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2563627141
Short name T771
Test name
Test status
Simulation time 327394545217 ps
CPU time 349.19 seconds
Started Jul 07 06:02:29 PM PDT 24
Finished Jul 07 06:08:18 PM PDT 24
Peak memory 201920 kb
Host smart-e24df07f-e4c0-44ee-bbe9-dc4e98c0c84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563627141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2563627141
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.3063045812
Short name T114
Test name
Test status
Simulation time 165454611129 ps
CPU time 405.27 seconds
Started Jul 07 06:02:30 PM PDT 24
Finished Jul 07 06:09:15 PM PDT 24
Peak memory 201860 kb
Host smart-d37bccbb-525a-4c4f-8fc8-c6b77e6b6dbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063045812 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.3063045812
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.2690245014
Short name T219
Test name
Test status
Simulation time 164803721001 ps
CPU time 174.1 seconds
Started Jul 07 06:02:24 PM PDT 24
Finished Jul 07 06:05:19 PM PDT 24
Peak memory 201976 kb
Host smart-6fab386d-d8e1-4ec4-8d67-7453a387b83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690245014 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.2690245014
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.682479818
Short name T645
Test name
Test status
Simulation time 493273916672 ps
CPU time 264.05 seconds
Started Jul 07 06:02:28 PM PDT 24
Finished Jul 07 06:06:52 PM PDT 24
Peak memory 201896 kb
Host smart-72338ea2-0fc4-4af0-9a23-8f58925b1157
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=682479818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fixe
d.682479818
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1565065638
Short name T235
Test name
Test status
Simulation time 180435376916 ps
CPU time 91.07 seconds
Started Jul 07 06:02:29 PM PDT 24
Finished Jul 07 06:04:01 PM PDT 24
Peak memory 201888 kb
Host smart-1af3d2e4-3eaf-47e1-b166-1feddcdc29cd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565065638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1565065638
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2935880272
Short name T565
Test name
Test status
Simulation time 413202931612 ps
CPU time 243.04 seconds
Started Jul 07 06:02:28 PM PDT 24
Finished Jul 07 06:06:31 PM PDT 24
Peak memory 201856 kb
Host smart-63ca7afe-ad56-440e-aa7b-1cc817f15695
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935880272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2935880272
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.3075114917
Short name T203
Test name
Test status
Simulation time 72984749261 ps
CPU time 249.47 seconds
Started Jul 07 06:02:29 PM PDT 24
Finished Jul 07 06:06:39 PM PDT 24
Peak memory 202252 kb
Host smart-3ef81c93-3cfd-4f64-9581-40ada55075d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075114917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.3075114917
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4094270766
Short name T669
Test name
Test status
Simulation time 41252068740 ps
CPU time 46.13 seconds
Started Jul 07 06:02:29 PM PDT 24
Finished Jul 07 06:03:15 PM PDT 24
Peak memory 201564 kb
Host smart-f4feec66-027f-45e1-8ab2-deb9859b0606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094270766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4094270766
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.4103105868
Short name T349
Test name
Test status
Simulation time 3961175393 ps
CPU time 5 seconds
Started Jul 07 06:02:27 PM PDT 24
Finished Jul 07 06:02:32 PM PDT 24
Peak memory 201720 kb
Host smart-768bed3d-45c9-4fb1-8a71-1dff8d1d1ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103105868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.4103105868
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.580473813
Short name T357
Test name
Test status
Simulation time 5766955316 ps
CPU time 7.35 seconds
Started Jul 07 06:02:29 PM PDT 24
Finished Jul 07 06:02:36 PM PDT 24
Peak memory 201700 kb
Host smart-d44315c0-7ed5-4def-8e61-864a541c48d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580473813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.580473813
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.2740417515
Short name T195
Test name
Test status
Simulation time 507960500446 ps
CPU time 529.74 seconds
Started Jul 07 06:02:30 PM PDT 24
Finished Jul 07 06:11:20 PM PDT 24
Peak memory 201952 kb
Host smart-2513927b-333d-4998-b3d5-9ac4f0d6febe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740417515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.2740417515
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.1441357551
Short name T409
Test name
Test status
Simulation time 317416228 ps
CPU time 1.28 seconds
Started Jul 07 06:02:46 PM PDT 24
Finished Jul 07 06:02:48 PM PDT 24
Peak memory 201644 kb
Host smart-e78cdc1d-c1fe-434e-a926-b1a41edd64af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441357551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.1441357551
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.3546201150
Short name T300
Test name
Test status
Simulation time 422217657821 ps
CPU time 618.41 seconds
Started Jul 07 06:02:42 PM PDT 24
Finished Jul 07 06:13:01 PM PDT 24
Peak memory 201880 kb
Host smart-58c8397d-966f-4966-81d4-c21f89ddb3f7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546201150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.3546201150
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.3316596337
Short name T136
Test name
Test status
Simulation time 360147733570 ps
CPU time 303.38 seconds
Started Jul 07 06:02:41 PM PDT 24
Finished Jul 07 06:07:44 PM PDT 24
Peak memory 201980 kb
Host smart-c8a7a230-cfe0-4468-89ac-b2effc2584b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316596337 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.3316596337
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.1315466312
Short name T549
Test name
Test status
Simulation time 166618009788 ps
CPU time 350.47 seconds
Started Jul 07 06:02:35 PM PDT 24
Finished Jul 07 06:08:25 PM PDT 24
Peak memory 201896 kb
Host smart-5f972d75-20dc-43df-bfc8-349a7fd3900d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315466312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.1315466312
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.2698215637
Short name T439
Test name
Test status
Simulation time 332525781659 ps
CPU time 202.5 seconds
Started Jul 07 06:02:35 PM PDT 24
Finished Jul 07 06:05:58 PM PDT 24
Peak memory 201868 kb
Host smart-1f162d3b-da8e-4003-a8d6-e87c5858d0cc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698215637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.2698215637
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.1341961062
Short name T285
Test name
Test status
Simulation time 331817822452 ps
CPU time 387.82 seconds
Started Jul 07 06:02:38 PM PDT 24
Finished Jul 07 06:09:06 PM PDT 24
Peak memory 201888 kb
Host smart-52032ab8-2606-4dcd-b936-0d9f88d97050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341961062 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.1341961062
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2135895549
Short name T95
Test name
Test status
Simulation time 505929341973 ps
CPU time 653.63 seconds
Started Jul 07 06:02:39 PM PDT 24
Finished Jul 07 06:13:33 PM PDT 24
Peak memory 201924 kb
Host smart-cd85e85a-ec90-47ee-ac87-8041389e6717
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135895549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2135895549
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.1171192571
Short name T784
Test name
Test status
Simulation time 539409265993 ps
CPU time 219.36 seconds
Started Jul 07 06:02:37 PM PDT 24
Finished Jul 07 06:06:16 PM PDT 24
Peak memory 201888 kb
Host smart-1a6f1c40-655d-4f4e-9ded-e1533279adbe
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171192571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.1171192571
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.4248294909
Short name T399
Test name
Test status
Simulation time 603424780268 ps
CPU time 202.98 seconds
Started Jul 07 06:02:38 PM PDT 24
Finished Jul 07 06:06:01 PM PDT 24
Peak memory 201892 kb
Host smart-20ed38a6-69cb-4e59-9a53-49ec53db95d3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248294909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.4248294909
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.1321949565
Short name T337
Test name
Test status
Simulation time 129257556622 ps
CPU time 419 seconds
Started Jul 07 06:02:44 PM PDT 24
Finished Jul 07 06:09:43 PM PDT 24
Peak memory 202148 kb
Host smart-38d11fff-4d3b-4c74-b539-decd583f7bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321949565 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.1321949565
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.311810157
Short name T190
Test name
Test status
Simulation time 43276017551 ps
CPU time 93.49 seconds
Started Jul 07 06:02:44 PM PDT 24
Finished Jul 07 06:04:17 PM PDT 24
Peak memory 201744 kb
Host smart-8958fcf0-03e4-4cd2-aafc-f5d67726a7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311810157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.311810157
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.4289832718
Short name T553
Test name
Test status
Simulation time 2911131347 ps
CPU time 7.53 seconds
Started Jul 07 06:02:41 PM PDT 24
Finished Jul 07 06:02:49 PM PDT 24
Peak memory 201700 kb
Host smart-bf443c69-d44e-4fe2-9072-8a26afdc409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289832718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.4289832718
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.963586627
Short name T562
Test name
Test status
Simulation time 5783284289 ps
CPU time 7.12 seconds
Started Jul 07 06:02:34 PM PDT 24
Finished Jul 07 06:02:41 PM PDT 24
Peak memory 201712 kb
Host smart-ad3e651d-0678-401e-8d4d-4d8adbcb4586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963586627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.963586627
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2626275021
Short name T164
Test name
Test status
Simulation time 30642282887 ps
CPU time 72.2 seconds
Started Jul 07 06:02:42 PM PDT 24
Finished Jul 07 06:03:55 PM PDT 24
Peak memory 201712 kb
Host smart-925f72bf-edcc-4090-a593-2f1b2a6a379b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626275021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2626275021
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.761467588
Short name T679
Test name
Test status
Simulation time 311873816 ps
CPU time 0.82 seconds
Started Jul 07 06:02:54 PM PDT 24
Finished Jul 07 06:02:55 PM PDT 24
Peak memory 201668 kb
Host smart-67e61d2e-3041-430d-86e0-a00428c07917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761467588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.761467588
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.1286407704
Short name T566
Test name
Test status
Simulation time 168283944410 ps
CPU time 324.98 seconds
Started Jul 07 06:02:50 PM PDT 24
Finished Jul 07 06:08:15 PM PDT 24
Peak memory 201884 kb
Host smart-594b9739-095a-402d-876f-e92f5277394f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286407704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.1286407704
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.3494863780
Short name T79
Test name
Test status
Simulation time 163292709972 ps
CPU time 203.59 seconds
Started Jul 07 06:02:44 PM PDT 24
Finished Jul 07 06:06:08 PM PDT 24
Peak memory 201924 kb
Host smart-7952152a-191c-4d2d-868f-815dec147ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494863780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.3494863780
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.2827548143
Short name T168
Test name
Test status
Simulation time 490033187672 ps
CPU time 208.62 seconds
Started Jul 07 06:02:45 PM PDT 24
Finished Jul 07 06:06:13 PM PDT 24
Peak memory 201892 kb
Host smart-9c0a2791-eddc-49dc-8254-3dbd198e45b5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827548143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.2827548143
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.1754656579
Short name T137
Test name
Test status
Simulation time 494818463701 ps
CPU time 190.66 seconds
Started Jul 07 06:02:45 PM PDT 24
Finished Jul 07 06:05:56 PM PDT 24
Peak memory 201976 kb
Host smart-1ae48eee-22f1-4302-92af-07603f919fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754656579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.1754656579
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3453569575
Short name T418
Test name
Test status
Simulation time 164173363527 ps
CPU time 185.82 seconds
Started Jul 07 06:02:44 PM PDT 24
Finished Jul 07 06:05:50 PM PDT 24
Peak memory 201864 kb
Host smart-34b2f6b5-3487-43b7-9bef-43ed41e84c94
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453569575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3453569575
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.1467706600
Short name T277
Test name
Test status
Simulation time 206172288237 ps
CPU time 110.64 seconds
Started Jul 07 06:02:48 PM PDT 24
Finished Jul 07 06:04:39 PM PDT 24
Peak memory 201908 kb
Host smart-271a0a16-17c8-415c-b1aa-1fdc606d81cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467706600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.1467706600
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.380852713
Short name T364
Test name
Test status
Simulation time 390374178958 ps
CPU time 900.74 seconds
Started Jul 07 06:02:45 PM PDT 24
Finished Jul 07 06:17:46 PM PDT 24
Peak memory 201892 kb
Host smart-e89e2bbe-b402-4019-970e-0dad6b01b0b5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380852713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.
adc_ctrl_filters_wakeup_fixed.380852713
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1016004997
Short name T187
Test name
Test status
Simulation time 73593554947 ps
CPU time 393.28 seconds
Started Jul 07 06:02:57 PM PDT 24
Finished Jul 07 06:09:30 PM PDT 24
Peak memory 202212 kb
Host smart-2165096b-3fad-4c76-a6f4-7feb9a92ddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016004997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1016004997
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3691658853
Short name T346
Test name
Test status
Simulation time 36468688715 ps
CPU time 10.47 seconds
Started Jul 07 06:02:51 PM PDT 24
Finished Jul 07 06:03:02 PM PDT 24
Peak memory 201692 kb
Host smart-a214f2e1-4a29-4993-95d0-fda0b78a9b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691658853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3691658853
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3496504276
Short name T449
Test name
Test status
Simulation time 4112910379 ps
CPU time 9.28 seconds
Started Jul 07 06:02:53 PM PDT 24
Finished Jul 07 06:03:03 PM PDT 24
Peak memory 201664 kb
Host smart-e23d33d1-f6e4-45b4-9c86-d6b2b8ea3173
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496504276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3496504276
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.531352719
Short name T613
Test name
Test status
Simulation time 6106557857 ps
CPU time 7.78 seconds
Started Jul 07 06:02:46 PM PDT 24
Finished Jul 07 06:02:54 PM PDT 24
Peak memory 201692 kb
Host smart-1def668f-f0ad-4cf1-a8c9-c8f000f045b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531352719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.531352719
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.2139482072
Short name T788
Test name
Test status
Simulation time 329359828090 ps
CPU time 676.44 seconds
Started Jul 07 06:02:57 PM PDT 24
Finished Jul 07 06:14:14 PM PDT 24
Peak memory 201808 kb
Host smart-37c8bd16-3142-43f1-b827-aaae62419019
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139482072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.2139482072
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.929765552
Short name T387
Test name
Test status
Simulation time 404392611 ps
CPU time 0.84 seconds
Started Jul 07 06:03:05 PM PDT 24
Finished Jul 07 06:03:06 PM PDT 24
Peak memory 201652 kb
Host smart-6e869fb9-ebe9-4658-b3f1-5a923302a104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929765552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.929765552
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2866988790
Short name T272
Test name
Test status
Simulation time 503313768996 ps
CPU time 189.52 seconds
Started Jul 07 06:02:56 PM PDT 24
Finished Jul 07 06:06:05 PM PDT 24
Peak memory 201980 kb
Host smart-faee2f03-b77f-4098-9859-71505ed73836
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866988790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2866988790
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.3660421801
Short name T676
Test name
Test status
Simulation time 167812388626 ps
CPU time 366.6 seconds
Started Jul 07 06:02:55 PM PDT 24
Finished Jul 07 06:09:02 PM PDT 24
Peak memory 201912 kb
Host smart-1bb22983-2eac-4d16-a278-58ff3bc9d825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660421801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.3660421801
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.2496088231
Short name T753
Test name
Test status
Simulation time 488103859940 ps
CPU time 1168.45 seconds
Started Jul 07 06:02:58 PM PDT 24
Finished Jul 07 06:22:27 PM PDT 24
Peak memory 201908 kb
Host smart-d2ef5e25-7202-4577-978f-beefce827168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496088231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.2496088231
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3642614987
Short name T507
Test name
Test status
Simulation time 160998006738 ps
CPU time 183.56 seconds
Started Jul 07 06:02:54 PM PDT 24
Finished Jul 07 06:05:58 PM PDT 24
Peak memory 201852 kb
Host smart-899085f0-5c19-43ca-b7db-dcae5392cc75
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642614987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3642614987
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2416403471
Short name T481
Test name
Test status
Simulation time 161382799962 ps
CPU time 381.77 seconds
Started Jul 07 06:02:59 PM PDT 24
Finished Jul 07 06:09:21 PM PDT 24
Peak memory 201968 kb
Host smart-a2f74a2e-79c5-4b7f-92dc-20eb35416abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416403471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2416403471
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.564306027
Short name T505
Test name
Test status
Simulation time 495061571289 ps
CPU time 1129.05 seconds
Started Jul 07 06:02:58 PM PDT 24
Finished Jul 07 06:21:47 PM PDT 24
Peak memory 201932 kb
Host smart-6810607e-ac27-4c68-b80e-e75ba68f95b4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=564306027 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fixe
d.564306027
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1799943163
Short name T396
Test name
Test status
Simulation time 198218271355 ps
CPU time 461.92 seconds
Started Jul 07 06:02:57 PM PDT 24
Finished Jul 07 06:10:39 PM PDT 24
Peak memory 201856 kb
Host smart-0b9f87e3-aa5b-4cf3-8ee3-d25cc3f8c342
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799943163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1799943163
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.1828253616
Short name T622
Test name
Test status
Simulation time 93937172754 ps
CPU time 363.38 seconds
Started Jul 07 06:03:00 PM PDT 24
Finished Jul 07 06:09:03 PM PDT 24
Peak memory 202296 kb
Host smart-86551b22-8b2f-4748-8f5a-fda01efc6dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828253616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.1828253616
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.1160897952
Short name T673
Test name
Test status
Simulation time 43236171847 ps
CPU time 46.7 seconds
Started Jul 07 06:03:01 PM PDT 24
Finished Jul 07 06:03:48 PM PDT 24
Peak memory 201688 kb
Host smart-15d45f6e-84a5-4cfb-8d4f-6f5864e5cff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160897952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.1160897952
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.3553455617
Short name T112
Test name
Test status
Simulation time 3676462676 ps
CPU time 2.87 seconds
Started Jul 07 06:03:01 PM PDT 24
Finished Jul 07 06:03:04 PM PDT 24
Peak memory 201640 kb
Host smart-e34e47ca-bf26-4f3f-9fa9-6eae16fcb2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553455617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.3553455617
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2437192289
Short name T775
Test name
Test status
Simulation time 5771612970 ps
CPU time 7.33 seconds
Started Jul 07 06:02:56 PM PDT 24
Finished Jul 07 06:03:03 PM PDT 24
Peak memory 201688 kb
Host smart-2786ad31-eb9f-4f98-9f7a-06e126a7756d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437192289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2437192289
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.797510844
Short name T777
Test name
Test status
Simulation time 431771606857 ps
CPU time 1190.1 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:22:54 PM PDT 24
Peak memory 202248 kb
Host smart-86da0ae8-5225-47fa-bfde-69972e838e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797510844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all.
797510844
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3581763166
Short name T291
Test name
Test status
Simulation time 172996064986 ps
CPU time 156.19 seconds
Started Jul 07 06:03:03 PM PDT 24
Finished Jul 07 06:05:39 PM PDT 24
Peak memory 210592 kb
Host smart-a00cfc33-ffc8-46f7-bc24-74c45493d6ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581763166 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3581763166
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3314393560
Short name T390
Test name
Test status
Simulation time 402823200 ps
CPU time 0.87 seconds
Started Jul 07 06:03:14 PM PDT 24
Finished Jul 07 06:03:15 PM PDT 24
Peak memory 201652 kb
Host smart-f40eb955-1325-482e-aecf-0fed4247856b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314393560 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3314393560
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.2328341611
Short name T271
Test name
Test status
Simulation time 350646221875 ps
CPU time 812.23 seconds
Started Jul 07 06:03:13 PM PDT 24
Finished Jul 07 06:16:45 PM PDT 24
Peak memory 201912 kb
Host smart-a5810232-b5db-4584-8dc6-7413476d1a35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328341611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.2328341611
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.653251606
Short name T148
Test name
Test status
Simulation time 493308861713 ps
CPU time 90.66 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:04:35 PM PDT 24
Peak memory 201948 kb
Host smart-0c970b4b-3519-4a8d-be25-39f21c1938d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653251606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.653251606
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.654653682
Short name T639
Test name
Test status
Simulation time 165545098873 ps
CPU time 185.43 seconds
Started Jul 07 06:03:06 PM PDT 24
Finished Jul 07 06:06:12 PM PDT 24
Peak memory 201860 kb
Host smart-0ae32956-704b-49c5-bca2-5eb48b1eca97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=654653682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrup
t_fixed.654653682
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1011419289
Short name T508
Test name
Test status
Simulation time 166509271647 ps
CPU time 94.63 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:04:39 PM PDT 24
Peak memory 201900 kb
Host smart-bb395c2f-ffb1-423d-a93a-8431400dd27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011419289 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1011419289
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3083066455
Short name T438
Test name
Test status
Simulation time 330311565708 ps
CPU time 750.44 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:15:35 PM PDT 24
Peak memory 201844 kb
Host smart-f6331ffe-2421-4299-a945-a057deda879f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083066455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3083066455
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3897488509
Short name T311
Test name
Test status
Simulation time 562277383924 ps
CPU time 1282.45 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:24:27 PM PDT 24
Peak memory 201952 kb
Host smart-4485081f-d5b3-44a9-907d-b529b0f35a01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3897488509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3897488509
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.3084949562
Short name T558
Test name
Test status
Simulation time 205375675963 ps
CPU time 488.85 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:11:13 PM PDT 24
Peak memory 201872 kb
Host smart-b251c2b8-8eba-49db-b0cc-edd13ea31d98
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084949562 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.3084949562
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.3659984663
Short name T212
Test name
Test status
Simulation time 107753364384 ps
CPU time 421.17 seconds
Started Jul 07 06:03:07 PM PDT 24
Finished Jul 07 06:10:08 PM PDT 24
Peak memory 202232 kb
Host smart-edaff887-5fe3-4a68-9a6f-ffd24fff21fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659984663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.3659984663
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2907878192
Short name T711
Test name
Test status
Simulation time 21859517943 ps
CPU time 48.42 seconds
Started Jul 07 06:03:11 PM PDT 24
Finished Jul 07 06:04:00 PM PDT 24
Peak memory 201712 kb
Host smart-a6fa4000-75d1-4623-a400-b9f46ae645d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907878192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2907878192
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2495717961
Short name T446
Test name
Test status
Simulation time 3875914319 ps
CPU time 9.57 seconds
Started Jul 07 06:03:07 PM PDT 24
Finished Jul 07 06:03:17 PM PDT 24
Peak memory 201708 kb
Host smart-040c8efc-c40f-46a3-b2db-6cf678928322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495717961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2495717961
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.559798656
Short name T721
Test name
Test status
Simulation time 5994586081 ps
CPU time 7.34 seconds
Started Jul 07 06:03:04 PM PDT 24
Finished Jul 07 06:03:11 PM PDT 24
Peak memory 201608 kb
Host smart-b5b20447-da0e-4b8a-b20b-896f483dd08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559798656 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.559798656
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3856691943
Short name T370
Test name
Test status
Simulation time 40098969638 ps
CPU time 47.11 seconds
Started Jul 07 06:03:14 PM PDT 24
Finished Jul 07 06:04:01 PM PDT 24
Peak memory 201696 kb
Host smart-254409f0-1982-4650-bb20-7207c8e8ac21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856691943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3856691943
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2789554394
Short name T23
Test name
Test status
Simulation time 1302089471424 ps
CPU time 861.89 seconds
Started Jul 07 06:03:17 PM PDT 24
Finished Jul 07 06:17:39 PM PDT 24
Peak memory 210732 kb
Host smart-3190f473-f610-496c-ae48-e90d1471b542
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789554394 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2789554394
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.974050820
Short name T499
Test name
Test status
Simulation time 282582772 ps
CPU time 1.33 seconds
Started Jul 07 06:03:26 PM PDT 24
Finished Jul 07 06:03:28 PM PDT 24
Peak memory 201628 kb
Host smart-04466d10-b210-4dee-930d-bf90f286886a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974050820 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.974050820
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.3017087598
Short name T628
Test name
Test status
Simulation time 490418533655 ps
CPU time 908.82 seconds
Started Jul 07 06:03:16 PM PDT 24
Finished Jul 07 06:18:25 PM PDT 24
Peak memory 201828 kb
Host smart-34fcdacd-741b-4a31-9051-bbf8b931d359
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017087598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.3017087598
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.637069147
Short name T474
Test name
Test status
Simulation time 160857979747 ps
CPU time 267.47 seconds
Started Jul 07 06:03:15 PM PDT 24
Finished Jul 07 06:07:43 PM PDT 24
Peak memory 201904 kb
Host smart-08af4046-8659-45ec-b300-bfdaca537ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637069147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.637069147
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2027451591
Short name T501
Test name
Test status
Simulation time 170305076721 ps
CPU time 381.61 seconds
Started Jul 07 06:03:18 PM PDT 24
Finished Jul 07 06:09:40 PM PDT 24
Peak memory 201812 kb
Host smart-c98b1a38-5e8b-4729-bc1b-228ed9d11996
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027451591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2027451591
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1639642964
Short name T764
Test name
Test status
Simulation time 329429075778 ps
CPU time 712.8 seconds
Started Jul 07 06:03:14 PM PDT 24
Finished Jul 07 06:15:07 PM PDT 24
Peak memory 201904 kb
Host smart-8012dcda-fe28-48b5-880a-4f41c4f66cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639642964 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1639642964
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.237776335
Short name T425
Test name
Test status
Simulation time 158557167988 ps
CPU time 164.44 seconds
Started Jul 07 06:03:11 PM PDT 24
Finished Jul 07 06:05:56 PM PDT 24
Peak memory 201892 kb
Host smart-ec5ec171-9b5b-43e2-a769-6c8f645beedd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=237776335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.237776335
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3870871784
Short name T302
Test name
Test status
Simulation time 547560362446 ps
CPU time 1256.11 seconds
Started Jul 07 06:03:15 PM PDT 24
Finished Jul 07 06:24:11 PM PDT 24
Peak memory 201980 kb
Host smart-1a54d43a-e03d-4153-b337-e58c01971758
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870871784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3870871784
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.3471094320
Short name T510
Test name
Test status
Simulation time 614248822343 ps
CPU time 1294.66 seconds
Started Jul 07 06:03:15 PM PDT 24
Finished Jul 07 06:24:50 PM PDT 24
Peak memory 201848 kb
Host smart-22f59ab7-15f6-428b-bce6-e9fb923e0c96
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471094320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.3471094320
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.364547366
Short name T43
Test name
Test status
Simulation time 106425987973 ps
CPU time 508.12 seconds
Started Jul 07 06:03:21 PM PDT 24
Finished Jul 07 06:11:49 PM PDT 24
Peak memory 202248 kb
Host smart-2d81d1e9-62e3-4345-b6d1-3e1427fd8b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364547366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.364547366
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.2229254274
Short name T473
Test name
Test status
Simulation time 45468971153 ps
CPU time 96.5 seconds
Started Jul 07 06:03:24 PM PDT 24
Finished Jul 07 06:05:01 PM PDT 24
Peak memory 201708 kb
Host smart-56ceb2b2-3d12-4b44-83c4-ad9233c17ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229254274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.2229254274
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3101329514
Short name T603
Test name
Test status
Simulation time 2752954159 ps
CPU time 1.84 seconds
Started Jul 07 06:03:16 PM PDT 24
Finished Jul 07 06:03:18 PM PDT 24
Peak memory 201688 kb
Host smart-333a1746-0719-493d-af82-7d0e88aae88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101329514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3101329514
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1169268597
Short name T614
Test name
Test status
Simulation time 6057472879 ps
CPU time 7.26 seconds
Started Jul 07 06:03:15 PM PDT 24
Finished Jul 07 06:03:22 PM PDT 24
Peak memory 201696 kb
Host smart-37e09859-0664-4f89-b5f6-3ce7074b0f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169268597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1169268597
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.1611305335
Short name T760
Test name
Test status
Simulation time 376061775863 ps
CPU time 326.46 seconds
Started Jul 07 06:03:19 PM PDT 24
Finished Jul 07 06:08:46 PM PDT 24
Peak memory 201896 kb
Host smart-552adb96-9c7f-4660-9ad6-a73a68811a9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611305335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.1611305335
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.1839613259
Short name T42
Test name
Test status
Simulation time 120761156665 ps
CPU time 370.97 seconds
Started Jul 07 06:03:18 PM PDT 24
Finished Jul 07 06:09:29 PM PDT 24
Peak memory 210824 kb
Host smart-7428d4fb-a16d-4c23-b9e9-e9c1c28d98e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839613259 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.1839613259
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.3551138942
Short name T638
Test name
Test status
Simulation time 415487538 ps
CPU time 0.97 seconds
Started Jul 07 06:03:38 PM PDT 24
Finished Jul 07 06:03:39 PM PDT 24
Peak memory 201648 kb
Host smart-3ff33adc-64f2-4a4a-a67b-ba0fcf89018e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551138942 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.3551138942
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1411780636
Short name T174
Test name
Test status
Simulation time 518831357458 ps
CPU time 116.8 seconds
Started Jul 07 06:03:28 PM PDT 24
Finished Jul 07 06:05:25 PM PDT 24
Peak memory 201896 kb
Host smart-a87a03a3-71dd-4fef-8ab3-0443eaca161e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411780636 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1411780636
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.2088528035
Short name T158
Test name
Test status
Simulation time 342024876234 ps
CPU time 197.46 seconds
Started Jul 07 06:03:28 PM PDT 24
Finished Jul 07 06:06:45 PM PDT 24
Peak memory 201876 kb
Host smart-89875de4-9bce-458c-8032-5c18a2fba413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088528035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.2088528035
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.3029021045
Short name T189
Test name
Test status
Simulation time 486368989025 ps
CPU time 553.76 seconds
Started Jul 07 06:03:28 PM PDT 24
Finished Jul 07 06:12:42 PM PDT 24
Peak memory 201884 kb
Host smart-64dc3882-203c-489e-ad91-ce900f1b3899
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029021045 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.3029021045
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3644109872
Short name T605
Test name
Test status
Simulation time 169023354759 ps
CPU time 53.94 seconds
Started Jul 07 06:03:24 PM PDT 24
Finished Jul 07 06:04:18 PM PDT 24
Peak memory 201904 kb
Host smart-86e222f5-9de7-454b-875d-65a676e00019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644109872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3644109872
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.453358576
Short name T467
Test name
Test status
Simulation time 325492370137 ps
CPU time 160.62 seconds
Started Jul 07 06:03:26 PM PDT 24
Finished Jul 07 06:06:06 PM PDT 24
Peak memory 201920 kb
Host smart-0d760a8e-8cc6-4d53-88cb-016877ccda58
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=453358576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fixe
d.453358576
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3705910475
Short name T161
Test name
Test status
Simulation time 359807095575 ps
CPU time 782.55 seconds
Started Jul 07 06:03:28 PM PDT 24
Finished Jul 07 06:16:31 PM PDT 24
Peak memory 201904 kb
Host smart-1417d9f3-8f52-4098-87ad-05f86d8f74fb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705910475 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3705910475
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2082924067
Short name T714
Test name
Test status
Simulation time 621966635880 ps
CPU time 718.65 seconds
Started Jul 07 06:03:27 PM PDT 24
Finished Jul 07 06:15:26 PM PDT 24
Peak memory 201868 kb
Host smart-2a540aba-802d-471e-9816-6d67fe1c3673
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082924067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2082924067
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.3324844436
Short name T664
Test name
Test status
Simulation time 86595284328 ps
CPU time 291.98 seconds
Started Jul 07 06:03:30 PM PDT 24
Finished Jul 07 06:08:23 PM PDT 24
Peak memory 202220 kb
Host smart-bf9a6488-1cd5-46d5-8f07-7110a3d64140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324844436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.3324844436
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.1665535660
Short name T545
Test name
Test status
Simulation time 24515409534 ps
CPU time 11.83 seconds
Started Jul 07 06:03:37 PM PDT 24
Finished Jul 07 06:03:49 PM PDT 24
Peak memory 201700 kb
Host smart-4d27d56d-9840-4056-bba9-fad3309466bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665535660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.1665535660
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.4027649712
Short name T376
Test name
Test status
Simulation time 5063968871 ps
CPU time 12.5 seconds
Started Jul 07 06:03:26 PM PDT 24
Finished Jul 07 06:03:39 PM PDT 24
Peak memory 201724 kb
Host smart-9b814241-7660-406f-bd13-fc356fdf8795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027649712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.4027649712
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.2171157464
Short name T83
Test name
Test status
Simulation time 5774870855 ps
CPU time 3.44 seconds
Started Jul 07 06:03:23 PM PDT 24
Finished Jul 07 06:03:26 PM PDT 24
Peak memory 201704 kb
Host smart-95af77a4-57a0-4010-adf0-c732ed7a4ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171157464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.2171157464
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1571279537
Short name T243
Test name
Test status
Simulation time 383342865534 ps
CPU time 227.97 seconds
Started Jul 07 06:03:30 PM PDT 24
Finished Jul 07 06:07:18 PM PDT 24
Peak memory 201860 kb
Host smart-fe2d61bb-d5fc-4b5d-a32d-1314237f9424
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571279537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1571279537
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.849139486
Short name T498
Test name
Test status
Simulation time 412892295 ps
CPU time 1.11 seconds
Started Jul 07 06:03:44 PM PDT 24
Finished Jul 07 06:03:45 PM PDT 24
Peak memory 201660 kb
Host smart-b33d7abd-70ad-4420-9df2-6697c4af8968
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849139486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.849139486
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.1599047080
Short name T180
Test name
Test status
Simulation time 511594974031 ps
CPU time 170.88 seconds
Started Jul 07 06:03:38 PM PDT 24
Finished Jul 07 06:06:29 PM PDT 24
Peak memory 201892 kb
Host smart-6418aa7e-ce11-4629-8efb-e7be7666aa47
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599047080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gat
ing.1599047080
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2309821292
Short name T172
Test name
Test status
Simulation time 159696137094 ps
CPU time 363.6 seconds
Started Jul 07 06:03:39 PM PDT 24
Finished Jul 07 06:09:43 PM PDT 24
Peak memory 201948 kb
Host smart-bee2857d-7128-41ce-a60a-6c813cd880f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309821292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2309821292
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.2238627151
Short name T290
Test name
Test status
Simulation time 334182091010 ps
CPU time 213.2 seconds
Started Jul 07 06:03:33 PM PDT 24
Finished Jul 07 06:07:07 PM PDT 24
Peak memory 201808 kb
Host smart-7972c8fe-1434-4dba-9370-2d295817682b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238627151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.2238627151
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.1372101165
Short name T493
Test name
Test status
Simulation time 333386358317 ps
CPU time 208.81 seconds
Started Jul 07 06:03:38 PM PDT 24
Finished Jul 07 06:07:07 PM PDT 24
Peak memory 201884 kb
Host smart-3c93c90b-b595-4f0b-9c17-22a371872cc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372101165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.1372101165
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.3346999327
Short name T179
Test name
Test status
Simulation time 483926168762 ps
CPU time 258.88 seconds
Started Jul 07 06:03:34 PM PDT 24
Finished Jul 07 06:07:53 PM PDT 24
Peak memory 201904 kb
Host smart-bc2785bf-4e9e-467c-801f-29ff272d960a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346999327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.3346999327
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.2036119896
Short name T479
Test name
Test status
Simulation time 161359412926 ps
CPU time 322.55 seconds
Started Jul 07 06:03:32 PM PDT 24
Finished Jul 07 06:08:55 PM PDT 24
Peak memory 201868 kb
Host smart-62e0c6af-cb60-481d-9d81-1bc1ce1e2b1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036119896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.2036119896
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3139337928
Short name T635
Test name
Test status
Simulation time 186709040425 ps
CPU time 117.01 seconds
Started Jul 07 06:03:33 PM PDT 24
Finished Jul 07 06:05:31 PM PDT 24
Peak memory 201964 kb
Host smart-b86f0a8d-9ae5-4bd0-b18c-e2bf550e6e90
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139337928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3139337928
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.3995050676
Short name T369
Test name
Test status
Simulation time 198955127976 ps
CPU time 217.65 seconds
Started Jul 07 06:03:38 PM PDT 24
Finished Jul 07 06:07:16 PM PDT 24
Peak memory 201884 kb
Host smart-a63914b3-6760-4a86-8945-9a77d39eb5c7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995050676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.3995050676
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2882813592
Short name T210
Test name
Test status
Simulation time 128933332881 ps
CPU time 455.8 seconds
Started Jul 07 06:03:39 PM PDT 24
Finished Jul 07 06:11:15 PM PDT 24
Peak memory 202212 kb
Host smart-135fa0e2-a70e-4e26-856a-bf9072d77ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882813592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2882813592
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.3958134097
Short name T166
Test name
Test status
Simulation time 46293201766 ps
CPU time 99.11 seconds
Started Jul 07 06:03:38 PM PDT 24
Finished Jul 07 06:05:17 PM PDT 24
Peak memory 201708 kb
Host smart-9aaf5ba5-fe14-49f4-b92f-d721bd94ae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958134097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.3958134097
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.4029830972
Short name T633
Test name
Test status
Simulation time 4637588911 ps
CPU time 5.64 seconds
Started Jul 07 06:03:38 PM PDT 24
Finished Jul 07 06:03:44 PM PDT 24
Peak memory 201640 kb
Host smart-773b3980-48e6-4204-a517-d5ef1f0f17cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029830972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.4029830972
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.1155536671
Short name T371
Test name
Test status
Simulation time 5905575250 ps
CPU time 12.31 seconds
Started Jul 07 06:03:34 PM PDT 24
Finished Jul 07 06:03:47 PM PDT 24
Peak memory 201696 kb
Host smart-1085d3e4-4e85-406d-affa-2b8fdc505779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155536671 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.1155536671
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.3342346471
Short name T27
Test name
Test status
Simulation time 341131051136 ps
CPU time 200.04 seconds
Started Jul 07 06:03:43 PM PDT 24
Finished Jul 07 06:07:03 PM PDT 24
Peak memory 201864 kb
Host smart-4c980084-0841-4b68-9a20-89fa3fb55196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342346471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.3342346471
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.1251918483
Short name T225
Test name
Test status
Simulation time 313681983048 ps
CPU time 216.06 seconds
Started Jul 07 06:03:41 PM PDT 24
Finished Jul 07 06:07:17 PM PDT 24
Peak memory 210572 kb
Host smart-8e06a0b1-7fa1-46d2-bb02-0133cc9486a6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251918483 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.1251918483
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.2787545347
Short name T459
Test name
Test status
Simulation time 419245736 ps
CPU time 0.79 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:00:39 PM PDT 24
Peak memory 201692 kb
Host smart-35e4d560-6c49-4e5c-9b3e-4b0b1d101255
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787545347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.2787545347
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.1560444172
Short name T138
Test name
Test status
Simulation time 160368355185 ps
CPU time 32.1 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:01:08 PM PDT 24
Peak memory 201900 kb
Host smart-38655a9f-5908-4619-938f-2b1b2dcf465c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560444172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.1560444172
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.782126723
Short name T321
Test name
Test status
Simulation time 167577807016 ps
CPU time 322.4 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:05:59 PM PDT 24
Peak memory 201904 kb
Host smart-16d7951c-e1d0-44dc-96a7-32d98e6ead18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782126723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.782126723
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.83807453
Short name T392
Test name
Test status
Simulation time 167057645022 ps
CPU time 60.67 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:01:44 PM PDT 24
Peak memory 201880 kb
Host smart-e6b126b7-aed6-4dac-abce-592841636a3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=83807453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt_
fixed.83807453
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.543844672
Short name T246
Test name
Test status
Simulation time 490661777341 ps
CPU time 1151.07 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:19:49 PM PDT 24
Peak memory 201876 kb
Host smart-6bcab1e8-2383-4c1d-b30a-b07b5620c668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543844672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.543844672
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.2387556087
Short name T414
Test name
Test status
Simulation time 483007658634 ps
CPU time 458.94 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:08:15 PM PDT 24
Peak memory 201828 kb
Host smart-b22c5853-ad5d-4ab0-a301-e9562d6859b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387556087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixe
d.2387556087
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.3236449247
Short name T256
Test name
Test status
Simulation time 510748779887 ps
CPU time 540.16 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:09:36 PM PDT 24
Peak memory 201976 kb
Host smart-53d907c7-0fbe-4853-ab0a-b92bebc42615
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236449247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.3236449247
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2565739850
Short name T363
Test name
Test status
Simulation time 208212805532 ps
CPU time 464 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:08:19 PM PDT 24
Peak memory 201888 kb
Host smart-1e7b25e0-ae56-401e-8ec4-0d3c1cbbafde
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565739850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2565739850
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.193036134
Short name T759
Test name
Test status
Simulation time 104358228591 ps
CPU time 445.82 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:08:01 PM PDT 24
Peak memory 202292 kb
Host smart-ca87c89f-08ed-4905-a65f-23a23dd118e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193036134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.193036134
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1987941835
Short name T563
Test name
Test status
Simulation time 38854544522 ps
CPU time 8.63 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:00:52 PM PDT 24
Peak memory 201696 kb
Host smart-3c0248b3-a82c-4d94-975a-8e77395388ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987941835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1987941835
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.2765209211
Short name T451
Test name
Test status
Simulation time 3885531394 ps
CPU time 1.95 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:00:38 PM PDT 24
Peak memory 201708 kb
Host smart-a975919d-a35d-4361-be5d-c3712c4ebc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765209211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.2765209211
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3924790568
Short name T84
Test name
Test status
Simulation time 5994859240 ps
CPU time 14.51 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:00:51 PM PDT 24
Peak memory 201600 kb
Host smart-29c46d6e-25a9-4e60-be4a-21a5c614b10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924790568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3924790568
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.2534244071
Short name T689
Test name
Test status
Simulation time 195548100122 ps
CPU time 111.52 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:02:34 PM PDT 24
Peak memory 201912 kb
Host smart-76fe2795-c2e2-424b-8025-7b88729b5671
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534244071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.
2534244071
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.4088673581
Short name T730
Test name
Test status
Simulation time 36656574666 ps
CPU time 85.7 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:02:05 PM PDT 24
Peak memory 202048 kb
Host smart-cefe3bac-4e48-4ea3-a6d4-5b960f7010a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088673581 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.4088673581
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.2297887863
Short name T406
Test name
Test status
Simulation time 392124023 ps
CPU time 1.4 seconds
Started Jul 07 06:03:50 PM PDT 24
Finished Jul 07 06:03:51 PM PDT 24
Peak memory 201660 kb
Host smart-529e79c2-b28a-4504-b1d8-f192c28d1a2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297887863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.2297887863
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.4246494492
Short name T37
Test name
Test status
Simulation time 170156907560 ps
CPU time 402.25 seconds
Started Jul 07 06:03:48 PM PDT 24
Finished Jul 07 06:10:30 PM PDT 24
Peak memory 201908 kb
Host smart-c803bade-8c64-4975-a033-bc11ee1a845d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246494492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.4246494492
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.1378267228
Short name T247
Test name
Test status
Simulation time 328930506955 ps
CPU time 162.88 seconds
Started Jul 07 06:03:47 PM PDT 24
Finished Jul 07 06:06:30 PM PDT 24
Peak memory 201952 kb
Host smart-229a498e-0345-4785-87f5-1f2b95b95c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378267228 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.1378267228
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.625463504
Short name T516
Test name
Test status
Simulation time 163217946778 ps
CPU time 98.29 seconds
Started Jul 07 06:03:43 PM PDT 24
Finished Jul 07 06:05:22 PM PDT 24
Peak memory 201844 kb
Host smart-3cca8d40-bc16-4c48-838c-ff3ae038ca2d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=625463504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrup
t_fixed.625463504
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1844415446
Short name T293
Test name
Test status
Simulation time 483800182558 ps
CPU time 1102.73 seconds
Started Jul 07 06:03:47 PM PDT 24
Finished Jul 07 06:22:10 PM PDT 24
Peak memory 201896 kb
Host smart-a38216e2-cb0c-4ca1-a881-72a6002bec39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844415446 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1844415446
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2797927041
Short name T621
Test name
Test status
Simulation time 160718994996 ps
CPU time 97.1 seconds
Started Jul 07 06:03:43 PM PDT 24
Finished Jul 07 06:05:21 PM PDT 24
Peak memory 201780 kb
Host smart-796adf91-8d56-4307-ac9b-7445d5cc578c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797927041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2797927041
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.2015052749
Short name T306
Test name
Test status
Simulation time 195279252541 ps
CPU time 34.09 seconds
Started Jul 07 06:03:53 PM PDT 24
Finished Jul 07 06:04:27 PM PDT 24
Peak memory 201904 kb
Host smart-029423bd-0d91-4985-99a6-ce69635a0ef1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015052749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.2015052749
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.43230596
Short name T426
Test name
Test status
Simulation time 596601098860 ps
CPU time 681.68 seconds
Started Jul 07 06:03:47 PM PDT 24
Finished Jul 07 06:15:09 PM PDT 24
Peak memory 201876 kb
Host smart-4cf641af-25f1-4487-bf6d-03aa9a115aff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43230596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.a
dc_ctrl_filters_wakeup_fixed.43230596
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.3772003827
Short name T747
Test name
Test status
Simulation time 81236568784 ps
CPU time 329.58 seconds
Started Jul 07 06:03:48 PM PDT 24
Finished Jul 07 06:09:17 PM PDT 24
Peak memory 202260 kb
Host smart-add344e6-b4fc-483f-88ee-ed81d0dbf37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772003827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.3772003827
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.114264157
Short name T423
Test name
Test status
Simulation time 26962175675 ps
CPU time 13.08 seconds
Started Jul 07 06:03:49 PM PDT 24
Finished Jul 07 06:04:03 PM PDT 24
Peak memory 201720 kb
Host smart-5835ab9d-6e0d-4c8d-adaf-8c5af15fb140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114264157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.114264157
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.4078149332
Short name T680
Test name
Test status
Simulation time 2791050866 ps
CPU time 7.62 seconds
Started Jul 07 06:03:54 PM PDT 24
Finished Jul 07 06:04:02 PM PDT 24
Peak memory 201696 kb
Host smart-e8371e59-74a3-43bb-9971-aeb39520c71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078149332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.4078149332
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4278932713
Short name T623
Test name
Test status
Simulation time 5612284116 ps
CPU time 12.99 seconds
Started Jul 07 06:03:44 PM PDT 24
Finished Jul 07 06:03:57 PM PDT 24
Peak memory 201696 kb
Host smart-eadbc3ad-fe1a-41cc-b815-210ab19d9bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278932713 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4278932713
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.1244985220
Short name T696
Test name
Test status
Simulation time 294058043435 ps
CPU time 549.75 seconds
Started Jul 07 06:03:50 PM PDT 24
Finished Jul 07 06:13:00 PM PDT 24
Peak memory 210332 kb
Host smart-aa2221fa-8d5d-4148-9eca-dfedeaae0843
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244985220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.1244985220
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.1044171087
Short name T17
Test name
Test status
Simulation time 39909848828 ps
CPU time 93.84 seconds
Started Jul 07 06:03:50 PM PDT 24
Finished Jul 07 06:05:24 PM PDT 24
Peak memory 201996 kb
Host smart-e51fa2df-af44-4d91-a483-c6fd2cfe855c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044171087 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.1044171087
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.994098435
Short name T530
Test name
Test status
Simulation time 432007697 ps
CPU time 1.16 seconds
Started Jul 07 06:04:09 PM PDT 24
Finished Jul 07 06:04:11 PM PDT 24
Peak memory 201648 kb
Host smart-c084230a-8275-4af6-b3e6-7cd2c884821e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994098435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.994098435
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.174789175
Short name T314
Test name
Test status
Simulation time 351257196634 ps
CPU time 41.63 seconds
Started Jul 07 06:04:03 PM PDT 24
Finished Jul 07 06:04:45 PM PDT 24
Peak memory 201892 kb
Host smart-db812e12-72dd-46ce-869e-6f2e977c9094
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174789175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gati
ng.174789175
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.3264368122
Short name T779
Test name
Test status
Simulation time 495523436317 ps
CPU time 289.68 seconds
Started Jul 07 06:03:56 PM PDT 24
Finished Jul 07 06:08:46 PM PDT 24
Peak memory 201892 kb
Host smart-a8412975-5abf-4fe7-83ee-bedf4dd0e546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264368122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.3264368122
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.3662931116
Short name T350
Test name
Test status
Simulation time 335590588320 ps
CPU time 95.65 seconds
Started Jul 07 06:04:02 PM PDT 24
Finished Jul 07 06:05:38 PM PDT 24
Peak memory 201736 kb
Host smart-991c1582-da05-4eaa-a808-93279ff57574
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662931116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.3662931116
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2863066367
Short name T513
Test name
Test status
Simulation time 161593123097 ps
CPU time 102.36 seconds
Started Jul 07 06:03:55 PM PDT 24
Finished Jul 07 06:05:38 PM PDT 24
Peak memory 201888 kb
Host smart-445b6601-a1f0-4e0e-84b5-7521013dd826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863066367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2863066367
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2380668870
Short name T487
Test name
Test status
Simulation time 493426911421 ps
CPU time 1004.53 seconds
Started Jul 07 06:03:56 PM PDT 24
Finished Jul 07 06:20:41 PM PDT 24
Peak memory 201932 kb
Host smart-5e50c3b0-13d9-48ef-872d-18c2a2d4f590
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380668870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2380668870
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2355187138
Short name T87
Test name
Test status
Simulation time 566723636517 ps
CPU time 1297.74 seconds
Started Jul 07 06:04:00 PM PDT 24
Finished Jul 07 06:25:38 PM PDT 24
Peak memory 201908 kb
Host smart-b597a922-ef13-4f53-8312-43849028b5cf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355187138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2355187138
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1798272729
Short name T452
Test name
Test status
Simulation time 608776375239 ps
CPU time 399.54 seconds
Started Jul 07 06:04:03 PM PDT 24
Finished Jul 07 06:10:43 PM PDT 24
Peak memory 201888 kb
Host smart-aa833e10-99d0-4555-9ed2-9b7991cc5460
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798272729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1798272729
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2874348304
Short name T40
Test name
Test status
Simulation time 111662429049 ps
CPU time 447.8 seconds
Started Jul 07 06:04:05 PM PDT 24
Finished Jul 07 06:11:34 PM PDT 24
Peak memory 202216 kb
Host smart-6ac578b0-b1b4-4682-9059-b03b67b9770b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874348304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2874348304
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1660957173
Short name T416
Test name
Test status
Simulation time 42051713276 ps
CPU time 49.61 seconds
Started Jul 07 06:04:05 PM PDT 24
Finished Jul 07 06:04:55 PM PDT 24
Peak memory 201692 kb
Host smart-4a2b2a59-82e5-4b26-b2cf-cba1e2cc1477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660957173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1660957173
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1462822724
Short name T649
Test name
Test status
Simulation time 2887187796 ps
CPU time 2.29 seconds
Started Jul 07 06:04:04 PM PDT 24
Finished Jul 07 06:04:07 PM PDT 24
Peak memory 201664 kb
Host smart-8d894208-fc31-41d3-b96b-87937190e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462822724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1462822724
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.174491186
Short name T359
Test name
Test status
Simulation time 5623519045 ps
CPU time 11.65 seconds
Started Jul 07 06:03:55 PM PDT 24
Finished Jul 07 06:04:06 PM PDT 24
Peak memory 201712 kb
Host smart-3534f36f-d3f6-45e1-af5f-430d733c38f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174491186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.174491186
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.917842836
Short name T47
Test name
Test status
Simulation time 174523535552 ps
CPU time 232.67 seconds
Started Jul 07 06:04:05 PM PDT 24
Finished Jul 07 06:07:58 PM PDT 24
Peak memory 201856 kb
Host smart-63b6eda2-fdbc-4ca4-8a0d-a9b640f4f5ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917842836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
917842836
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.1183118873
Short name T365
Test name
Test status
Simulation time 451003344 ps
CPU time 0.89 seconds
Started Jul 07 06:04:20 PM PDT 24
Finished Jul 07 06:04:22 PM PDT 24
Peak memory 201640 kb
Host smart-956f3220-f912-4cfb-9add-d6a3b53982cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183118873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.1183118873
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.2754548900
Short name T529
Test name
Test status
Simulation time 490681341046 ps
CPU time 531.16 seconds
Started Jul 07 06:04:13 PM PDT 24
Finished Jul 07 06:13:05 PM PDT 24
Peak memory 201888 kb
Host smart-9cf9c777-b0b4-452c-a038-db6f54eb0bcd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754548900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.2754548900
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.166256002
Short name T221
Test name
Test status
Simulation time 567977018584 ps
CPU time 180.6 seconds
Started Jul 07 06:04:14 PM PDT 24
Finished Jul 07 06:07:15 PM PDT 24
Peak memory 201908 kb
Host smart-82d2b44d-7c5d-4338-bac7-d742d604bd4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166256002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.166256002
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.2308636478
Short name T471
Test name
Test status
Simulation time 324002681273 ps
CPU time 626.77 seconds
Started Jul 07 06:04:08 PM PDT 24
Finished Jul 07 06:14:35 PM PDT 24
Peak memory 201892 kb
Host smart-c80e8ee5-85f8-41be-9595-b1fe8246e59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308636478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.2308636478
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1854263280
Short name T755
Test name
Test status
Simulation time 492235397859 ps
CPU time 1082.46 seconds
Started Jul 07 06:04:08 PM PDT 24
Finished Jul 07 06:22:11 PM PDT 24
Peak memory 201856 kb
Host smart-3d329d72-974a-4dfe-9390-d504a11b50b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854263280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1854263280
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2156205674
Short name T724
Test name
Test status
Simulation time 167970388618 ps
CPU time 365.71 seconds
Started Jul 07 06:04:14 PM PDT 24
Finished Jul 07 06:10:20 PM PDT 24
Peak memory 201892 kb
Host smart-da8fabb6-c466-481d-909d-c5bd45f7408a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156205674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2156205674
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.2045815029
Short name T394
Test name
Test status
Simulation time 335462347670 ps
CPU time 96.57 seconds
Started Jul 07 06:04:11 PM PDT 24
Finished Jul 07 06:05:48 PM PDT 24
Peak memory 201852 kb
Host smart-f6d7a080-8fe9-4d06-afab-59c283ae6829
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045815029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.2045815029
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.2384765865
Short name T305
Test name
Test status
Simulation time 408084077627 ps
CPU time 439.58 seconds
Started Jul 07 06:04:11 PM PDT 24
Finished Jul 07 06:11:31 PM PDT 24
Peak memory 201948 kb
Host smart-36c41009-2c8f-465a-abfc-c1a35d2ca98a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384765865 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.2384765865
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.4028168482
Short name T199
Test name
Test status
Simulation time 192881268695 ps
CPU time 417.17 seconds
Started Jul 07 06:04:14 PM PDT 24
Finished Jul 07 06:11:12 PM PDT 24
Peak memory 201876 kb
Host smart-5742c0ce-d596-4994-b0f8-f0600cfb2310
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028168482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.4028168482
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2522858861
Short name T615
Test name
Test status
Simulation time 57560030613 ps
CPU time 244.88 seconds
Started Jul 07 06:04:19 PM PDT 24
Finished Jul 07 06:08:24 PM PDT 24
Peak memory 202292 kb
Host smart-50e90fad-ae2d-4978-9c41-e934d96cdffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522858861 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2522858861
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.2873641104
Short name T193
Test name
Test status
Simulation time 41172379325 ps
CPU time 44.14 seconds
Started Jul 07 06:04:18 PM PDT 24
Finished Jul 07 06:05:03 PM PDT 24
Peak memory 201696 kb
Host smart-d3418acd-9c75-47c5-a08a-94336cf5f46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873641104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.2873641104
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.3283379340
Short name T754
Test name
Test status
Simulation time 4195669958 ps
CPU time 5.09 seconds
Started Jul 07 06:04:15 PM PDT 24
Finished Jul 07 06:04:21 PM PDT 24
Peak memory 201680 kb
Host smart-abf09807-1b5a-4628-ac00-f6fb6e3fab0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283379340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.3283379340
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.1115595612
Short name T101
Test name
Test status
Simulation time 5909176784 ps
CPU time 14.31 seconds
Started Jul 07 06:04:09 PM PDT 24
Finished Jul 07 06:04:24 PM PDT 24
Peak memory 201700 kb
Host smart-9220ed45-1e76-485c-9e15-c8f21646683d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115595612 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.1115595612
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3377987209
Short name T153
Test name
Test status
Simulation time 497563518923 ps
CPU time 213.85 seconds
Started Jul 07 06:04:18 PM PDT 24
Finished Jul 07 06:07:53 PM PDT 24
Peak memory 201932 kb
Host smart-dd00b6c9-bb93-44a2-aaca-48d23efe65e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377987209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3377987209
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2515440335
Short name T677
Test name
Test status
Simulation time 57465083904 ps
CPU time 33.55 seconds
Started Jul 07 06:04:20 PM PDT 24
Finished Jul 07 06:04:54 PM PDT 24
Peak memory 202024 kb
Host smart-c622380e-62d0-493b-828a-8f067a30f34e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515440335 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2515440335
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.2872684606
Short name T735
Test name
Test status
Simulation time 478490525 ps
CPU time 0.88 seconds
Started Jul 07 06:04:36 PM PDT 24
Finished Jul 07 06:04:38 PM PDT 24
Peak memory 201684 kb
Host smart-5995b06f-f7c1-4e93-8162-b2eacab2ede3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872684606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.2872684606
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.23086476
Short name T141
Test name
Test status
Simulation time 163785639117 ps
CPU time 163.12 seconds
Started Jul 07 06:04:28 PM PDT 24
Finished Jul 07 06:07:11 PM PDT 24
Peak memory 201952 kb
Host smart-21572502-82f1-42ea-9fa3-3aa53c50da64
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23086476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gatin
g.23086476
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3224274159
Short name T310
Test name
Test status
Simulation time 157020360111 ps
CPU time 370.78 seconds
Started Jul 07 06:04:23 PM PDT 24
Finished Jul 07 06:10:35 PM PDT 24
Peak memory 201904 kb
Host smart-1eb96d9b-5ed6-4006-88c7-62bb638b787b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224274159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3224274159
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.37562727
Short name T454
Test name
Test status
Simulation time 322729361717 ps
CPU time 168.23 seconds
Started Jul 07 06:04:23 PM PDT 24
Finished Jul 07 06:07:11 PM PDT 24
Peak memory 201908 kb
Host smart-be15480d-8597-45d7-a9f5-e03d6a132627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37562727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.37562727
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2827494305
Short name T75
Test name
Test status
Simulation time 166418656695 ps
CPU time 383.61 seconds
Started Jul 07 06:04:22 PM PDT 24
Finished Jul 07 06:10:46 PM PDT 24
Peak memory 201860 kb
Host smart-3fa6c4be-b978-4de2-b74e-9fab6a5fdfeb
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827494305 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2827494305
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.3118573344
Short name T462
Test name
Test status
Simulation time 333765625287 ps
CPU time 180.05 seconds
Started Jul 07 06:04:20 PM PDT 24
Finished Jul 07 06:07:20 PM PDT 24
Peak memory 201848 kb
Host smart-abb05a81-19de-47cf-8826-e78ddc11f301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118573344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.3118573344
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.866518871
Short name T718
Test name
Test status
Simulation time 158324255839 ps
CPU time 174.59 seconds
Started Jul 07 06:04:20 PM PDT 24
Finished Jul 07 06:07:15 PM PDT 24
Peak memory 201896 kb
Host smart-32c071ca-b44a-4b85-ad11-75db860207a8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=866518871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.866518871
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.1738155012
Short name T455
Test name
Test status
Simulation time 362465506738 ps
CPU time 811.66 seconds
Started Jul 07 06:04:20 PM PDT 24
Finished Jul 07 06:17:52 PM PDT 24
Peak memory 201896 kb
Host smart-9a150d48-3c1f-4fb6-a598-905765cc45da
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738155012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.1738155012
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.286139403
Short name T478
Test name
Test status
Simulation time 195845327632 ps
CPU time 464.94 seconds
Started Jul 07 06:04:23 PM PDT 24
Finished Jul 07 06:12:08 PM PDT 24
Peak memory 201900 kb
Host smart-b47e9376-46ee-4cac-b01f-2d6cbf5e699b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286139403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.286139403
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.1072263537
Short name T41
Test name
Test status
Simulation time 128642549733 ps
CPU time 643.41 seconds
Started Jul 07 06:04:27 PM PDT 24
Finished Jul 07 06:15:10 PM PDT 24
Peak memory 202244 kb
Host smart-e192e94a-aee6-462b-8f40-d7b7f6789353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072263537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.1072263537
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3176826997
Short name T582
Test name
Test status
Simulation time 27701428390 ps
CPU time 16.72 seconds
Started Jul 07 06:04:27 PM PDT 24
Finished Jul 07 06:04:44 PM PDT 24
Peak memory 201688 kb
Host smart-e0806978-ba7e-4c41-b55c-ec14e6ff01be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176826997 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3176826997
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.465232315
Short name T384
Test name
Test status
Simulation time 4151941181 ps
CPU time 4.99 seconds
Started Jul 07 06:04:27 PM PDT 24
Finished Jul 07 06:04:32 PM PDT 24
Peak memory 201700 kb
Host smart-0f66fe88-37d8-4c22-b0e6-1740e2c58a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465232315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.465232315
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.228847868
Short name T435
Test name
Test status
Simulation time 5977067354 ps
CPU time 6.8 seconds
Started Jul 07 06:04:20 PM PDT 24
Finished Jul 07 06:04:27 PM PDT 24
Peak memory 201636 kb
Host smart-f7cea0df-6239-4d89-b0ef-96974e1507c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228847868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.228847868
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.439273114
Short name T729
Test name
Test status
Simulation time 42429528855 ps
CPU time 77.42 seconds
Started Jul 07 06:04:28 PM PDT 24
Finished Jul 07 06:05:45 PM PDT 24
Peak memory 210536 kb
Host smart-aa9b99a3-fbda-4f8a-948d-8d4a795ab073
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439273114 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.439273114
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3952029559
Short name T569
Test name
Test status
Simulation time 426583500 ps
CPU time 1.08 seconds
Started Jul 07 06:04:40 PM PDT 24
Finished Jul 07 06:04:41 PM PDT 24
Peak memory 201644 kb
Host smart-63d4308b-861d-454a-977c-c8dfe7b33a71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952029559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3952029559
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.3506824218
Short name T791
Test name
Test status
Simulation time 505396017325 ps
CPU time 581.98 seconds
Started Jul 07 06:04:37 PM PDT 24
Finished Jul 07 06:14:20 PM PDT 24
Peak memory 201996 kb
Host smart-3c1f58ae-77fb-4911-8a68-d43c53176e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506824218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.3506824218
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.2381923480
Short name T12
Test name
Test status
Simulation time 162232421973 ps
CPU time 82.94 seconds
Started Jul 07 06:04:30 PM PDT 24
Finished Jul 07 06:05:54 PM PDT 24
Peak memory 201904 kb
Host smart-fb4d7ed7-ad0b-46b7-92c6-82500da2d58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381923480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.2381923480
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.603320994
Short name T762
Test name
Test status
Simulation time 328391149605 ps
CPU time 333.51 seconds
Started Jul 07 06:04:35 PM PDT 24
Finished Jul 07 06:10:09 PM PDT 24
Peak memory 201868 kb
Host smart-b8a2584d-a61e-41c9-a283-cc655e50cba0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=603320994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.603320994
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.2984927291
Short name T108
Test name
Test status
Simulation time 486558067384 ps
CPU time 115.08 seconds
Started Jul 07 06:04:34 PM PDT 24
Finished Jul 07 06:06:30 PM PDT 24
Peak memory 201956 kb
Host smart-968f20e7-22e9-44b3-a7c4-884eebd60954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984927291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.2984927291
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2205607145
Short name T541
Test name
Test status
Simulation time 313246497304 ps
CPU time 164.29 seconds
Started Jul 07 06:04:31 PM PDT 24
Finished Jul 07 06:07:16 PM PDT 24
Peak memory 201876 kb
Host smart-82290ac7-d165-4d67-9542-5446503ff613
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205607145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2205607145
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.3298021744
Short name T782
Test name
Test status
Simulation time 177669238654 ps
CPU time 80.11 seconds
Started Jul 07 06:04:33 PM PDT 24
Finished Jul 07 06:05:54 PM PDT 24
Peak memory 201904 kb
Host smart-6913e4f7-ca5b-4356-b2b2-0d9ff2ca31a6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298021744 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.3298021744
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2982365639
Short name T518
Test name
Test status
Simulation time 376628338647 ps
CPU time 188.1 seconds
Started Jul 07 06:04:31 PM PDT 24
Finished Jul 07 06:07:40 PM PDT 24
Peak memory 201876 kb
Host smart-1cfd35c7-5793-4939-a60e-dae351be8b54
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982365639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2982365639
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.2462582988
Short name T600
Test name
Test status
Simulation time 93074676831 ps
CPU time 349.55 seconds
Started Jul 07 06:04:34 PM PDT 24
Finished Jul 07 06:10:24 PM PDT 24
Peak memory 202480 kb
Host smart-448d8ea3-a09f-4ad8-9066-673cb7416be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462582988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.2462582988
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.958164635
Short name T443
Test name
Test status
Simulation time 33454470803 ps
CPU time 7.42 seconds
Started Jul 07 06:04:36 PM PDT 24
Finished Jul 07 06:04:45 PM PDT 24
Peak memory 201720 kb
Host smart-0ab82e5f-71fd-46bd-bc66-3cec236ac821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958164635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.958164635
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2661370122
Short name T520
Test name
Test status
Simulation time 5030490221 ps
CPU time 11.55 seconds
Started Jul 07 06:04:34 PM PDT 24
Finished Jul 07 06:04:46 PM PDT 24
Peak memory 201700 kb
Host smart-c5b9d3dd-e219-48a2-8eac-0002ec4d82e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661370122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2661370122
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.1536997566
Short name T361
Test name
Test status
Simulation time 5656745907 ps
CPU time 13.52 seconds
Started Jul 07 06:04:31 PM PDT 24
Finished Jul 07 06:04:45 PM PDT 24
Peak memory 201680 kb
Host smart-c08b01f9-b035-4335-926d-be68bf47ce03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536997566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.1536997566
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1924269695
Short name T559
Test name
Test status
Simulation time 173458677212 ps
CPU time 109.47 seconds
Started Jul 07 06:04:49 PM PDT 24
Finished Jul 07 06:06:39 PM PDT 24
Peak memory 201940 kb
Host smart-397f42cc-a5be-4e1f-ab17-1ad420e1d2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924269695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1924269695
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.2529874732
Short name T769
Test name
Test status
Simulation time 387293672763 ps
CPU time 352.79 seconds
Started Jul 07 06:04:39 PM PDT 24
Finished Jul 07 06:10:32 PM PDT 24
Peak memory 210548 kb
Host smart-65eb9532-cc9d-4871-8a23-727231bf2101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529874732 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.2529874732
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.1451337797
Short name T758
Test name
Test status
Simulation time 410912942 ps
CPU time 0.83 seconds
Started Jul 07 06:04:45 PM PDT 24
Finished Jul 07 06:04:47 PM PDT 24
Peak memory 201644 kb
Host smart-b7456722-191d-40d1-a3cc-2dfcc5052dd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451337797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.1451337797
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.502714111
Short name T279
Test name
Test status
Simulation time 325580993284 ps
CPU time 292.19 seconds
Started Jul 07 06:04:47 PM PDT 24
Finished Jul 07 06:09:40 PM PDT 24
Peak memory 201956 kb
Host smart-8415cf11-6083-439e-83e8-fcc5c63f9555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502714111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gati
ng.502714111
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3761750839
Short name T329
Test name
Test status
Simulation time 325727975292 ps
CPU time 184.74 seconds
Started Jul 07 06:04:38 PM PDT 24
Finished Jul 07 06:07:43 PM PDT 24
Peak memory 201920 kb
Host smart-f5de8d9f-d7ae-48be-b45f-cd1b812d8611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761750839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3761750839
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.1651829827
Short name T107
Test name
Test status
Simulation time 327802113138 ps
CPU time 789.27 seconds
Started Jul 07 06:04:39 PM PDT 24
Finished Jul 07 06:17:49 PM PDT 24
Peak memory 201884 kb
Host smart-ed04d709-597a-4051-bb69-3b9a5b2c935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651829827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.1651829827
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.2139304690
Short name T1
Test name
Test status
Simulation time 162845937529 ps
CPU time 100.24 seconds
Started Jul 07 06:04:47 PM PDT 24
Finished Jul 07 06:06:28 PM PDT 24
Peak memory 201864 kb
Host smart-e8a362b4-5923-4f96-8f1f-7fdcfc9b0216
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139304690 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.2139304690
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.106949060
Short name T152
Test name
Test status
Simulation time 487340894820 ps
CPU time 148.66 seconds
Started Jul 07 06:04:48 PM PDT 24
Finished Jul 07 06:07:18 PM PDT 24
Peak memory 201980 kb
Host smart-f7897e2e-88ef-4c6c-904c-f77867044e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106949060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.106949060
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1816459767
Short name T699
Test name
Test status
Simulation time 333192617969 ps
CPU time 366.74 seconds
Started Jul 07 06:04:49 PM PDT 24
Finished Jul 07 06:10:56 PM PDT 24
Peak memory 201868 kb
Host smart-5c603d58-5c46-4e41-a139-1b5f0c7b653c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816459767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1816459767
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2457401776
Short name T472
Test name
Test status
Simulation time 630495261376 ps
CPU time 291.28 seconds
Started Jul 07 06:04:42 PM PDT 24
Finished Jul 07 06:09:34 PM PDT 24
Peak memory 201848 kb
Host smart-d4a26b69-ea91-457f-a908-66e8d52909cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457401776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2457401776
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4077644922
Short name T702
Test name
Test status
Simulation time 120710024259 ps
CPU time 437.47 seconds
Started Jul 07 06:04:45 PM PDT 24
Finished Jul 07 06:12:03 PM PDT 24
Peak memory 202228 kb
Host smart-4bdfd320-b8b8-40dc-bfd9-ffa6e2d158a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077644922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4077644922
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.1063406054
Short name T741
Test name
Test status
Simulation time 40575372123 ps
CPU time 46.1 seconds
Started Jul 07 06:04:44 PM PDT 24
Finished Jul 07 06:05:30 PM PDT 24
Peak memory 201664 kb
Host smart-8a2c184e-b89d-46b1-a6d2-8446ea6a5949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063406054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.1063406054
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.4185861367
Short name T678
Test name
Test status
Simulation time 4893952858 ps
CPU time 12.04 seconds
Started Jul 07 06:04:41 PM PDT 24
Finished Jul 07 06:04:54 PM PDT 24
Peak memory 201716 kb
Host smart-33029993-f135-4540-a68a-2dbd0c83be1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185861367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.4185861367
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3349043486
Short name T542
Test name
Test status
Simulation time 5823165135 ps
CPU time 6.93 seconds
Started Jul 07 06:04:42 PM PDT 24
Finished Jul 07 06:04:49 PM PDT 24
Peak memory 201696 kb
Host smart-85b663c9-6a5e-4ed9-841d-356c4e20d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349043486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3349043486
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3702961307
Short name T627
Test name
Test status
Simulation time 58030257805 ps
CPU time 55.2 seconds
Started Jul 07 06:04:47 PM PDT 24
Finished Jul 07 06:05:43 PM PDT 24
Peak memory 210516 kb
Host smart-32d58232-7b1a-4768-bd98-66478ff7c361
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702961307 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3702961307
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1125067385
Short name T514
Test name
Test status
Simulation time 549635798 ps
CPU time 0.9 seconds
Started Jul 07 06:04:58 PM PDT 24
Finished Jul 07 06:05:00 PM PDT 24
Peak memory 201656 kb
Host smart-f74ab7e4-5ebe-42ab-b9bd-e436f8d1b3b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125067385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1125067385
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1501197783
Short name T625
Test name
Test status
Simulation time 405187694465 ps
CPU time 148.05 seconds
Started Jul 07 06:04:57 PM PDT 24
Finished Jul 07 06:07:26 PM PDT 24
Peak memory 201944 kb
Host smart-c90d18c7-c9ef-4040-a81b-1b7514af48d9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501197783 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1501197783
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.3812586746
Short name T643
Test name
Test status
Simulation time 498702262364 ps
CPU time 1136.6 seconds
Started Jul 07 06:04:57 PM PDT 24
Finished Jul 07 06:23:55 PM PDT 24
Peak memory 201928 kb
Host smart-305e0e36-161b-4b3a-a172-30abe9372a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812586746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.3812586746
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.830975722
Short name T382
Test name
Test status
Simulation time 492484135284 ps
CPU time 1111.74 seconds
Started Jul 07 06:04:49 PM PDT 24
Finished Jul 07 06:23:21 PM PDT 24
Peak memory 201872 kb
Host smart-8759112a-074f-4231-81ca-d5a2744b9b89
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=830975722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrup
t_fixed.830975722
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.4245691108
Short name T653
Test name
Test status
Simulation time 331401397640 ps
CPU time 180.01 seconds
Started Jul 07 06:04:46 PM PDT 24
Finished Jul 07 06:07:46 PM PDT 24
Peak memory 201992 kb
Host smart-dd96e431-908a-4e32-b52a-22d3236253ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245691108 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.4245691108
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1762776379
Short name T457
Test name
Test status
Simulation time 490478452967 ps
CPU time 1125.63 seconds
Started Jul 07 06:04:53 PM PDT 24
Finished Jul 07 06:23:40 PM PDT 24
Peak memory 201880 kb
Host smart-db98b1ca-355f-4870-b932-75eec2670ecf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762776379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1762776379
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.441245193
Short name T497
Test name
Test status
Simulation time 599287873645 ps
CPU time 612.51 seconds
Started Jul 07 06:04:53 PM PDT 24
Finished Jul 07 06:15:06 PM PDT 24
Peak memory 201884 kb
Host smart-f7d85588-efa7-41df-9d95-7507965559d6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441245193 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.441245193
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.4257347302
Short name T10
Test name
Test status
Simulation time 73200473835 ps
CPU time 304.51 seconds
Started Jul 07 06:04:52 PM PDT 24
Finished Jul 07 06:09:57 PM PDT 24
Peak memory 202204 kb
Host smart-1ef013c4-3f5d-4620-9857-d8e4a28158cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257347302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.4257347302
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2001710412
Short name T447
Test name
Test status
Simulation time 30394332162 ps
CPU time 37.69 seconds
Started Jul 07 06:04:56 PM PDT 24
Finished Jul 07 06:05:34 PM PDT 24
Peak memory 201644 kb
Host smart-5298555f-42f9-410f-a375-1c78ccc6dd13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001710412 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2001710412
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.1194312050
Short name T464
Test name
Test status
Simulation time 3834643718 ps
CPU time 9.56 seconds
Started Jul 07 06:04:53 PM PDT 24
Finished Jul 07 06:05:03 PM PDT 24
Peak memory 201640 kb
Host smart-4343170c-aeb9-4c84-96f5-24a0aa8e1520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194312050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.1194312050
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2296248240
Short name T580
Test name
Test status
Simulation time 6024355110 ps
CPU time 12.93 seconds
Started Jul 07 06:04:48 PM PDT 24
Finished Jul 07 06:05:02 PM PDT 24
Peak memory 201708 kb
Host smart-06d89b9e-f165-4ac8-a72e-4ff0c36dbc0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296248240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2296248240
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.3802063717
Short name T242
Test name
Test status
Simulation time 262131249900 ps
CPU time 411.76 seconds
Started Jul 07 06:05:01 PM PDT 24
Finished Jul 07 06:11:54 PM PDT 24
Peak memory 202188 kb
Host smart-7495a165-f069-403b-9f2b-c5f433d511b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802063717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.3802063717
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.816309602
Short name T35
Test name
Test status
Simulation time 14693671922 ps
CPU time 33 seconds
Started Jul 07 06:04:55 PM PDT 24
Finished Jul 07 06:05:28 PM PDT 24
Peak memory 210248 kb
Host smart-0c5a4bda-94f9-4151-aecb-17f7dd6bfc56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816309602 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.816309602
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.431050721
Short name T704
Test name
Test status
Simulation time 337204057 ps
CPU time 0.81 seconds
Started Jul 07 06:05:08 PM PDT 24
Finished Jul 07 06:05:10 PM PDT 24
Peak memory 201652 kb
Host smart-86113350-28b1-4be3-a45d-671e3208fca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431050721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.431050721
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.2902661455
Short name T139
Test name
Test status
Simulation time 182782325077 ps
CPU time 106.58 seconds
Started Jul 07 06:05:01 PM PDT 24
Finished Jul 07 06:06:49 PM PDT 24
Peak memory 201924 kb
Host smart-b0e81280-85f0-4349-bfde-b1e154696c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902661455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.2902661455
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4019179002
Short name T675
Test name
Test status
Simulation time 336671398752 ps
CPU time 694.98 seconds
Started Jul 07 06:04:58 PM PDT 24
Finished Jul 07 06:16:33 PM PDT 24
Peak memory 201892 kb
Host smart-9ec3d633-53fb-40d5-b5bb-628d33696be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019179002 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4019179002
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1783025259
Short name T684
Test name
Test status
Simulation time 166797059391 ps
CPU time 359.96 seconds
Started Jul 07 06:05:01 PM PDT 24
Finished Jul 07 06:11:02 PM PDT 24
Peak memory 201856 kb
Host smart-40a7c53b-74f0-459f-9cf5-c26fc1b27135
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783025259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1783025259
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.689523322
Short name T217
Test name
Test status
Simulation time 489643621299 ps
CPU time 95.01 seconds
Started Jul 07 06:05:01 PM PDT 24
Finished Jul 07 06:06:36 PM PDT 24
Peak memory 201976 kb
Host smart-9b925959-b06c-451f-a24d-19c17f26e210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689523322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.689523322
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1870954900
Short name T386
Test name
Test status
Simulation time 165169478113 ps
CPU time 369.4 seconds
Started Jul 07 06:04:58 PM PDT 24
Finished Jul 07 06:11:08 PM PDT 24
Peak memory 201960 kb
Host smart-82617d03-d34c-4ec8-b4a5-c0c1ff54f55a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870954900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1870954900
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.1288129774
Short name T186
Test name
Test status
Simulation time 362195370108 ps
CPU time 202.13 seconds
Started Jul 07 06:05:00 PM PDT 24
Finished Jul 07 06:08:23 PM PDT 24
Peak memory 201968 kb
Host smart-daa11ea0-89f8-4340-98d7-fac919eba369
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288129774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.1288129774
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2943905607
Short name T407
Test name
Test status
Simulation time 570884777801 ps
CPU time 1391.9 seconds
Started Jul 07 06:05:03 PM PDT 24
Finished Jul 07 06:28:16 PM PDT 24
Peak memory 201848 kb
Host smart-851f01b2-f5c9-442b-b884-c6d98dc61f17
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943905607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2943905607
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.1911210577
Short name T658
Test name
Test status
Simulation time 98572508809 ps
CPU time 412.87 seconds
Started Jul 07 06:05:02 PM PDT 24
Finished Jul 07 06:11:55 PM PDT 24
Peak memory 202292 kb
Host smart-774ea005-0c99-44c3-8edc-bb924c567c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911210577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.1911210577
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.156472606
Short name T725
Test name
Test status
Simulation time 42490537392 ps
CPU time 45.63 seconds
Started Jul 07 06:05:02 PM PDT 24
Finished Jul 07 06:05:48 PM PDT 24
Peak memory 201700 kb
Host smart-45399040-1d6f-409c-862e-8fc0d2061119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156472606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.156472606
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.3454081086
Short name T561
Test name
Test status
Simulation time 5596981601 ps
CPU time 1.88 seconds
Started Jul 07 06:05:05 PM PDT 24
Finished Jul 07 06:05:07 PM PDT 24
Peak memory 201672 kb
Host smart-fcc18635-d067-4577-bce2-23ec3e1a3da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454081086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.3454081086
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.4031323465
Short name T737
Test name
Test status
Simulation time 6025710339 ps
CPU time 5.06 seconds
Started Jul 07 06:05:00 PM PDT 24
Finished Jul 07 06:05:05 PM PDT 24
Peak memory 201676 kb
Host smart-10d38cd7-3870-4494-8618-50db0a5b60a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031323465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.4031323465
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.309502053
Short name T231
Test name
Test status
Simulation time 371081900468 ps
CPU time 863.81 seconds
Started Jul 07 06:05:06 PM PDT 24
Finished Jul 07 06:19:30 PM PDT 24
Peak memory 201900 kb
Host smart-d2bca26c-8fc9-4e00-bd41-d48ed7403885
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309502053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.
309502053
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.3149334690
Short name T521
Test name
Test status
Simulation time 42129003468 ps
CPU time 88.34 seconds
Started Jul 07 06:05:01 PM PDT 24
Finished Jul 07 06:06:31 PM PDT 24
Peak memory 202592 kb
Host smart-ad55f294-692e-4add-856e-970037f58d4f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149334690 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.3149334690
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1326696833
Short name T671
Test name
Test status
Simulation time 517395934 ps
CPU time 0.9 seconds
Started Jul 07 06:05:12 PM PDT 24
Finished Jul 07 06:05:13 PM PDT 24
Peak memory 201604 kb
Host smart-27d8103e-0aac-4e91-95e8-342b98fc5707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326696833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1326696833
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.815226429
Short name T304
Test name
Test status
Simulation time 500936547818 ps
CPU time 269.92 seconds
Started Jul 07 06:05:11 PM PDT 24
Finished Jul 07 06:09:41 PM PDT 24
Peak memory 201924 kb
Host smart-c2e904b4-6aff-4f87-8c9b-192961d083af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815226429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.815226429
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.154871954
Short name T313
Test name
Test status
Simulation time 163337969512 ps
CPU time 376.76 seconds
Started Jul 07 06:05:08 PM PDT 24
Finished Jul 07 06:11:25 PM PDT 24
Peak memory 201912 kb
Host smart-c491cfbb-df70-4c34-a808-5f221ee52d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154871954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.154871954
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.4172670168
Short name T358
Test name
Test status
Simulation time 333136692868 ps
CPU time 725.24 seconds
Started Jul 07 06:05:07 PM PDT 24
Finished Jul 07 06:17:13 PM PDT 24
Peak memory 201808 kb
Host smart-4689634e-9db9-405f-9eb5-9098d48a3532
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172670168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.4172670168
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1375344344
Short name T317
Test name
Test status
Simulation time 495395190573 ps
CPU time 261 seconds
Started Jul 07 06:05:08 PM PDT 24
Finished Jul 07 06:09:30 PM PDT 24
Peak memory 201968 kb
Host smart-7229307f-a3c2-4e57-8cf3-421405f3be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375344344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1375344344
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.2610000856
Short name T115
Test name
Test status
Simulation time 170252776711 ps
CPU time 189.09 seconds
Started Jul 07 06:05:06 PM PDT 24
Finished Jul 07 06:08:15 PM PDT 24
Peak memory 201780 kb
Host smart-0169e805-ea55-4272-aa51-fc5509a7386f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610000856 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.2610000856
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.2110219987
Short name T554
Test name
Test status
Simulation time 201668715263 ps
CPU time 229.48 seconds
Started Jul 07 06:05:07 PM PDT 24
Finished Jul 07 06:08:57 PM PDT 24
Peak memory 201816 kb
Host smart-6994c83e-ebe4-4005-b579-bb2e79902315
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110219987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.2110219987
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.2523296252
Short name T511
Test name
Test status
Simulation time 77712023923 ps
CPU time 405.09 seconds
Started Jul 07 06:05:12 PM PDT 24
Finished Jul 07 06:11:58 PM PDT 24
Peak memory 202208 kb
Host smart-f920e351-5a3a-4945-b9e8-c783815b2af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523296252 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.2523296252
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.3803068995
Short name T375
Test name
Test status
Simulation time 42712262945 ps
CPU time 93.23 seconds
Started Jul 07 06:05:11 PM PDT 24
Finished Jul 07 06:06:45 PM PDT 24
Peak memory 201704 kb
Host smart-6b464f68-aee9-4ce2-994c-9a3044f6f4d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803068995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.3803068995
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1693589474
Short name T461
Test name
Test status
Simulation time 3537349161 ps
CPU time 2.75 seconds
Started Jul 07 06:05:13 PM PDT 24
Finished Jul 07 06:05:16 PM PDT 24
Peak memory 201700 kb
Host smart-fe1fee93-0f30-4e33-bf10-f6e83ac0988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693589474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1693589474
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.685516983
Short name T412
Test name
Test status
Simulation time 5847174125 ps
CPU time 13.12 seconds
Started Jul 07 06:05:08 PM PDT 24
Finished Jul 07 06:05:22 PM PDT 24
Peak memory 201696 kb
Host smart-757ee919-af8a-4abe-a2d5-dd80bb0361a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685516983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.685516983
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3610616864
Short name T596
Test name
Test status
Simulation time 526911475 ps
CPU time 1.19 seconds
Started Jul 07 06:05:17 PM PDT 24
Finished Jul 07 06:05:19 PM PDT 24
Peak memory 201684 kb
Host smart-208f5bc5-ceba-4e4c-a186-1206795208d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610616864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3610616864
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2352340313
Short name T222
Test name
Test status
Simulation time 335487239943 ps
CPU time 204.61 seconds
Started Jul 07 06:05:20 PM PDT 24
Finished Jul 07 06:08:45 PM PDT 24
Peak memory 201932 kb
Host smart-124713c0-c124-440f-822a-ad2a1cfd6b35
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352340313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2352340313
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.2174521950
Short name T772
Test name
Test status
Simulation time 330055725331 ps
CPU time 762.19 seconds
Started Jul 07 06:05:19 PM PDT 24
Finished Jul 07 06:18:02 PM PDT 24
Peak memory 201916 kb
Host smart-76d06e6d-dd0a-49b9-b856-ae1e69e49053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174521950 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.2174521950
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.2228733186
Short name T173
Test name
Test status
Simulation time 322924741496 ps
CPU time 209.2 seconds
Started Jul 07 06:05:13 PM PDT 24
Finished Jul 07 06:08:42 PM PDT 24
Peak memory 201896 kb
Host smart-4c0b046f-03b0-42d6-85c8-93fcfc8f9c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228733186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.2228733186
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.274202437
Short name T717
Test name
Test status
Simulation time 168755284978 ps
CPU time 53.29 seconds
Started Jul 07 06:05:15 PM PDT 24
Finished Jul 07 06:06:09 PM PDT 24
Peak memory 201868 kb
Host smart-9fe42278-120b-4143-93dc-2e419fb50fc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=274202437 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrup
t_fixed.274202437
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.3466068859
Short name T182
Test name
Test status
Simulation time 320779378040 ps
CPU time 682.09 seconds
Started Jul 07 06:05:15 PM PDT 24
Finished Jul 07 06:16:37 PM PDT 24
Peak memory 201860 kb
Host smart-a0ff83ba-befa-461c-8a22-8a2e15c01804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466068859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.3466068859
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.4132676583
Short name T745
Test name
Test status
Simulation time 326137624287 ps
CPU time 362.44 seconds
Started Jul 07 06:05:13 PM PDT 24
Finished Jul 07 06:11:16 PM PDT 24
Peak memory 201880 kb
Host smart-c06783f6-1665-463e-8379-5f64c24345be
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132676583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.4132676583
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3195045653
Short name T695
Test name
Test status
Simulation time 196161945300 ps
CPU time 471.48 seconds
Started Jul 07 06:05:15 PM PDT 24
Finished Jul 07 06:13:07 PM PDT 24
Peak memory 201988 kb
Host smart-01060fd5-cee8-423f-8ea9-b28d96767168
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195045653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3195045653
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.1927191020
Short name T400
Test name
Test status
Simulation time 591739622047 ps
CPU time 129.24 seconds
Started Jul 07 06:05:19 PM PDT 24
Finished Jul 07 06:07:29 PM PDT 24
Peak memory 201896 kb
Host smart-e199aa9e-6a3a-4575-8633-665492f1eb33
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927191020 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.1927191020
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2663057261
Short name T428
Test name
Test status
Simulation time 68682896259 ps
CPU time 269.32 seconds
Started Jul 07 06:05:16 PM PDT 24
Finished Jul 07 06:09:45 PM PDT 24
Peak memory 202228 kb
Host smart-0757ab33-9234-4fa0-a5f1-67ff2eed75d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2663057261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2663057261
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1420094493
Short name T422
Test name
Test status
Simulation time 36883755786 ps
CPU time 85.17 seconds
Started Jul 07 06:05:18 PM PDT 24
Finished Jul 07 06:06:44 PM PDT 24
Peak memory 201700 kb
Host smart-49c1d589-19cb-445f-a3e7-ce233d78ce68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420094493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1420094493
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.2950728249
Short name T552
Test name
Test status
Simulation time 5145045628 ps
CPU time 1.71 seconds
Started Jul 07 06:05:16 PM PDT 24
Finished Jul 07 06:05:18 PM PDT 24
Peak memory 201712 kb
Host smart-2b646dc6-6c99-44cd-84a1-9deb0e245d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950728249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.2950728249
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.4250182810
Short name T92
Test name
Test status
Simulation time 5677346128 ps
CPU time 13.56 seconds
Started Jul 07 06:05:12 PM PDT 24
Finished Jul 07 06:05:26 PM PDT 24
Peak memory 201664 kb
Host smart-0b4fb9e8-7137-4c91-8972-ae6aff4c7769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250182810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.4250182810
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.939598984
Short name T657
Test name
Test status
Simulation time 457850470 ps
CPU time 1.64 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:00:44 PM PDT 24
Peak memory 201648 kb
Host smart-e25469f7-8163-4ca2-8056-04910482a8da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939598984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.939598984
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.4231667143
Short name T150
Test name
Test status
Simulation time 351423103006 ps
CPU time 401.18 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:07:18 PM PDT 24
Peak memory 201996 kb
Host smart-4f16d3be-4e38-4f18-ba08-12a99d7b5e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231667143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.4231667143
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.3065634530
Short name T331
Test name
Test status
Simulation time 324609704481 ps
CPU time 189.81 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:03:53 PM PDT 24
Peak memory 201948 kb
Host smart-c1175367-590e-4bd8-a916-fc78ddcbc732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3065634530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.3065634530
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1305900119
Short name T780
Test name
Test status
Simulation time 328834096900 ps
CPU time 770.15 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:13:27 PM PDT 24
Peak memory 201924 kb
Host smart-a6aa7df1-6d7d-41e3-ad02-c8f2e655a49f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305900119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1305900119
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.303599538
Short name T297
Test name
Test status
Simulation time 330632173871 ps
CPU time 156.77 seconds
Started Jul 07 06:00:32 PM PDT 24
Finished Jul 07 06:03:09 PM PDT 24
Peak memory 201904 kb
Host smart-56b6425c-ccd6-4d14-b4d9-5f831a11fd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303599538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.303599538
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3920255400
Short name T570
Test name
Test status
Simulation time 329234671929 ps
CPU time 353.52 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:06:37 PM PDT 24
Peak memory 201884 kb
Host smart-896239cb-6b72-4447-b5c8-92882da58bed
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920255400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3920255400
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.3119773028
Short name T491
Test name
Test status
Simulation time 176791906288 ps
CPU time 101.98 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:02:23 PM PDT 24
Peak memory 201980 kb
Host smart-a32eb108-e212-47ad-9f1c-3447c61bd811
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119773028 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.3119773028
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2256437803
Short name T492
Test name
Test status
Simulation time 600116561409 ps
CPU time 1365.27 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:23:25 PM PDT 24
Peak memory 201788 kb
Host smart-1ef117f1-a5b6-4de3-b686-c470c0917f67
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256437803 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2256437803
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.2138964884
Short name T389
Test name
Test status
Simulation time 31876047062 ps
CPU time 73.47 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:01:53 PM PDT 24
Peak memory 201740 kb
Host smart-2d029a4a-47e3-4389-9133-80f8ad0590d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138964884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.2138964884
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.3954819185
Short name T433
Test name
Test status
Simulation time 5009325154 ps
CPU time 11.39 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:00:48 PM PDT 24
Peak memory 201704 kb
Host smart-377a6e50-798b-4a1a-8674-135e2d2a6a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954819185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.3954819185
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1357803335
Short name T427
Test name
Test status
Simulation time 5640431653 ps
CPU time 13.57 seconds
Started Jul 07 06:00:34 PM PDT 24
Finished Jul 07 06:00:48 PM PDT 24
Peak memory 201692 kb
Host smart-98d9435c-cc06-4ba6-9089-6070b4973fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357803335 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1357803335
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1428229170
Short name T734
Test name
Test status
Simulation time 11069013491 ps
CPU time 6.93 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:00:44 PM PDT 24
Peak memory 201700 kb
Host smart-f977a9df-441b-48e4-84ab-346ee9979568
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428229170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1428229170
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.3974453688
Short name T281
Test name
Test status
Simulation time 155288063565 ps
CPU time 302.42 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:05:41 PM PDT 24
Peak memory 210216 kb
Host smart-67e593e8-ee15-4d05-ba65-e4e98ecdad0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974453688 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.3974453688
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.2646480852
Short name T585
Test name
Test status
Simulation time 490021573 ps
CPU time 1.22 seconds
Started Jul 07 06:00:35 PM PDT 24
Finished Jul 07 06:00:37 PM PDT 24
Peak memory 201656 kb
Host smart-076bcb63-6fdd-4e7a-8792-e8c36866ba21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646480852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.2646480852
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3937507347
Short name T5
Test name
Test status
Simulation time 160729564413 ps
CPU time 29.15 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:01:06 PM PDT 24
Peak memory 201900 kb
Host smart-0ef97c7a-b8f8-48a6-a77c-289c3a17c064
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3937507347 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3937507347
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1256349668
Short name T197
Test name
Test status
Simulation time 159322932668 ps
CPU time 81.77 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:02:01 PM PDT 24
Peak memory 201452 kb
Host smart-830dea0a-9541-493e-be84-e12e176c15e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256349668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1256349668
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.196551568
Short name T770
Test name
Test status
Simulation time 157024570338 ps
CPU time 94.93 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:02:19 PM PDT 24
Peak memory 201880 kb
Host smart-e76069fa-2191-4501-8dc2-7dedd7d077ee
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=196551568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt
_fixed.196551568
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1965455448
Short name T494
Test name
Test status
Simulation time 164256100811 ps
CPU time 341.76 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:06:24 PM PDT 24
Peak memory 201956 kb
Host smart-a794fc93-ba0e-4319-9339-dfa9c3d92613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965455448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1965455448
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.3892780265
Short name T2
Test name
Test status
Simulation time 489279434657 ps
CPU time 271.57 seconds
Started Jul 07 06:00:39 PM PDT 24
Finished Jul 07 06:05:11 PM PDT 24
Peak memory 201792 kb
Host smart-313da098-711d-4a2d-a9e7-819057274fe5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892780265 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.3892780265
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.3767710888
Short name T315
Test name
Test status
Simulation time 360547319391 ps
CPU time 164.22 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:03:20 PM PDT 24
Peak memory 201920 kb
Host smart-8d3f5700-47ec-4ded-bde8-e45a8575f84d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767710888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.3767710888
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3105795345
Short name T270
Test name
Test status
Simulation time 400470890956 ps
CPU time 459.02 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:08:20 PM PDT 24
Peak memory 201812 kb
Host smart-6f807c51-d047-4f54-95b1-c92aa5c58d48
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105795345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3105795345
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.2529185552
Short name T477
Test name
Test status
Simulation time 73654457920 ps
CPU time 390.46 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:07:14 PM PDT 24
Peak memory 202212 kb
Host smart-242eb4dc-8290-4590-b5ce-d2ef6f8e7ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529185552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.2529185552
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.1552186559
Short name T626
Test name
Test status
Simulation time 41525807171 ps
CPU time 23.38 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:01:02 PM PDT 24
Peak memory 201372 kb
Host smart-f1dccacf-7a17-4aa6-93ef-c2be745b9f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552186559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.1552186559
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3573706691
Short name T405
Test name
Test status
Simulation time 4494323447 ps
CPU time 3.45 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:00:41 PM PDT 24
Peak memory 201696 kb
Host smart-9ab98df2-c741-4181-b55e-30d77e2c3b7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573706691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3573706691
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.2244342622
Short name T102
Test name
Test status
Simulation time 5593491554 ps
CPU time 14.49 seconds
Started Jul 07 06:00:37 PM PDT 24
Finished Jul 07 06:00:53 PM PDT 24
Peak memory 201596 kb
Host smart-6f1a0104-c4e0-4a73-ae49-b0f9e96edac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244342622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.2244342622
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2283241314
Short name T25
Test name
Test status
Simulation time 130556358412 ps
CPU time 359.22 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:06:42 PM PDT 24
Peak memory 210460 kb
Host smart-775cb287-81c5-465d-956b-35e3405f8e02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283241314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2283241314
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.1882558529
Short name T330
Test name
Test status
Simulation time 70661316065 ps
CPU time 126.15 seconds
Started Jul 07 06:00:38 PM PDT 24
Finished Jul 07 06:02:45 PM PDT 24
Peak memory 211044 kb
Host smart-a9a0a274-eef0-4d16-b5ca-a475c7ca1ddc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882558529 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.1882558529
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.299842912
Short name T60
Test name
Test status
Simulation time 475697084 ps
CPU time 1.61 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:00:42 PM PDT 24
Peak memory 201616 kb
Host smart-54c718b4-a1f3-4c5a-8efc-d36600396012
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299842912 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.299842912
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1978773794
Short name T72
Test name
Test status
Simulation time 169095820394 ps
CPU time 196.23 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:04:00 PM PDT 24
Peak memory 202180 kb
Host smart-758d9304-4319-4efa-8365-90bc56f8dc3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978773794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1978773794
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.3502525201
Short name T296
Test name
Test status
Simulation time 328093376084 ps
CPU time 352.74 seconds
Started Jul 07 06:00:47 PM PDT 24
Finished Jul 07 06:06:40 PM PDT 24
Peak memory 201896 kb
Host smart-6e445e8d-b4b3-4a9a-a286-a6196ce3ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502525201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.3502525201
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.339673551
Short name T776
Test name
Test status
Simulation time 158147583507 ps
CPU time 368.08 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:06:53 PM PDT 24
Peak memory 201936 kb
Host smart-8bf9f678-8cb0-4d45-b90a-ebfde78f5ca1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=339673551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt
_fixed.339673551
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.2954855425
Short name T651
Test name
Test status
Simulation time 161898883318 ps
CPU time 104.11 seconds
Started Jul 07 06:00:39 PM PDT 24
Finished Jul 07 06:02:24 PM PDT 24
Peak memory 201872 kb
Host smart-a31a4314-f39d-47d2-9549-dab6c93df553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954855425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.2954855425
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.134943608
Short name T421
Test name
Test status
Simulation time 162733448825 ps
CPU time 350.54 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:06:36 PM PDT 24
Peak memory 201868 kb
Host smart-72dce0fb-5da1-4cb0-be20-9c15d757f58e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=134943608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed
.134943608
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.3467612733
Short name T91
Test name
Test status
Simulation time 395827577348 ps
CPU time 222.77 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:04:25 PM PDT 24
Peak memory 201980 kb
Host smart-1dbc6efe-4508-4730-b129-c53d98e11a52
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467612733 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.3467612733
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.4697316
Short name T604
Test name
Test status
Simulation time 592478010600 ps
CPU time 371.33 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:06:54 PM PDT 24
Peak memory 201940 kb
Host smart-2c819acd-5cba-496a-8b5c-37f62cdc634c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4697316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc
_ctrl_filters_wakeup_fixed.4697316
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.3689846946
Short name T338
Test name
Test status
Simulation time 87670630460 ps
CPU time 393.25 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:07:14 PM PDT 24
Peak memory 202276 kb
Host smart-deef5303-8727-4337-8b87-70105cc6c3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689846946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.3689846946
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.1643626852
Short name T719
Test name
Test status
Simulation time 42043128022 ps
CPU time 26.7 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:01:08 PM PDT 24
Peak memory 201976 kb
Host smart-981f3ab6-c5da-41f8-a7ce-34d3083933ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643626852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.1643626852
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1259971512
Short name T748
Test name
Test status
Simulation time 4444104773 ps
CPU time 3.24 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:00:48 PM PDT 24
Peak memory 201724 kb
Host smart-a3d5036b-8e4e-4d45-90c3-3f9816f8599f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259971512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1259971512
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.475655960
Short name T550
Test name
Test status
Simulation time 6129481768 ps
CPU time 4.51 seconds
Started Jul 07 06:00:36 PM PDT 24
Finished Jul 07 06:00:41 PM PDT 24
Peak memory 201692 kb
Host smart-66209796-86b4-4ce6-bed9-11de8008262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475655960 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.475655960
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3118034277
Short name T738
Test name
Test status
Simulation time 162771979260 ps
CPU time 198.43 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:04:01 PM PDT 24
Peak memory 201968 kb
Host smart-b65a3276-1051-4c6e-b91f-c7b6da52e829
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118034277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3118034277
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2922288387
Short name T527
Test name
Test status
Simulation time 177087400099 ps
CPU time 304.74 seconds
Started Jul 07 06:00:46 PM PDT 24
Finished Jul 07 06:05:51 PM PDT 24
Peak memory 210608 kb
Host smart-4ff1f410-5f6e-4851-b62d-65bbcff12721
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922288387 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2922288387
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.791221632
Short name T694
Test name
Test status
Simulation time 367438338 ps
CPU time 1.45 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:00:56 PM PDT 24
Peak memory 201600 kb
Host smart-fd867db8-5321-4c08-a8dd-3e6f1c53ae2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791221632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.791221632
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.2714556983
Short name T289
Test name
Test status
Simulation time 500075166548 ps
CPU time 1120.18 seconds
Started Jul 07 06:00:55 PM PDT 24
Finished Jul 07 06:19:35 PM PDT 24
Peak memory 201872 kb
Host smart-427ff7e8-7735-40b2-b1a7-e3cd55af9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714556983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.2714556983
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.2813232617
Short name T162
Test name
Test status
Simulation time 499702808522 ps
CPU time 286.48 seconds
Started Jul 07 06:00:55 PM PDT 24
Finished Jul 07 06:05:42 PM PDT 24
Peak memory 201904 kb
Host smart-7daa4ed0-10d5-4eac-bd8a-40f98bb29c4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813232617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.2813232617
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.3412248970
Short name T348
Test name
Test status
Simulation time 161130243814 ps
CPU time 185.25 seconds
Started Jul 07 06:00:46 PM PDT 24
Finished Jul 07 06:03:51 PM PDT 24
Peak memory 201916 kb
Host smart-c709fdd6-c56c-4d82-a011-47db61b0aeb1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412248970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.3412248970
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.280403096
Short name T185
Test name
Test status
Simulation time 495419110101 ps
CPU time 289.2 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:05:37 PM PDT 24
Peak memory 201676 kb
Host smart-e43e3dc4-b63a-4b34-856c-02aea8a305e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280403096 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.280403096
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3886968653
Short name T76
Test name
Test status
Simulation time 165322137726 ps
CPU time 166.97 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:03:29 PM PDT 24
Peak memory 201988 kb
Host smart-02a715f3-80c5-4d8f-b775-28c91b4f9921
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886968653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3886968653
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2232723807
Short name T233
Test name
Test status
Simulation time 599768444759 ps
CPU time 1282.58 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:22:04 PM PDT 24
Peak memory 201840 kb
Host smart-1d65fc75-7415-4437-bf79-5a9acd42bb3c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232723807 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2232723807
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.2166011848
Short name T616
Test name
Test status
Simulation time 194658129171 ps
CPU time 221.68 seconds
Started Jul 07 06:01:01 PM PDT 24
Finished Jul 07 06:04:43 PM PDT 24
Peak memory 201832 kb
Host smart-7452afb7-9236-4d42-880f-c93a7fc6c853
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166011848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.2166011848
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.719236365
Short name T201
Test name
Test status
Simulation time 76329999648 ps
CPU time 239.57 seconds
Started Jul 07 06:00:48 PM PDT 24
Finished Jul 07 06:04:48 PM PDT 24
Peak memory 201996 kb
Host smart-41d58fcc-c85e-4980-925e-68b58ff26ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719236365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.719236365
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3870042757
Short name T726
Test name
Test status
Simulation time 37266910663 ps
CPU time 80.34 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:02:05 PM PDT 24
Peak memory 201720 kb
Host smart-39dd353a-e9b6-4e9e-a37b-38545b78e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870042757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3870042757
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.2888847145
Short name T485
Test name
Test status
Simulation time 5173307034 ps
CPU time 4.19 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:00:49 PM PDT 24
Peak memory 201712 kb
Host smart-6e4f03d3-e407-4081-a6a0-c08d31f982f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888847145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.2888847145
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.2516017721
Short name T708
Test name
Test status
Simulation time 5615142823 ps
CPU time 7.15 seconds
Started Jul 07 06:00:41 PM PDT 24
Finished Jul 07 06:00:49 PM PDT 24
Peak memory 201748 kb
Host smart-524b9748-1b2c-4901-af8e-4ae2ec29d59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516017721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.2516017721
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1685130716
Short name T26
Test name
Test status
Simulation time 185408145140 ps
CPU time 106.04 seconds
Started Jul 07 06:00:55 PM PDT 24
Finished Jul 07 06:02:41 PM PDT 24
Peak memory 201844 kb
Host smart-36a861c9-b3d8-4285-b423-30e461d701fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685130716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1685130716
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.2589437342
Short name T77
Test name
Test status
Simulation time 112596738481 ps
CPU time 89.49 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:02:14 PM PDT 24
Peak memory 210552 kb
Host smart-fe90cab8-241f-4800-a9a6-da6e909c8580
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589437342 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.2589437342
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.3805551240
Short name T379
Test name
Test status
Simulation time 491864684 ps
CPU time 1.64 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:00:47 PM PDT 24
Peak memory 201636 kb
Host smart-748fc033-a8c4-477d-aec2-98d961478e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805551240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.3805551240
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.2595134237
Short name T687
Test name
Test status
Simulation time 165288480444 ps
CPU time 233.52 seconds
Started Jul 07 06:00:40 PM PDT 24
Finished Jul 07 06:04:34 PM PDT 24
Peak memory 201896 kb
Host smart-9d8d8493-bcea-44ce-8cbb-62d49c5d632f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595134237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.2595134237
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1725226946
Short name T746
Test name
Test status
Simulation time 330749620363 ps
CPU time 789.33 seconds
Started Jul 07 06:00:54 PM PDT 24
Finished Jul 07 06:14:04 PM PDT 24
Peak memory 201820 kb
Host smart-b66e624c-befb-42b9-95d3-9b373fb06805
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725226946 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1725226946
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3275053148
Short name T620
Test name
Test status
Simulation time 160355187047 ps
CPU time 79.45 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:02:03 PM PDT 24
Peak memory 201968 kb
Host smart-cfc3b42e-661b-4325-bcc3-85d6713dee2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275053148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3275053148
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.1538791216
Short name T763
Test name
Test status
Simulation time 320995222570 ps
CPU time 316.43 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:06:02 PM PDT 24
Peak memory 201872 kb
Host smart-3f69bcab-864c-478e-9e4a-3d50c93f8d8d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538791216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.1538791216
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1569794253
Short name T722
Test name
Test status
Simulation time 576224257025 ps
CPU time 1295.79 seconds
Started Jul 07 06:00:45 PM PDT 24
Finished Jul 07 06:22:21 PM PDT 24
Peak memory 201856 kb
Host smart-9f4b06e0-ae23-408a-8dcf-93ab2a907441
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569794253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1569794253
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.586884372
Short name T339
Test name
Test status
Simulation time 108245388372 ps
CPU time 538.41 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:09:43 PM PDT 24
Peak memory 202228 kb
Host smart-1ce10e6d-8d65-4953-a103-58aaa5ec55a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586884372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.586884372
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.3601369188
Short name T165
Test name
Test status
Simulation time 25184498072 ps
CPU time 28.91 seconds
Started Jul 07 06:00:42 PM PDT 24
Finished Jul 07 06:01:12 PM PDT 24
Peak memory 201700 kb
Host smart-a24bb165-3878-44b4-8d32-905d25e47221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601369188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.3601369188
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.3098449388
Short name T692
Test name
Test status
Simulation time 3153141206 ps
CPU time 7.99 seconds
Started Jul 07 06:00:43 PM PDT 24
Finished Jul 07 06:00:52 PM PDT 24
Peak memory 201708 kb
Host smart-edaaa109-09af-4719-8523-8faab9f725ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098449388 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.3098449388
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.914237410
Short name T378
Test name
Test status
Simulation time 5581475114 ps
CPU time 13.48 seconds
Started Jul 07 06:00:44 PM PDT 24
Finished Jul 07 06:00:58 PM PDT 24
Peak memory 201676 kb
Host smart-133047a2-7951-46aa-8a88-c6124afd219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914237410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.914237410
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1636691756
Short name T560
Test name
Test status
Simulation time 185367050821 ps
CPU time 433.31 seconds
Started Jul 07 06:00:49 PM PDT 24
Finished Jul 07 06:08:03 PM PDT 24
Peak memory 201900 kb
Host smart-fa7041c0-2c22-4197-a4dc-254cd45250b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636691756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1636691756
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2724991823
Short name T15
Test name
Test status
Simulation time 27501485265 ps
CPU time 85.82 seconds
Started Jul 07 06:00:46 PM PDT 24
Finished Jul 07 06:02:12 PM PDT 24
Peak memory 210520 kb
Host smart-d0d283f0-6c21-489a-ae83-a02bfe45472d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724991823 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2724991823
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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