Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	7288	1			T1	40		T2	7		T3	20
testmodes[AdcCtrlTestmodeNormal]	5782	1			T1	52		T2	6		T3	2
testmodes[AdcCtrlTestmodeLowpower]	5828	1			T1	64		T3	19		T5	17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3979	1			T1	12		T2	3		T3	19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1863	1			T1	13		T2	3		T9	14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1325	1			T1	14		T9	18		T11	13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1879	1			T1	20		T2	3		T3	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2143	1			T1	16		T2	3		T3	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1436	1			T1	16		T7	1		T9	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1319	1			T1	8		T9	18		T11	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1439	1			T1	23		T3	1		T9	18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2816	1			T1	33		T3	18		T5	16