Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv



Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
testmode_cp 12 0 12 100.00 100 1 1 0


Summary for Variable testmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for testmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
testmodes[AdcCtrlTestmodeOneShot] 7288 1 T1 40 T2 7 T3 20
testmodes[AdcCtrlTestmodeNormal] 5782 1 T1 52 T2 6 T3 2
testmodes[AdcCtrlTestmodeLowpower] 5828 1 T1 64 T3 19 T5 17
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot] 3979 1 T1 12 T2 3 T3 19
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal] 1863 1 T1 13 T2 3 T9 14
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower] 1325 1 T1 14 T9 18 T11 13
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot] 1879 1 T1 20 T2 3 T3 1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal] 2143 1 T1 16 T2 3 T3 1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower] 1436 1 T1 16 T7 1 T9 18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot] 1319 1 T1 8 T9 18 T11 18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal] 1439 1 T1 23 T3 1 T9 18
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower] 2816 1 T1 33 T3 18 T5 16

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%