Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23714

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3153

1

T3

14

T6

13

T11

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21142

1

T1

156

T2

13

T3

53

auto[1]

5725

1

T3

10

T7

29

T8

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	78	1			T21	1		T147	15		T210	3
values[1]	654	1			T3	10		T136	26		T137	1
values[2]	584	1			T10	21		T53	25		T149	3
values[3]	803	1			T10	19		T51	1		T144	15
values[4]	647	1			T7	18		T47	1		T53	8
values[5]	777	1			T7	29		T14	5		T53	9
values[6]	582	1			T13	21		T139	25		T140	1
values[7]	722	1			T11	25		T149	3		T137	1
values[8]	843	1			T3	14		T7	15		T14	6
values[9]	3223	1			T6	13		T8	31		T11	17
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	813	1			T3	10		T136	26		T137	1
values[1]	696	1			T10	21		T53	25		T149	3
values[2]	689	1			T10	19		T51	1		T144	15
values[3]	598	1			T47	1		T53	8		T149	12
values[4]	900	1			T7	47		T14	5		T53	9
values[5]	597	1			T13	21		T139	25		T140	1
values[6]	2990	1			T7	15		T8	31		T11	25
values[7]	703	1			T3	14		T11	17		T14	6
values[8]	687	1			T12	14		T13	15		T52	46
values[9]	229	1			T6	13		T139	16		T141	12
minimum	17965	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	1		T136	12		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T85	2		T40	8		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T10	12		T53	17		T16	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T149	1		T83	12		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	14		T86	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T51	1		T144	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T47	1		T149	1		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T53	6		T81	1		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	27		T14	5		T53	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T83	5		T27	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	12		T141	6		T20	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	9		T139	14		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1608	1			T7	6		T8	31		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	13		T137	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	11		T47	26		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T3	12		T14	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	15		T52	4		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T12	1		T52	25		T139	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T110	13		T211	10		T212	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T6	11		T139	8		T141	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17818	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	9		T136	14		T144	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T85	16		T40	8		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	9		T53	8		T16	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T149	2		T83	11		T32	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	5		T86	11		T17	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T144	14		T21	10		T213	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	11		T214	13		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T53	2		T83	1		T215	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	20		T53	4		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T83	11		T216	2		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T141	2		T20	1		T217	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T139	11		T32	1		T218	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T7	9		T54	19		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	12		T144	5		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T11	6		T47	16		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	2		T14	5		T151	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T52	2		T151	10		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	13		T52	15		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T211	16		T212	12		T219	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T6	2		T139	8		T141	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T47	3		T16	1		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T21	1		T147	1		T203	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T210	1		T220	1		T221	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	1		T136	12		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T85	2		T40	8		T152	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	12		T53	17		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T149	1		T138	1		T32	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T10	14		T86	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T51	1		T144	1		T83	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	10		T47	1		T136	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	6		T81	1		T83	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T7	17		T14	5		T53	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T216	1		T217	5		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	12		T20	4		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	9		T139	14		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T149	1		T81	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T11	13		T137	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T7	6		T47	26		T150	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	12		T14	1		T143	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1615	1			T8	31		T11	11		T13	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T6	11		T12	1		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T147	14		T223	17		T224	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T210	2		T221	2		T225	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	9		T136	14		T144	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T85	16		T40	8		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T10	9		T53	8		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T149	2		T32	6		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	5		T86	11		T153	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T144	14		T83	11		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	8		T136	8		T17	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T53	2		T83	1		T215	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	12		T53	4		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T216	2		T217	10		T226	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T20	1		T102	2		T205	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T139	11		T83	11		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T149	2		T222	6		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	12		T144	5		T164	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	9		T47	16		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	2		T14	5		T86	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T11	6		T52	2		T54	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T6	2		T12	13		T52	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T3	10		T136	15		T137	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T85	18		T40	9		T152	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T10	10		T53	9		T16	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T149	3		T83	12		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T10	6		T86	12		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T51	1		T144	15		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T47	1		T149	12		T37	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T53	3		T81	1		T83	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	22		T14	1		T53	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T83	12		T27	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T141	3		T20	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T13	1		T139	12		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1344	1			T7	10		T8	3		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	13		T137	1		T144	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	7		T47	21		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T3	3		T14	6		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	1		T52	3		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T12	14		T52	17		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T110	1		T211	20		T212	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T6	3		T139	9		T141	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17965	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T136	11		T184	4		T33	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	7		T152	2		T227	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	11		T53	16		T16	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T83	11		T148	13		T199	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T10	13		T17	12		T56	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T228	9		T21	11		T110	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T229	13		T148	9		T88	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T53	5		T215	9		T230	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T7	25		T14	4		T53	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T83	4		T231	18		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	11		T141	5		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	8		T139	13		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T7	5		T8	28		T232	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T11	12		T164	6		T165	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	10		T47	21		T18	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	11		T143	13		T192	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T13	14		T52	3		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T52	23		T139	11		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T110	12		T211	6		T212	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T6	10		T139	7		T141	8

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T21	1		T147	15		T203	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T210	3		T220	1		T221	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	10		T136	15		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T85	18		T40	9		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T10	10		T53	9		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T149	3		T138	1		T32	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T10	6		T86	12		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T51	1		T144	15		T83	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	9		T47	1		T136	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T53	3		T81	1		T83	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T7	13		T14	1		T53	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T216	3		T217	11		T103	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T13	1		T20	4		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T139	12		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T149	3		T81	1		T222	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	13		T137	1		T144	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	10		T47	21		T150	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	3		T14	6		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T8	3		T11	7		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	381	1			T6	3		T12	14		T51	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T223	11		T224	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T136	11		T184	4		T33	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T40	7		T152	2		T233	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	11		T53	16		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T227	10		T148	7		T93	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T10	13		T56	2		T153	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T83	11		T228	9		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T7	9		T136	6		T17	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T53	5		T215	9		T21	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	16		T14	4		T53	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T217	4		T226	11		T234	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	11		T20	1		T102	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T13	8		T139	13		T83	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T18	3		T217	4		T169	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T11	12		T191	2		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	5		T47	21		T150	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	11		T143	13		T165	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1258	1			T8	28		T11	10		T13	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T6	10		T52	23		T139	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23452

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3415

1

T3

14

T7

33

T10

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21021

1

T1

156

T2

13

T3

39

auto[1]

5846

1

T3

24

T6

13

T8

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	21	1			T235	9		T171	2		T181	10
values[1]	625	1			T7	33		T10	19		T11	17
values[2]	770	1			T10	21		T13	15		T136	15
values[3]	701	1			T3	24		T53	25		T139	14
values[4]	617	1			T13	12		T47	42		T51	1
values[5]	508	1			T11	25		T13	9		T83	23
values[6]	763	1			T149	15		T139	25		T140	1
values[7]	817	1			T14	5		T136	26		T83	2
values[8]	2870	1			T8	31		T47	1		T49	2
values[9]	1221	1			T6	13		T7	29		T52	6
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	794	1			T7	33		T10	19		T11	17
values[1]	761	1			T3	10		T10	21		T139	14
values[2]	688	1			T3	14		T13	27		T51	1
values[3]	585	1			T47	42		T81	1		T86	12
values[4]	517	1			T11	25		T13	9		T83	23
values[5]	861	1			T149	15		T139	25		T140	1
values[6]	2980	1			T8	31		T14	5		T49	2
values[7]	692	1			T52	11		T137	1		T141	12
values[8]	858	1			T6	13		T7	29		T47	1
values[9]	141	1			T144	7		T228	10		T45	1
minimum	17990	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	14		T11	11		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	16		T12	1		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T3	1		T139	12		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	12		T141	6		T17	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	12		T53	17		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	12		T13	15		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T81	1		T86	1		T17	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T47	26		T163	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T11	13		T83	12		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	9		T36	1		T191	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T149	1		T139	14		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T149	1		T151	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1575	1			T8	31		T14	5		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T83	1		T86	1		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T17	1		T36	4		T227	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T52	8		T137	1		T141	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	11		T7	17		T52	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T47	1		T149	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T144	1		T228	10		T213	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T45	1		T229	18		T162	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17842	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T236	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	5		T11	6		T53	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	17		T12	13		T14	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T3	9		T139	2		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	9		T141	2		T17	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T53	8		T40	8		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	2		T32	6		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T86	11		T17	15		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T47	16		T147	18		T237	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	12		T83	11		T213	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T148	5		T88	1		T205	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T149	2		T139	11		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T149	11		T151	10		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	933	1			T52	12		T54	19		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T83	1		T86	6		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T36	18		T227	9		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T52	3		T141	3		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T6	2		T7	12		T52	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T149	2		T144	5		T214	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T144	6		T213	8		T88	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T171	14		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T47	3		T16	1		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T236	6		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	8	40	83.33	8

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T235	9		T171	1		T181	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	14		T11	11		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T7	16		T12	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T26	1		T37	1		T191	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T10	12		T13	15		T136	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T53	17		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	12		T141	6		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	12		T137	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T47	26		T51	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T11	13		T83	12		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	9		T163	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T149	1		T139	14		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	1		T151	1		T191	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	5		T136	12		T33	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T83	1		T27	1		T153	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T8	31		T49	2		T52	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	1		T52	8		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T6	11		T7	17		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T149	1		T144	1		T143	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T171	1		T181	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T10	5		T11	6		T53	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T7	17		T12	13		T14	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T26	1		T152	13		T216	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	9		T136	8		T17	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	9		T53	8		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T3	2		T141	2		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T86	11		T40	8		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	16		T217	10		T164	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T11	12		T83	11		T213	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T88	1		T205	3		T239	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T149	2		T139	11		T18	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T149	11		T151	10		T45	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T136	14		T20	1		T162	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T83	1		T153	21		T211	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	942	1			T52	12		T54	19		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T52	3		T141	3		T86	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	303	1			T6	2		T7	12		T52	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T149	2		T144	5		T214	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4