Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23273

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3594

1

T3

14

T6

13

T10

40

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20978

1

T1

156

T2

13

T3

53

auto[1]

5889

1

T3

10

T6

13

T7

29

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	22	1			T305	14		T306	8		-	-
values[0]	69	1			T142	1		T36	1		T229	16
values[1]	701	1			T7	29		T11	25		T51	1
values[2]	731	1			T6	13		T13	12		T136	41
values[3]	650	1			T10	19		T149	12		T150	9
values[4]	581	1			T3	10		T7	33		T10	21
values[5]	2665	1			T8	31		T49	2		T54	21
values[6]	742	1			T13	15		T47	42		T53	8
values[7]	776	1			T3	14		T12	14		T52	6
values[8]	566	1			T52	11		T149	3		T137	1
values[9]	1410	1			T11	17		T13	9		T14	11
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	946	1			T7	29		T11	25		T13	12
values[1]	656	1			T6	13		T10	19		T136	26
values[2]	746	1			T7	33		T10	21		T149	12
values[3]	2608	1			T3	10		T8	31		T47	1
values[4]	479	1			T47	42		T139	16		T86	7
values[5]	786	1			T3	14		T13	15		T52	6
values[6]	757	1			T12	14		T137	1		T144	7
values[7]	656	1			T52	40		T149	3		T83	18
values[8]	1021	1			T13	9		T14	11		T53	25
values[9]	214	1			T11	17		T85	17		T86	12
minimum	17998	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T7	17		T11	13		T13	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T51	1		T136	7		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T17	1		T191	3		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T6	11		T10	14		T136	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T7	16		T149	1		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T10	12		T150	9		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1451	1			T3	1		T8	31		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T47	1		T149	1		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	26		T307	1		T217	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T139	8		T86	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T52	4		T53	6		T139	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	12		T13	15		T53	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T81	1		T83	12		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T12	1		T137	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T52	25		T149	1		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T83	5		T138	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	9		T14	5		T141	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T14	1		T53	17		T139	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T11	11		T86	1		T103	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T85	1		T151	1		T214	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17829	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T152	1		T164	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T7	12		T11	12		T40	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T136	8		T18	2		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T17	3		T152	13		T148	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	2		T10	5		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	17		T149	11		T86	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	9		T17	12		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	889	1			T3	9		T54	19		T79	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	2		T144	14		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T47	16		T217	10		T218	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T139	8		T86	6		T237	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T52	2		T53	2		T139	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	2		T53	4		T46	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T83	11		T222	6		T227	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T12	13		T144	6		T46	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T52	15		T149	2		T83	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T83	11		T20	1		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T141	5		T26	1		T36	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	5		T53	8		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T11	6		T86	11		T268	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T85	16		T151	10		T214	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T47	3		T16	1		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T164	10		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T306	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T305	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T142	1		T188	1		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T36	1		T229	16		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	17		T11	13		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T51	1		T140	1		T143	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	12		T86	1		T17	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T6	11		T136	19		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T149	1		T41	1		T191	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T10	14		T150	9		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T3	1		T7	16		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T10	12		T47	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1437	1			T8	31		T49	2		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T138	1		T44	1		T191	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T47	26		T53	6		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T13	15		T143	14		T86	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T52	4		T81	1		T83	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T3	12		T12	1		T53	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T52	8		T149	1		T141	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T137	1		T144	1		T83	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	375	1			T11	11		T13	9		T14	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	375	1			T14	1		T53	17		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T306	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T166	2		T308	14		T309	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T310	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	12		T11	12		T214	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T18	2		T48	1		T56	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T86	11		T17	3		T40	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T6	2		T136	22		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T149	11		T22	7		T171	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	5		T45	12		T153	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	9		T7	17		T85	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	9		T149	2		T139	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	870	1			T54	19		T79	4		T80	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T215	8		T169	10		T238	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T47	16		T53	2		T139	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T86	6		T46	17		T213	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T52	2		T83	11		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T3	2		T12	13		T53	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T52	3		T149	2		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T144	6		T83	11		T199	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T11	6		T52	12		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	347	1			T14	5		T53	8		T139	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	13		T11	13		T13	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T51	1		T136	9		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T17	4		T191	1		T152	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	3		T10	6		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	19		T149	12		T86	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T10	10		T150	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T3	10		T8	3		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	1		T149	3		T144	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	21		T307	1		T217	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T139	9		T86	7		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T52	3		T53	3		T139	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	3		T13	1		T53	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T81	1		T83	12		T222	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T12	14		T137	1		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T52	17		T149	3		T83	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T83	12		T138	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T13	1		T14	1		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T14	6		T53	9		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	7		T86	12		T103	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T85	17		T151	11		T214	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17970	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T152	1		T164	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T7	16		T11	12		T13	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T136	6		T143	2		T18	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T191	2		T152	2		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	10		T10	13		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	14		T191	8		T93	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	11		T150	8		T17	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1130	1			T8	28		T232	19		T158	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T48	3		T215	2		T169	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T47	21		T217	4		T280	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T139	7		T191	7		T266	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T52	3		T53	5		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	11		T13	14		T53	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T83	11		T227	10		T56	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T110	12		T235	8		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T52	23		T32	4		T192	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T83	4		T33	15		T229	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	8		T14	4		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T53	16		T139	11		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T11	10		T268	12		T265	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T305	13		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T293	8		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T164	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T306	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T305	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T142	1		T188	1		T166	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T36	1		T229	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	13		T11	13		T37	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T51	1		T140	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	1		T86	12		T17	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	3		T136	24		T151	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T149	12		T41	1		T191	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T10	6		T150	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	10		T7	19		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	10		T47	1		T149	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1192	1			T8	3		T49	2		T54	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T138	1		T44	1		T191	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T47	21		T53	3		T139	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	1		T143	1		T86	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T52	3		T81	1		T83	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T3	3		T12	14		T53	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T52	4		T149	3		T141	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T137	1		T144	7		T83	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	401	1			T11	7		T13	1		T14	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	424	1			T14	6		T53	9		T139	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T306	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T305	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T309	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T229	15		T310	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	16		T11	12		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T143	2		T18	3		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	11		T40	7		T191	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	10		T136	17		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T191	2		T22	8		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T10	13		T150	8		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	14		T17	16		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T10	11		T139	7		T17	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T8	28		T232	19		T158	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T191	7		T215	2		T169	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	21		T53	5		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	14		T143	13		T46	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T52	3		T83	11		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	11		T53	4		T229	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T52	7		T141	5		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T83	4		T33	15		T110	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T11	10		T13	8		T14	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T53	16		T139	11		T16	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30