Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23756

1

T1

156

T2

13

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

3111

1

T3

10

T6

13

T7

33

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21069

1

T1

156

T2

13

T3

63

auto[1]

5798

1

T7

47

T8

31

T13

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T213	10		T279	5		T303	16
values[0]	79	1			T3	14		T22	18		T295	21
values[1]	862	1			T7	18		T11	25		T14	5
values[2]	632	1			T3	10		T7	15		T12	14
values[3]	614	1			T11	17		T53	9		T137	1
values[4]	2828	1			T6	13		T7	29		T8	31
values[5]	681	1			T10	40		T137	1		T85	13
values[6]	720	1			T137	1		T81	1		T41	1
values[7]	583	1			T13	12		T53	33		T149	12
values[8]	653	1			T13	9		T139	25		T141	12
values[9]	1217	1			T14	6		T47	43		T51	1
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1073	1			T3	14		T7	33		T11	25
values[1]	607	1			T3	10		T12	14		T13	15
values[2]	659	1			T6	13		T11	17		T149	3
values[3]	2798	1			T7	29		T8	31		T49	2
values[4]	693	1			T10	40		T137	2		T36	1
values[5]	670	1			T53	25		T139	16		T144	15
values[6]	752	1			T13	12		T53	8		T149	12
values[7]	582	1			T13	9		T47	42		T139	25
values[8]	774	1			T14	6		T47	1		T51	1
values[9]	247	1			T41	1		T46	31		T21	2
minimum	18012	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T3	12		T14	5		T139	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T7	16		T11	13		T136	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	15		T53	5		T136	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	1		T12	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T11	11		T86	1		T40	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	11		T149	1		T184	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1577	1			T7	17		T8	31		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T51	1		T52	4		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T137	1		T152	3		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T10	26		T137	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T139	8		T81	1		T85	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T53	17		T144	1		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T143	14		T81	1		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	12		T53	6		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T47	26		T139	14		T141	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T13	9		T152	1		T205	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T14	1		T47	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T144	1		T193	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T46	14		T156	1		T234	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T41	1		T21	2		T263	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17832	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T52	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T3	2		T139	2		T86	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T7	17		T11	12		T136	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T53	4		T136	8		T144	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	9		T12	13		T222	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	6		T86	6		T40	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	2		T149	2		T164	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	934	1			T7	12		T54	19		T149	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T52	2		T85	12		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T152	13		T46	12		T56	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	14		T151	15		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T139	8		T85	16		T45	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T53	8		T144	14		T216	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T16	2		T17	3		T214	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T53	2		T149	11		T83	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T47	16		T139	11		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T205	2		T278	9		T305	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T14	5		T52	12		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T144	6		T214	13		T213	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T46	17		T156	2		T234	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T263	9		T238	8		T297	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T47	3		T16	1		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T52	3		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T276	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T213	1		T279	5		T303	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T3	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T22	11		T295	21		T296	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	5		T139	12		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	10		T11	13		T52	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	15		T136	7		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	1		T7	6		T12	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	11		T53	5		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T137	1		T85	1		T184	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1546	1			T7	17		T8	31		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T6	11		T51	1		T52	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T137	1		T191	8		T152	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T10	26		T85	1		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T81	1		T41	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T137	1		T216	1		T217	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T139	8		T81	1		T85	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	12		T53	23		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T139	14		T141	9		T143	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	9		T152	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	426	1			T14	1		T47	27		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T144	1		T193	1		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T276	7		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T213	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T3	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T22	7		T296	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T139	2		T86	11		T153	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T7	8		T11	12		T52	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T136	8		T86	11		T32	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T3	9		T7	9		T12	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	6		T53	4		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T222	6		T48	1		T164	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	938	1			T7	12		T54	19		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T6	2		T52	2		T149	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T152	13		T46	12		T56	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	14		T85	12		T151	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T45	12		T216	11		T21	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T216	2		T217	12		T213	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T139	8		T85	16		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T53	10		T149	11		T144	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T139	11		T141	3		T17	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T199	2		T155	4		T265	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T14	5		T47	16		T52	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T144	6		T214	13		T213	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T3	3		T14	1		T139	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T7	19		T11	13		T136	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T53	5		T136	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	10		T12	14		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T11	7		T86	7		T40	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T6	3		T149	3		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1276	1			T7	13		T8	3		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	1		T52	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T137	1		T152	14		T46	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T10	16		T137	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T139	9		T81	1		T85	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T53	9		T144	15		T37	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T143	1		T81	1		T16	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T53	3		T149	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T47	21		T139	12		T141	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	1		T152	1		T205	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T14	6		T47	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	7		T193	1		T27	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T46	18		T156	3		T234	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T41	1		T21	2		T263	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17989	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T52	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	11		T14	4		T139	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T7	14		T11	12		T136	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	14		T53	4		T136	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T229	15		T301	2		T266	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	10		T40	7		T56	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	10		T184	4		T229	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T7	16		T8	28		T232	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T52	3		T231	18		T48	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T152	2		T56	8		T21	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	24		T48	3		T164	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T139	7		T162	4		T240	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T53	16		T217	4		T88	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T143	13		T16	2		T191	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	11		T53	5		T228	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	21		T139	13		T141	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T13	8		T234	10		T278	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T52	16		T141	5		T33	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T155	13		T279	4		T280	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T46	13		T234	4		T245	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T303	18		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T153	12		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T52	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T276	8		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T213	10		T279	1		T303	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T3	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T22	10		T295	1		T296	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T14	1		T139	3		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T7	9		T11	13		T52	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	1		T136	9		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T3	10		T7	10		T12	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	7		T53	5		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T137	1		T85	1		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1280	1			T7	13		T8	3		T49	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	3		T51	1		T52	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T137	1		T191	1		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T10	16		T85	13		T36	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T81	1		T41	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T137	1		T216	3		T217	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T139	9		T81	1		T85	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T53	12		T149	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T139	12		T141	4		T143	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	1		T152	1		T46	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	433	1			T14	6		T47	22		T51	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T144	7		T193	1		T27	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T279	4		T303	15		T244	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T3	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T22	8		T295	20		T296	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	4		T139	11		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T7	9		T11	12		T52	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	14		T136	6		T32	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T7	5		T229	15		T301	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	10		T53	4		T40	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T184	4		T48	2		T164	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T7	16		T8	28		T232	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T6	10		T52	3		T231	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T191	7		T152	2		T56	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T10	24		T48	3		T164	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T21	11		T162	4		T240	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T217	4		T110	12		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T139	7		T16	2		T191	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T13	11		T53	21		T228	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T139	13		T141	8		T143	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T13	8		T155	2		T234	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T47	21		T52	16		T141	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T155	13		T278	9		T280	2

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30