Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23291

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3576

1

T3

14

T6

13

T7

29

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20908

1

T1

156

T2

13

T3

53

auto[1]

5959

1

T3

10

T6

13

T7

18

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	339	1			T14	6		T151	11		T216	3
values[0]	77	1			T142	1		T229	16		T166	3
values[1]	696	1			T7	29		T11	25		T51	1
values[2]	722	1			T6	13		T13	12		T136	41
values[3]	691	1			T10	19		T149	12		T150	9
values[4]	536	1			T3	10		T7	33		T10	21
values[5]	2697	1			T8	31		T49	2		T54	21
values[6]	670	1			T13	15		T47	42		T53	8
values[7]	818	1			T3	14		T12	14		T52	6
values[8]	610	1			T52	11		T149	3		T137	1
values[9]	1057	1			T11	17		T13	9		T14	5
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	665	1			T7	29		T13	12		T136	15
values[1]	653	1			T6	13		T10	19		T136	26
values[2]	721	1			T7	33		T149	12		T150	9
values[3]	2576	1			T3	10		T8	31		T10	21
values[4]	589	1			T47	42		T139	16		T86	7
values[5]	755	1			T3	14		T12	14		T13	15
values[6]	751	1			T137	1		T144	7		T81	2
values[7]	606	1			T52	11		T149	3		T83	16
values[8]	1091	1			T13	9		T14	11		T52	29
values[9]	176	1			T11	17		T85	17		T151	11
minimum	18284	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	12		T142	1		T40	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T7	17		T136	7		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T191	3		T152	3		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	11		T10	14		T136	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T7	16		T86	1		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T149	1		T150	9		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1438	1			T3	1		T8	31		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T10	12		T47	1		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T47	26		T45	1		T217	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T139	8		T86	1		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T13	15		T52	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	12		T53	5		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T137	1		T81	2		T83	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	1		T37	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T52	8		T149	1		T32	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T83	5		T138	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T13	9		T52	17		T141	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T14	6		T53	17		T139	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T11	11		T265	10		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T85	1		T151	1		T312	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17919	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T51	1		T36	1		T18	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T40	8		T164	9		T263	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T7	12		T136	8		T48	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T152	13		T148	5		T251	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T6	2		T10	5		T136	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	17		T86	11		T214	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T149	11		T17	12		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T3	9		T54	19		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T10	9		T149	2		T48	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	16		T217	10		T218	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T139	8		T86	6		T46	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T12	13		T52	2		T53	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	2		T53	4		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T83	11		T227	9		T147	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T144	6		T46	12		T154	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T52	3		T149	2		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T83	11		T20	1		T199	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T52	12		T141	5		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T14	5		T53	8		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T11	6		T265	12		T178	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T85	16		T151	10		T313	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T11	12		T47	3		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T18	2		T213	8		T164	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T216	1		T260	1		T314	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T14	1		T151	1		T251	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T142	1		T229	16		T166	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T315	1		T35	1		T310	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T11	13		T40	8		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	17		T51	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T13	12		T86	1		T191	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T6	11		T136	19		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T41	1		T191	3		T214	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	14		T149	1		T150	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T7	16		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T10	12		T47	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1400	1			T8	31		T49	2		T54	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T139	8		T86	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	15		T47	26		T53	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T143	14		T46	14		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T12	1		T52	4		T81	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T3	12		T53	5		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T52	8		T149	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	1		T83	5		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T11	11		T13	9		T52	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	5		T53	17		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T216	2		T260	13		T265	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T14	5		T151	10		T251	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T166	2		T308	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T315	9		T310	11		T309	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T11	12		T40	8		T164	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	12		T18	2		T48	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T86	11		T152	13		T263	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	2		T136	22		T17	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T214	6		T213	2		T22	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T10	5		T149	11		T151	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T3	9		T7	17		T144	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T10	9		T149	2		T17	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	832	1			T54	19		T79	4		T80	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T139	8		T86	6		T215	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T47	16		T53	2		T139	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T46	17		T213	9		T155	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T12	13		T52	2		T83	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	2		T53	4		T46	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T52	3		T149	2		T141	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T144	6		T83	11		T199	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	6		T52	12		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T53	8		T139	2		T144	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T13	1		T142	1		T40	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	13		T136	9		T140	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T191	1		T152	14		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T6	3		T10	6		T136	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T7	19		T86	12		T41	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T149	12		T150	1		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1246	1			T3	10		T8	3		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T10	10		T47	1		T149	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T47	21		T45	1		T217	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	9		T86	7		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T12	14		T13	1		T52	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	3		T53	5		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T137	1		T81	2		T83	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T144	7		T37	1		T46	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T52	4		T149	3		T32	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T83	12		T138	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T13	1		T52	13		T141	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T14	7		T53	9		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T11	7		T265	13		T311	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T85	17		T151	11		T312	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18055	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T51	1		T36	1		T18	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	11		T40	7		T229	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	16		T136	6		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T191	2		T152	2		T148	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T6	10		T10	13		T136	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	14		T191	8		T269	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T150	8		T17	12		T228	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1115	1			T8	28		T232	19		T158	28
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T10	11		T48	3		T215	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T47	21		T217	4		T280	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T139	7		T191	7		T46	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	14		T52	3		T53	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	11		T53	4		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T83	11		T227	10		T56	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T229	17		T235	8		T234	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T52	7		T32	4		T192	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T83	4		T33	15		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	8		T52	16		T141	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T14	4		T53	16		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T11	10		T265	9		T178	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T312	12		T305	13		T313	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T11	12		T229	15		T162	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T18	3		T164	8		T316	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T216	3		T260	14		T314	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T14	6		T151	11		T251	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T142	1		T229	1		T166	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T315	10		T35	1		T310	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	13		T40	9		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T7	13		T51	1		T140	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	1		T86	12		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T6	3		T136	24		T17	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T41	1		T191	1		T214	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T10	6		T149	12		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	10		T7	19		T51	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T10	10		T47	1		T149	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1148	1			T8	3		T49	2		T54	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T139	9		T86	7		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	1		T47	21		T53	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T143	1		T46	18		T213	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T12	14		T52	3		T81	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	327	1			T3	3		T53	5		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T52	4		T149	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T144	7		T83	12		T138	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T11	7		T13	1		T52	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T14	1		T53	9		T139	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T259	10		T265	9		T178	17
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T312	12		T305	13		T313	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T229	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T310	6		T309	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	12		T40	7		T162	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T7	16		T143	2		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	11		T191	8		T152	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	10		T136	17		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T191	2		T22	8		T245	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T10	13		T150	8		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T7	14		T17	16		T215	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T10	11		T17	12		T48	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1084	1			T8	28		T232	19		T158	28
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T139	7		T191	7		T215	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T13	14		T47	21		T53	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T143	13		T46	13		T155	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T52	3		T83	11		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	11		T53	4		T229	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T52	7		T141	5		T32	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T83	4		T33	15		T165	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	10		T13	8		T52	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	4		T53	16		T139	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30