Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23597

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3270

1

T3

14

T11

25

T12

14

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21171

1

T1

156

T2

13

T3

53

auto[1]

5696

1

T3

10

T7

29

T8

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	239	1			T6	13		T12	14		T13	15
values[0]	39	1			T21	1		T210	3		T203	1
values[1]	651	1			T3	10		T136	26		T137	1
values[2]	630	1			T10	21		T53	25		T149	3
values[3]	763	1			T10	19		T51	1		T83	23
values[4]	627	1			T7	18		T47	1		T53	8
values[5]	790	1			T7	29		T14	5		T53	9
values[6]	642	1			T13	21		T139	25		T140	1
values[7]	728	1			T11	25		T149	3		T137	1
values[8]	821	1			T3	14		T7	15		T11	17
values[9]	2983	1			T8	31		T49	2		T51	1
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	605	1			T3	10		T137	1		T81	1
values[1]	677	1			T10	21		T149	3		T83	23
values[2]	661	1			T10	19		T51	1		T53	25
values[3]	653	1			T7	18		T47	1		T53	8
values[4]	857	1			T7	29		T14	5		T53	9
values[5]	663	1			T13	21		T139	25		T140	1
values[6]	2882	1			T7	15		T8	31		T11	25
values[7]	760	1			T3	14		T11	17		T14	6
values[8]	822	1			T13	15		T52	35		T139	30
values[9]	104	1			T6	13		T12	14		T46	31
minimum	18183	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	1		T137	1		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T85	2		T17	1		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T10	12		T16	5		T32	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T149	1		T83	12		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T10	14		T51	1		T53	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T144	1		T44	1		T228	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T7	10		T47	1		T149	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T53	6		T81	1		T83	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T7	17		T14	5		T53	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T83	5		T27	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	12		T141	6		T20	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	9		T139	14		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1544	1			T7	6		T8	31		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	13		T150	9		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	11		T86	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T3	12		T14	1		T47	26
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	15		T52	4		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T52	17		T139	20		T141	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T6	11		T110	13		T219	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T12	1		T46	14		T171	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17890	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T40	8		T317	2		T210	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T3	9		T56	9		T192	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T85	16		T17	3		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T10	9		T16	2		T32	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T149	2		T83	11		T148	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T10	5		T53	8		T86	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T144	14		T153	20		T21	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	8		T149	11		T17	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T53	2		T83	1		T215	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	12		T53	4		T136	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T83	11		T216	2		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T141	2		T20	1		T217	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T139	11		T32	1		T218	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T7	9		T54	19		T149	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T11	12		T144	5		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T11	6		T86	11		T213	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	2		T14	5		T47	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T52	2		T151	10		T48	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T52	12		T139	10		T141	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T6	2		T219	10		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T12	13		T46	17		T171	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T47	3		T136	14		T144	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T40	8		T210	2		T300	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T6	11		T13	15		T17	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T12	1		T46	14		T255	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T21	1		T203	1		T318	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T210	1		T300	2		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	1		T136	12		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T85	2		T40	8		T152	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T10	12		T53	17		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T149	1		T138	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T10	14		T51	1		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T83	12		T44	1		T228	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	10		T47	1		T17	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T53	6		T144	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	17		T14	5		T53	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T83	1		T41	1		T216	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	12		T141	6		T20	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	9		T139	14		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T149	1		T81	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	13		T137	1		T144	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	6		T11	11		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T3	12		T14	1		T47	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1585	1			T8	31		T49	2		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T51	1		T52	25		T139	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T6	2		T151	10		T169	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T12	13		T46	17		T88	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T318	3		T224	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T210	2		T300	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	9		T136	14		T144	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T85	16		T40	8		T152	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T10	9		T53	8		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T149	2		T17	3		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T10	5		T86	11		T147	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T83	11		T153	20		T213	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	8		T17	12		T214	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T53	2		T144	14		T215	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T7	12		T53	4		T149	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T83	1		T216	2		T217	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T141	2		T20	1		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T139	11		T83	11		T32	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T149	2		T222	6		T217	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T11	12		T144	5		T164	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T7	9		T11	6		T86	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	2		T14	5		T47	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T52	2		T54	19		T79	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T52	15		T139	10		T141	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T3	10		T137	1		T81	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T85	18		T17	4		T152	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T10	10		T16	5		T32	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T149	3		T83	12		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T10	6		T51	1		T53	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T144	15		T44	1		T228	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T7	9		T47	1		T149	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T53	3		T81	1		T83	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	13		T14	1		T53	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T83	12		T27	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T13	1		T141	3		T20	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	1		T139	12		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T7	10		T8	3		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	13		T150	1		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T11	7		T86	12		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	3		T14	6		T47	21
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	1		T52	3		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T52	13		T139	12		T141	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T6	3		T110	1		T219	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T12	14		T46	18		T171	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18047	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T40	9		T317	2		T210	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T56	8		T192	2		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T152	2		T227	10		T235	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	11		T16	2		T215	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T83	11		T148	13		T199	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	13		T53	16		T56	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T228	9		T153	12		T21	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	9		T17	12		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T53	5		T215	9		T110	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	16		T14	4		T53	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T83	4		T231	18		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	11		T141	5		T20	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	8		T139	13		T32	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1219	1			T7	5		T8	28		T232	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T11	12		T150	8		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T11	10		T229	17		T106	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T3	11		T47	21		T52	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	14		T52	3		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T52	16		T139	18		T141	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T6	10		T110	12		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T46	13		T212	8		T319	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T136	11		T184	4		T33	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T40	7		T300	1		T293	9

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T6	3		T13	1		T17	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T12	14		T46	18		T255	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T21	1		T203	1		T318	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T210	3		T300	2		T220	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	10		T136	15		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T85	18		T40	9		T152	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T10	10		T53	9		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T149	3		T138	1		T17	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T10	6		T51	1		T86	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T83	12		T44	1		T228	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	9		T47	1		T17	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T53	3		T144	15		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	13		T14	1		T53	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T83	2		T41	1		T216	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	1		T141	3		T20	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T13	1		T139	12		T140	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T149	3		T81	1		T222	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	13		T137	1		T144	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	10		T11	7		T86	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	3		T14	6		T47	21
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T8	3		T49	2		T52	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T51	1		T52	17		T139	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T6	10		T13	14		T320	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T46	13		T255	7		T88	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T318	6		T224	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T300	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T136	11		T184	4		T33	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T40	7		T152	2		T235	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	11		T53	16		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T227	10		T148	7		T93	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T10	13		T155	2		T268	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T83	11		T228	9		T153	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T7	9		T17	12		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T53	5		T215	9		T21	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	16		T14	4		T53	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T217	4		T155	13		T226	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T13	11		T141	5		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	8		T139	13		T83	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T217	4		T278	9		T266	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T11	12		T191	2		T164	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	5		T11	10		T106	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	11		T47	21		T150	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T8	28		T52	3		T232	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T52	23		T139	18		T141	8

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30