Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23250

1

T1

156

T2

13

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

3617

1

T3

10

T6

13

T7

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20956

1

T1

156

T2

13

T3

63

auto[1]

5911

1

T7

47

T8

31

T11

17

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	206	1			T51	1		T53	8		T149	3
values[0]	48	1			T144	15		T230	10		T321	10
values[1]	571	1			T11	17		T53	25		T137	1
values[2]	2846	1			T8	31		T13	15		T14	5
values[3]	564	1			T137	1		T40	16		T231	19
values[4]	796	1			T3	10		T14	6		T139	16
values[5]	744	1			T3	14		T7	29		T13	9
values[6]	574	1			T149	12		T141	8		T86	19
values[7]	567	1			T10	19		T13	12		T47	42
values[8]	974	1			T7	33		T11	25		T12	14
values[9]	1023	1			T6	13		T10	21		T52	17
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	570	1			T11	17		T14	5		T53	25
values[1]	2744	1			T8	31		T13	15		T49	2
values[2]	659	1			T139	16		T140	1		T144	6
values[3]	744	1			T3	10		T7	29		T14	6
values[4]	726	1			T3	14		T13	9		T47	1
values[5]	531	1			T47	42		T149	12		T141	8
values[6]	628	1			T10	19		T11	25		T13	12
values[7]	977	1			T6	13		T7	15		T12	14
values[8]	900	1			T7	18		T10	21		T51	1
values[9]	137	1			T52	11		T86	12		T307	1
minimum	18251	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T11	11		T14	5		T53	17
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T137	1		T144	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1516	1			T8	31		T13	15		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T52	17		T41	1		T151	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T140	1		T40	8		T48	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T139	8		T144	1		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	1		T142	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T3	1		T7	17		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	12		T47	1		T83	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	9		T85	1		T33	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T149	1		T141	6		T222	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T47	26		T86	2		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T10	14		T11	13		T13	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T144	1		T143	3		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T12	1		T51	1		T53	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T6	11		T7	6		T139	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T7	10		T10	12		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T52	4		T53	6		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T52	8		T86	1		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T214	1		T19	1		T167	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17869	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T85	1		T37	1		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T11	6		T53	8		T32	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	14		T147	4		T155	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	887	1			T54	19		T149	2		T79	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T52	12		T151	15		T215	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T40	8		T48	1		T217	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T139	8		T144	5		T106	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T14	5		T216	11		T46	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	9		T7	12		T83	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	2		T83	11		T192	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T17	12		T151	10		T214	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T149	11		T141	2		T222	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T47	16		T86	17		T162	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T10	5		T11	12		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T144	6		T153	20		T164	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T12	13		T53	4		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T6	2		T7	9		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T7	8		T10	9		T149	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T52	2		T53	2		T26	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T52	3		T86	11		T234	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T214	6		T250	10		T322	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T47	3		T83	1		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T85	12		T265	12		T223	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T51	1		T149	1		T45	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T53	6		T217	5		T164	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T230	3		T323	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T144	1		T321	5		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	11		T53	17		T83	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T137	1		T85	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1543	1			T8	31		T13	15		T14	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T52	17		T41	1		T215	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T137	1		T40	8		T48	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T231	19		T151	1		T263	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	1		T140	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T3	1		T139	8		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	12		T47	1		T83	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T7	17		T13	9		T85	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T149	1		T141	6		T222	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T86	2		T33	16		T151	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	14		T13	12		T36	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T47	26		T143	3		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T7	10		T11	13		T12	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	6		T139	14		T136	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T10	12		T52	8		T139	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T6	11		T52	4		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T149	2		T45	12		T216	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T53	2		T217	10		T164	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T230	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T144	14		T321	5		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	6		T53	8		T83	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T85	12		T264	9		T239	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T54	19		T149	2		T79	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T52	12		T215	8		T164	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T40	8		T48	1		T169	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T151	15		T263	9		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T14	5		T216	11		T46	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	9		T139	8		T144	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	2		T83	11		T192	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T7	12		T85	16		T17	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T149	11		T141	2		T222	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T86	17		T151	10		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	5		T36	18		T199	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T47	16		T153	20		T260	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T7	8		T11	12		T12	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T7	9		T139	11		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T10	9		T52	3		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T6	2		T52	2		T26	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T11	7		T14	1		T53	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T137	1		T144	15		T147	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1217	1			T8	3		T13	1		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T52	13		T41	1		T151	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T140	1		T40	9		T48	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T139	9		T144	6		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	6		T142	1		T138	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	10		T7	13		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	3		T47	1		T83	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T13	1		T85	1		T33	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T149	12		T141	3		T222	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T47	21		T86	19		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T10	6		T11	13		T13	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T144	7		T143	1		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T12	14		T51	1		T53	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T6	3		T7	10		T139	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T7	9		T10	10		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T52	3		T53	3		T163	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T52	4		T86	12		T307	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T214	7		T19	1		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18042	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T85	13		T37	1		T188	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T11	10		T14	4		T53	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	13		T93	10		T165	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1186	1			T8	28		T13	14		T232	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T52	16		T215	2		T164	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T40	7		T48	2		T217	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T139	7		T231	18		T106	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T215	9		T167	8		T171	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	16		T83	11		T102	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T3	11		T83	4		T192	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	8		T33	15		T17	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T141	5		T16	2		T229	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T47	21		T324	8		T179	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T10	13		T11	12		T13	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T143	2		T153	12		T164	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T53	4		T150	8		T141	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T6	10		T7	5		T139	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T7	9		T10	11		T139	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T52	3		T53	5		T191	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T52	7		T234	4		T325	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T167	9		T322	6		T326	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T230	2		T223	11		T236	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T327	8		T265	9		T223	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T51	1		T149	3		T45	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T53	3		T217	11		T164	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T230	8		T323	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T144	15		T321	6		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	7		T53	9		T83	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T137	1		T85	13		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T8	3		T13	1		T14	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T52	13		T41	1		T215	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T137	1		T40	9		T48	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T231	1		T151	16		T263	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T14	6		T140	1		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T3	10		T139	9		T144	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T3	3		T47	1		T83	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T7	13		T13	1		T85	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T149	12		T141	3		T222	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T86	19		T33	1		T151	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	6		T13	1		T36	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T47	21		T143	1		T81	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T7	9		T11	13		T12	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	10		T139	12		T136	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	280	1			T10	10		T52	4		T139	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T6	3		T52	3		T163	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T234	4		T328	3		T172	12
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T53	5		T217	4		T164	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T230	2		T323	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T321	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T11	10		T53	16		T184	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T280	2		T327	8		T265	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1205	1			T8	28		T13	14		T14	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T52	16		T215	2		T164	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T40	7		T48	2		T211	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T231	18		T148	6		T169	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T215	9		T217	4		T103	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T139	7		T83	11		T102	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T3	11		T83	4		T192	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	16		T13	8		T17	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T141	5		T16	2		T229	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T33	15		T191	2		T148	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T10	13		T13	11		T255	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T47	21		T143	2		T153	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T7	9		T11	12		T53	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T7	5		T139	13		T136	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T10	11		T52	7		T139	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T6	10		T52	3		T17	16

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30