Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21291

1

T1

156

T2

13

T3

53

auto[ADC_CTRL_FILTER_COND_OUT]

5576

1

T3

10

T6

13

T7

44

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21137

1

T1

156

T2

13

T3

49

auto[1]

5730

1

T3

14

T7

15

T8

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T144	7		T81	1		T32	9
values[0]	36	1			T137	1		T214	7		T279	1
values[1]	977	1			T3	14		T52	6		T53	33
values[2]	736	1			T6	13		T136	26		T140	1
values[3]	574	1			T13	12		T51	1		T141	8
values[4]	792	1			T7	29		T12	14		T51	1
values[5]	661	1			T14	5		T47	1		T52	11
values[6]	657	1			T3	10		T10	19		T11	25
values[7]	663	1			T13	15		T150	9		T81	1
values[8]	600	1			T7	18		T13	9		T149	3
values[9]	2953	1			T7	15		T8	31		T10	21
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1065	1			T3	14		T52	6		T53	33
values[1]	2638	1			T6	13		T8	31		T49	2
values[2]	656	1			T13	12		T51	1		T149	3
values[3]	798	1			T7	29		T12	14		T51	1
values[4]	631	1			T3	10		T14	5		T47	1
values[5]	607	1			T10	19		T11	25		T52	29
values[6]	653	1			T13	15		T150	9		T81	1
values[7]	649	1			T7	18		T11	17		T13	9
values[8]	798	1			T7	15		T10	21		T14	6
values[9]	160	1			T144	7		T81	1		T32	9
minimum	18212	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T3	12		T52	4		T53	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T53	17		T149	1		T139	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T137	1		T37	1		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1470	1			T6	11		T8	31		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	12		T149	1		T141	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T51	1		T142	1		T85	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T51	1		T52	8		T184	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T7	17		T12	1		T83	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	1		T33	16		T40	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	1		T14	5		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T10	14		T222	1		T152	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	13		T52	17		T143	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T13	15		T81	1		T83	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T150	9		T36	4		T213	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	10		T144	1		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T11	11		T13	9		T149	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	1		T47	26		T143	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	6		T10	12		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T144	1		T81	1		T32	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T48	3		T242	8		T240	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17901	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T154	1		T148	8		T317	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	2		T52	2		T53	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T53	8		T149	11		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T215	7		T20	1		T263	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	864	1			T6	2		T54	19		T79	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T149	2		T141	2		T83	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T85	12		T86	11		T199	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T52	3		T18	2		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	12		T12	13		T83	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	6		T40	8		T151	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	9		T53	4		T139	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	5		T222	6		T152	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T11	12		T52	12		T85	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T83	1		T86	6		T26	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T36	18		T213	8		T147	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T7	8		T144	5		T260	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	6		T149	2		T147	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T14	5		T47	16		T45	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T7	9		T10	9		T144	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T144	6		T32	1		T88	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T48	1		T242	8		T240	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T47	3		T16	1		T32	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T154	15		T148	7		T317	5

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T144	1		T81	1		T32	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T192	3		T199	10		T88	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T279	1		T262	19		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T137	1		T214	1		T267	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	335	1			T3	12		T52	4		T53	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T53	17		T149	1		T139	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T136	12		T137	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T6	11		T140	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	12		T141	6		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T51	1		T85	1		T86	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T51	1		T149	1		T184	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T7	17		T12	1		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T52	8		T40	8		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	5		T47	1		T139	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T10	14		T32	1		T33	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	1		T11	13		T52	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	15		T81	1		T83	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T150	9		T16	5		T36	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T7	10		T144	1		T155	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	9		T149	1		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T14	1		T47	26		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1582	1			T7	6		T8	31		T10	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T144	6		T32	1		T88	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T192	2		T199	6		T88	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T262	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T214	6		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T3	2		T52	2		T53	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T53	8		T149	11		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T136	14		T215	7		T263	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T6	2		T216	2		T227	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T141	2		T83	11		T20	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T85	12		T86	11		T199	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T149	2		T18	2		T216	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T7	12		T12	13		T83	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T52	3		T40	8		T48	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T139	8		T86	11		T145	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T10	5		T32	6		T151	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T3	9		T11	12		T52	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T83	1		T86	6		T222	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	2		T36	18		T213	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T7	8		T144	5		T155	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T149	2		T155	9		T156	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T14	5		T47	16		T45	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1002	1			T7	9		T10	9		T11	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	305	1			T3	3		T52	3		T53	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T53	9		T149	12		T139	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T137	1		T37	1		T41	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1187	1			T6	3		T8	3		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	1		T149	3		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T51	1		T142	1		T85	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T51	1		T52	4		T184	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T7	13		T12	14		T83	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T32	7		T33	1		T40	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	10		T14	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T10	6		T222	7		T152	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	13		T52	13		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	1		T81	1		T83	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T150	1		T36	22		T213	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T7	9		T144	6		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	7		T13	1		T149	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T14	6		T47	21		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T7	10		T10	10		T144	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T144	7		T81	1		T32	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T48	2		T242	9		T240	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18026	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T154	16		T148	8		T317	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T3	11		T52	3		T53	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T53	16		T139	11		T136	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T231	18		T215	9		T20	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1147	1			T6	10		T8	28		T232	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	11		T141	5		T83	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T162	4		T106	11		T205	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T52	7		T184	4		T18	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T7	16		T83	11		T148	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T33	15		T40	7		T191	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T14	4		T53	4		T139	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T10	13		T152	2		T46	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T11	12		T52	16		T143	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	14		T217	4		T155	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T150	8		T93	10		T165	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T7	9		T265	9		T230	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	10		T13	8		T191	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T47	21		T143	2		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T7	5		T10	11		T17	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T32	4		T88	1		T329	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T48	2		T242	7		T240	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T233	5		T265	15		T262	18
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T148	7		T317	5		T266	18

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T144	7		T81	1		T32	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T192	3		T199	7		T88	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T279	1		T262	3		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T137	1		T214	7		T267	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T3	3		T52	3		T53	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T53	9		T149	12		T139	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T136	15		T137	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T6	3		T140	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	1		T141	3		T81	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T51	1		T85	13		T86	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T51	1		T149	3		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T7	13		T12	14		T142	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T52	4		T40	9		T44	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	1		T47	1		T139	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T10	6		T32	7		T33	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	10		T11	13		T52	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	1		T81	1		T83	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T150	1		T16	5		T36	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	9		T144	6		T155	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	1		T149	3		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	6		T47	21		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1346	1			T7	10		T8	3		T10	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T32	4		T88	1		T330	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T192	2		T199	9		T88	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T262	18		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T267	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	11		T52	3		T53	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T53	16		T139	11		T136	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T136	11		T231	18		T215	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T6	10		T227	10		T215	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T13	11		T141	5		T83	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T162	4		T106	11		T205	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T184	4		T18	3		T228	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T7	16		T83	11		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T52	7		T40	7		T191	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T14	4		T139	7		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	13		T33	15		T152	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T11	12		T52	16		T53	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	14		T217	4		T279	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T150	8		T16	2		T93	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T7	9		T155	13		T269	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	8		T191	7		T255	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	21		T143	2		T56	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1238	1			T7	5		T8	28		T10	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30