Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T10	6		T11	7		T51	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T7	19		T12	14		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T3	10		T139	3		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	10		T141	3		T17	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	1		T53	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	3		T13	1		T51	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T81	1		T86	12		T17	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	21		T163	1		T151	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	13		T83	12		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T13	1		T36	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T149	3		T139	12		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T149	12		T151	11		T45	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T8	3		T14	1		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	312	1			T83	2		T86	7		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T17	1		T36	22		T227	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T52	4		T137	1		T141	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T6	3		T7	13		T52	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T47	1		T149	3		T144	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T144	7		T228	1		T213	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T45	1		T229	1		T162	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17958	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T236	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T10	13		T11	10		T53	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	14		T136	6		T32	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T139	11		T83	4		T191	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	11		T141	5		T17	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T13	11		T53	16		T184	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T3	11		T13	14		T143	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T17	16		T148	9		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T47	21		T240	9		T241	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	12		T83	11		T164	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T13	8		T191	8		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T139	13		T150	8		T18	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T153	12		T217	4		T110	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T8	28		T14	4		T52	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T16	2		T46	13		T242	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T227	10		T155	4		T167	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T52	7		T141	8		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T6	10		T7	16		T52	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T143	2		T103	1		T106	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T228	9		T88	1		T243	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T229	17		T162	4		T171	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T180	9		T244	14		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T236	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	9	39	81.25	9

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T235	1		T171	2		T181	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T10	6		T11	7		T51	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	19		T12	14		T14	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T26	2		T37	1		T191	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	10		T13	1		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T3	10		T53	9		T139	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T3	3		T141	3		T142	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	1		T137	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T47	21		T51	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T11	13		T83	12		T138	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	1		T163	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T149	3		T139	12		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T149	12		T151	11		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	1		T136	15		T33	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T83	2		T27	1		T153	23
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1269	1			T8	3		T49	2		T52	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T47	1		T52	4		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	389	1			T6	3		T7	13		T52	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	329	1			T149	3		T144	6		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T235	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T10	13		T11	10		T53	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T7	14		T32	4		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T191	2		T152	2		T164	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	11		T13	14		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T53	16		T139	11		T83	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	11		T141	5		T21	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	11		T184	4		T40	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T47	21		T143	13		T217	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T11	12		T83	11		T164	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T13	8		T205	1		T245	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T139	13		T150	8		T18	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T191	8		T217	4		T148	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T14	4		T136	11		T33	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T153	12		T211	6		T22	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1180	1			T8	28		T52	16		T232	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T52	7		T141	8		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	10		T7	16		T52	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T143	2		T229	17		T162	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30