Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23534

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3333

1

T3

14

T6

13

T10

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20862

1

T1

155

T2

13

T3

53

auto[1]

6005

1

T1

1

T3

10

T7

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	473	1			T1	1		T9	8		T11	3
values[0]	53	1			T246	23		T247	19		T248	11
values[1]	775	1			T11	25		T53	9		T139	25
values[2]	2789	1			T8	31		T10	21		T47	42
values[3]	710	1			T11	17		T13	12		T144	7
values[4]	783	1			T7	18		T52	29		T139	16
values[5]	664	1			T7	15		T51	1		T149	3
values[6]	722	1			T3	14		T10	19		T14	6
values[7]	650	1			T13	15		T53	8		T149	12
values[8]	596	1			T6	13		T12	14		T137	1
values[9]	1133	1			T3	10		T7	29		T13	9
minimum	17519	1			T1	155		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	960	1			T53	9		T139	25		T140	1
values[1]	2851	1			T8	31		T10	21		T11	25
values[2]	717	1			T11	17		T139	16		T144	7
values[3]	784	1			T7	18		T13	12		T52	29
values[4]	573	1			T7	15		T51	1		T149	3
values[5]	720	1			T3	14		T10	19		T14	6
values[6]	687	1			T12	14		T13	15		T53	8
values[7]	627	1			T6	13		T81	1		T83	2
values[8]	749	1			T7	29		T13	9		T14	5
values[9]	232	1			T3	10		T16	7		T41	1
minimum	17967	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T53	5		T139	14		T143	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T140	1		T81	1		T17	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1545	1			T8	31		T47	26		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	12		T11	13		T52	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T139	8		T144	1		T86	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	11		T141	6		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T7	10		T52	17		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	12		T149	1		T141	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	6		T51	1		T136	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T149	1		T150	9		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T10	14		T14	1		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	12		T85	1		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T12	1		T13	15		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T53	6		T137	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T138	1		T36	4		T229	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	11		T81	1		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	17		T13	9		T14	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T51	1		T52	8		T86	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T3	1		T16	5		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T151	2		T48	3		T249	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17824	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T27	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T53	4		T139	11		T152	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T17	3		T40	8		T18	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	904	1			T47	16		T54	19		T79	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	9		T11	12		T52	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T139	8		T144	6		T86	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	6		T141	2		T32	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	8		T52	12		T144	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T149	2		T141	3		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T7	9		T136	14		T83	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T149	2		T45	12		T215	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T10	5		T14	5		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	2		T85	16		T46	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T12	13		T149	11		T83	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T53	2		T216	11		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T36	18		T215	7		T217	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T6	2		T83	1		T153	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	12		T53	8		T214	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T52	3		T86	11		T214	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T3	9		T16	2		T21	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T151	25		T48	1		T249	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T47	3		T16	1		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	453	1			T1	1		T9	8		T11	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T246	13		T247	10		T248	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T53	5		T139	14		T143	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T11	13		T140	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1513	1			T8	31		T47	26		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	12		T52	4		T136	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T144	1		T86	1		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	11		T13	12		T141	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T7	10		T52	17		T139	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T142	1		T32	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	6		T51	1		T144	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T149	1		T141	9		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T10	14		T14	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	12		T149	1		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	15		T149	1		T83	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T53	6		T44	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T229	18		T217	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T6	11		T137	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T3	1		T7	17		T13	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T51	1		T52	8		T86	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T1	155		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T21	10		T250	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T246	10		T247	9		T248	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T53	4		T139	11		T214	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T11	12		T17	3		T40	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T47	16		T54	19		T79	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T10	9		T52	2		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T144	6		T86	11		T48	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	6		T141	2		T32	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T7	8		T52	12		T139	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T32	6		T216	2		T251	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	9		T144	19		T83	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T149	2		T141	3		T85	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T10	5		T14	5		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	2		T149	2		T45	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T149	11		T83	11		T147	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T53	2		T216	11		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T12	13		T217	12		T162	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T6	2		T83	1		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	9		T7	12		T53	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T52	3		T86	11		T151	25
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T53	5		T139	12		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T140	1		T81	1		T17	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1238	1			T8	3		T47	21		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	10		T11	13		T52	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T139	9		T144	7		T86	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	7		T141	3		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	9		T52	13		T144	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	1		T149	3		T141	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T7	10		T51	1		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T149	3		T150	1		T137	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T10	6		T14	6		T47	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T3	3		T85	17		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T12	14		T13	1		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T53	3		T137	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T138	1		T36	22		T229	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T6	3		T81	1		T83	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	13		T13	1		T14	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T51	1		T52	4		T86	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T3	10		T16	5		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T151	27		T48	2		T249	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17960	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T27	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T53	4		T139	13		T143	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T40	7		T18	3		T192	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1211	1			T8	28		T47	21		T232	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	11		T11	12		T52	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T139	7		T33	15		T191	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T11	10		T141	5		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T7	9		T52	16		T191	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T13	11		T141	8		T148	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T7	5		T136	11		T83	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T150	8		T143	13		T228	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T10	13		T139	11		T231	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T3	11		T46	13		T164	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	14		T83	11		T184	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T53	5		T227	10		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T229	17		T215	9		T217	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T6	10		T191	2		T164	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	16		T13	8		T14	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T52	7		T165	4		T205	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T16	2		T56	2		T21	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T48	2		T252	11		T253	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T254	6		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	460	1			T1	1		T9	8		T11	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T246	11		T247	10		T248	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T53	5		T139	12		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T11	13		T140	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1260	1			T8	3		T47	21		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	10		T52	3		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T144	7		T86	12		T17	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T11	7		T13	1		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T7	9		T52	13		T139	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T142	1		T32	7		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	10		T51	1		T144	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T149	3		T141	4		T85	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T10	6		T14	6		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	3		T149	3		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	1		T149	12		T83	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T53	3		T44	1		T45	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T12	14		T229	1		T217	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	3		T137	1		T81	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T3	10		T7	13		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T51	1		T52	4		T86	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17519	1			T1	155		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T56	2		T21	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T246	12		T247	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	4		T139	13		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T11	12		T40	7		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1182	1			T8	28		T47	21		T232	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T10	11		T52	3		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T191	8		T48	3		T255	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T11	10		T13	11		T141	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T7	9		T52	16		T139	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T103	1		T88	1		T256	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T7	5		T83	4		T229	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T141	8		T228	9		T215	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T10	13		T139	11		T136	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	11		T150	8		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T13	14		T83	11		T184	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T53	5		T227	10		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T229	17		T217	4		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T6	10		T191	2		T155	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	16		T13	8		T14	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T52	7		T48	2		T165	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30