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Summary for Variable clk_gate_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 1 1 50.00


Automatically Generated Bins for clk_gate_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
[auto[1]] 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 26867 1 T1 156 T2 13 T3 63



Summary for Variable cond_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cond_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[ADC_CTRL_FILTER_COND_IN] 21285 1 T1 156 T2 13 T3 53
auto[ADC_CTRL_FILTER_COND_OUT] 5582 1 T3 10 T6 13 T7 44



Summary for Variable en_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for en_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 21080 1 T1 156 T2 13 T3 49
auto[1] 5787 1 T3 14 T7 15 T8 31



Summary for Variable interrupt_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for interrupt_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22878 1 T1 156 T2 13 T3 52
auto[1] 3989 1 T3 11 T6 2 T7 29



Summary for Variable max_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for max_v_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
maximum 11 1 T257 1 T258 10 - -
values[0] 83 1 T52 6 T149 12 T137 1
values[1] 919 1 T3 14 T53 33 T139 39
values[2] 705 1 T6 13 T136 26 T140 1
values[3] 577 1 T13 12 T51 1 T141 8
values[4] 849 1 T7 29 T12 14 T51 1
values[5] 644 1 T14 5 T47 1 T52 11
values[6] 609 1 T3 10 T10 19 T11 25
values[7] 699 1 T13 15 T150 9 T81 1
values[8] 609 1 T7 18 T13 9 T14 6
values[9] 3208 1 T7 15 T8 31 T10 21
minimum 17954 1 T1 156 T2 13 T3 39



Summary for Variable min_v_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 1 11 91.67


User Defined Bins for min_v_cp

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
maximum 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 1266 1 T3 14 T52 6 T53 33
values[1] 2695 1 T6 13 T8 31 T49 2
values[2] 723 1 T13 12 T51 2 T149 3
values[3] 740 1 T7 29 T12 14 T52 11
values[4] 624 1 T3 10 T47 1 T53 9
values[5] 637 1 T10 19 T11 25 T14 5
values[6] 580 1 T13 15 T150 9 T137 1
values[7] 644 1 T7 18 T11 17 T13 9
values[8] 829 1 T7 15 T10 21 T14 6
values[9] 174 1 T144 7 T81 1 T32 9
minimum 17955 1 T1 156 T2 13 T3 39



Summary for Variable wakeup_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for wakeup_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22887 1 T1 156 T2 13 T3 52
auto[1] 3980 1 T3 11 T6 10 T7 30



Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] * -- -- 4
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 371 1 T3 12 T53 6 T139 14
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 337 1 T52 4 T53 17 T149 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 211 1 T137 1 T141 9 T37 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1485 1 T6 11 T8 31 T49 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 227 1 T13 12 T51 1 T149 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T51 1 T142 1 T85 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T52 8 T141 6 T44 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 221 1 T7 17 T12 1 T83 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 199 1 T32 1 T33 16 T40 8
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T3 1 T47 1 T53 5
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 159 1 T10 14 T222 1 T152 3
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 192 1 T11 13 T14 5 T52 17
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T13 15 T81 1 T83 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 120 1 T150 9 T137 1 T147 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 125 1 T7 10 T144 1 T37 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 202 1 T11 11 T13 9 T149 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T14 1 T47 26 T143 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 219 1 T7 6 T10 12 T144 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 46 1 T144 1 T81 1 T32 8
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 67 1 T48 3 T240 10 T259 11
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17818 1 T1 156 T2 13 T3 39
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 302 1 T3 2 T53 2 T139 11
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 256 1 T52 2 T53 8 T149 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 108 1 T141 3 T215 7 T20 1
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 891 1 T6 2 T54 19 T79 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T149 2 T83 11 T216 11
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 176 1 T85 12 T86 11 T199 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 102 1 T52 3 T141 2 T18 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 261 1 T7 12 T12 13 T83 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 139 1 T32 6 T40 8 T151 10
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 139 1 T3 9 T53 4 T139 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 132 1 T10 5 T222 6 T152 13
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 154 1 T11 12 T52 12 T85 16
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T83 1 T86 6 T26 1
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 140 1 T147 14 T93 8 T156 11
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 144 1 T7 8 T144 5 T260 6
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 173 1 T11 6 T149 2 T36 18
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 172 1 T14 5 T47 16 T45 12
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T7 9 T10 9 T144 14
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 40 1 T144 6 T32 1 T217 10
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 21 1 T48 1 T240 9 T261 11
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 137 1 T47 3 T16 1 T32 4



Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 4 44 91.67 4


Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
* [maximum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2
* [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] -- -- 2


Covered bins
interrupt_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 2 1 T257 1 T258 1 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 19 1 T262 19 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 43 1 T52 4 T149 1 T137 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 320 1 T3 12 T53 6 T139 14
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 183 1 T53 17 T139 12 T136 7
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T136 12 T137 1 T138 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 231 1 T6 11 T140 1 T163 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 207 1 T13 12 T141 6 T81 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 109 1 T51 1 T85 1 T216 1
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T51 1 T149 1 T18 7
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 276 1 T7 17 T12 1 T142 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 219 1 T52 8 T40 8 T44 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 156 1 T14 5 T47 1 T139 8
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 163 1 T10 14 T83 1 T32 1
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 178 1 T3 1 T11 13 T52 17
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 191 1 T13 15 T81 1 T86 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T150 9 T16 5 T36 4
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T7 10 T14 1 T144 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 189 1 T13 9 T149 1 T137 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 286 1 T47 26 T144 1 T143 3
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1651 1 T7 6 T8 31 T10 12
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17817 1 T1 156 T2 13 T3 39
auto[1] maximum auto[ADC_CTRL_FILTER_COND_IN] 9 1 T258 9 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 2 1 T262 2 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 19 1 T52 2 T149 11 T214 6
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 259 1 T3 2 T53 2 T139 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T53 8 T139 2 T136 8
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 118 1 T136 14 T215 7 T263 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 181 1 T6 2 T227 9 T215 8
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 114 1 T141 2 T83 11 T20 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 147 1 T85 12 T216 2 T46 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T149 2 T18 2 T216 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 275 1 T7 12 T12 13 T83 11
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T52 3 T40 8 T48 1
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 128 1 T139 8 T145 4 T264 9
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 137 1 T10 5 T83 1 T32 6
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 131 1 T3 9 T11 12 T52 12
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 156 1 T86 6 T222 6 T46 17
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 207 1 T16 2 T36 18 T213 8
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 146 1 T7 8 T14 5 T144 5
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 133 1 T149 2 T155 9 T156 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 228 1 T47 16 T144 6 T32 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1043 1 T7 9 T10 9 T11 6
auto[1] minimum auto[ADC_CTRL_FILTER_COND_IN] 137 1 T47 3 T16 1 T32 4



Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 7 41 85.42 7


Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] * -- -- 2
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmin_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 368 1 T3 3 T53 3 T139 12
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 324 1 T52 3 T53 9 T149 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 141 1 T137 1 T141 4 T37 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1213 1 T6 3 T8 3 T49 2
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 198 1 T13 1 T51 1 T149 3
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 210 1 T51 1 T142 1 T85 13
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 149 1 T52 4 T141 3 T44 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 314 1 T7 13 T12 14 T83 12
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 181 1 T32 7 T33 1 T40 9
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 171 1 T3 10 T47 1 T53 5
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 168 1 T10 6 T222 7 T152 14
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 196 1 T11 13 T14 1 T52 13
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 177 1 T13 1 T81 1 T83 2
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 170 1 T150 1 T137 1 T147 15
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 171 1 T7 9 T144 6 T37 1
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T11 7 T13 1 T149 3
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 227 1 T14 6 T47 21 T143 1
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 249 1 T7 10 T10 10 T144 15
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 56 1 T144 7 T81 1 T32 5
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 35 1 T48 2 T240 10 T259 1
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17955 1 T1 156 T2 13 T3 39
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 305 1 T3 11 T53 5 T139 13
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 269 1 T52 3 T53 16 T139 11
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T141 8 T231 18 T215 9
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 1163 1 T6 10 T8 28 T232 19
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 178 1 T13 11 T83 4 T184 4
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 137 1 T162 4 T106 11 T205 1
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 109 1 T52 7 T141 5 T18 3
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 168 1 T7 16 T83 11 T148 6
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 157 1 T33 15 T40 7 T191 8
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 115 1 T53 4 T139 7 T145 2
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 123 1 T10 13 T152 2 T46 13
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 150 1 T11 12 T14 4 T52 16
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 143 1 T13 14 T217 4 T155 13
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 90 1 T150 8 T93 10 T165 8
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 98 1 T7 9 T265 9 T230 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T11 10 T13 8 T191 7
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 173 1 T47 21 T143 2 T56 2
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 180 1 T7 5 T10 11 T17 12
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 30 1 T32 4 T217 4 T88 1
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 53 1 T48 2 T240 9 T259 10



Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 48 6 42 87.50 6


Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [maximum] * -- -- 2
[auto[1]] [minimum] * -- -- 2


Uncovered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTNUMBERSTATUS
[auto[0]] [maximum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1
[auto[0]] [minimum] [auto[ADC_CTRL_FILTER_COND_OUT]] 0 1 1


Covered bins
wakeup_cpmax_v_cpcond_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] maximum auto[ADC_CTRL_FILTER_COND_IN] 11 1 T257 1 T258 10 - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_IN] 3 1 T262 3 - - - -
auto[0] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 27 1 T52 3 T149 12 T137 1
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_IN] 316 1 T3 3 T53 3 T139 12
auto[0] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 195 1 T53 9 T139 3 T136 9
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_IN] 151 1 T136 15 T137 1 T138 1
auto[0] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 222 1 T6 3 T140 1 T163 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T13 1 T141 3 T81 1
auto[0] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 174 1 T51 1 T85 13 T216 3
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_IN] 161 1 T51 1 T149 3 T18 6
auto[0] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 337 1 T7 13 T12 14 T142 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_IN] 194 1 T52 4 T40 9 T44 1
auto[0] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 162 1 T14 1 T47 1 T139 9
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_IN] 179 1 T10 6 T83 2 T32 7
auto[0] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 161 1 T3 10 T11 13 T52 13
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_IN] 192 1 T13 1 T81 1 T86 7
auto[0] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 252 1 T150 1 T16 5 T36 22
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_IN] 175 1 T7 9 T14 6 T144 6
auto[0] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 165 1 T13 1 T149 3 T137 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_IN] 300 1 T47 21 T144 7 T143 1
auto[0] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1401 1 T7 10 T8 3 T10 10
auto[0] minimum auto[ADC_CTRL_FILTER_COND_IN] 17954 1 T1 156 T2 13 T3 39
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_IN] 18 1 T262 18 - - - -
auto[1] values[0] auto[ADC_CTRL_FILTER_COND_OUT] 35 1 T52 3 T266 18 T267 4
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_IN] 263 1 T3 11 T53 5 T139 13
auto[1] values[1] auto[ADC_CTRL_FILTER_COND_OUT] 145 1 T53 16 T139 11 T136 6
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_IN] 142 1 T136 11 T231 18 T215 9
auto[1] values[2] auto[ADC_CTRL_FILTER_COND_OUT] 190 1 T6 10 T227 10 T215 2
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T13 11 T141 5 T83 4
auto[1] values[3] auto[ADC_CTRL_FILTER_COND_OUT] 82 1 T162 4 T106 11 T268 12
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_IN] 137 1 T18 3 T228 9 T21 11
auto[1] values[4] auto[ADC_CTRL_FILTER_COND_OUT] 214 1 T7 16 T83 11 T148 6
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_IN] 166 1 T52 7 T40 7 T191 8
auto[1] values[5] auto[ADC_CTRL_FILTER_COND_OUT] 122 1 T14 4 T139 7 T145 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_IN] 121 1 T10 13 T33 15 T152 2
auto[1] values[6] auto[ADC_CTRL_FILTER_COND_OUT] 148 1 T11 12 T52 16 T53 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_IN] 155 1 T13 14 T46 13 T217 4
auto[1] values[7] auto[ADC_CTRL_FILTER_COND_OUT] 100 1 T150 8 T16 2 T93 10
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_IN] 112 1 T7 9 T155 13 T269 9
auto[1] values[8] auto[ADC_CTRL_FILTER_COND_OUT] 157 1 T13 8 T191 7 T255 15
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_IN] 214 1 T47 21 T143 2 T32 4
auto[1] values[9] auto[ADC_CTRL_FILTER_COND_OUT] 1293 1 T7 5 T8 28 T10 11



Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 2 2 50.00 2


Automatically Generated Cross Bins for wakeup_gated_xp

Element holes
wakeup_cpclk_gate_cpCOUNTAT LEASTNUMBERSTATUS
* [auto[1]] -- -- 2


Covered bins
wakeup_cpclk_gate_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 22887 1 T1 156 T2 13 T3 52
auto[1] auto[0] 3980 1 T3 11 T6 10 T7 30

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