Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23262

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3605

1

T3

14

T10

19

T11

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20980

1

T1

156

T2

13

T3

39

auto[1]

5887

1

T3

24

T6

13

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	27	1			T233	6		T270	1		T271	20
values[0]	12	1			T150	9		T203	1		T272	1
values[1]	658	1			T7	18		T52	11		T136	26
values[2]	634	1			T3	10		T11	42		T53	8
values[3]	828	1			T51	1		T149	3		T139	16
values[4]	599	1			T3	14		T10	21		T51	1
values[5]	2928	1			T7	44		T8	31		T12	14
values[6]	727	1			T10	19		T13	21		T149	3
values[7]	506	1			T6	13		T13	15		T52	29
values[8]	781	1			T14	5		T47	1		T52	6
values[9]	1213	1			T14	6		T53	25		T139	14
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	711	1			T7	18		T52	11		T139	25
values[1]	704	1			T3	10		T11	42		T53	8
values[2]	878	1			T51	1		T53	9		T85	17
values[3]	2764	1			T8	31		T10	21		T49	2
values[4]	784	1			T3	14		T7	44		T12	14
values[5]	577	1			T13	21		T231	19		T152	16
values[6]	627	1			T6	13		T10	19		T13	15
values[7]	800	1			T52	35		T149	12		T16	7
values[8]	841	1			T14	6		T53	25		T139	14
values[9]	196	1			T144	6		T215	17		T273	9
minimum	17985	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T7	10		T52	8		T150	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T139	14		T136	12		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	1		T11	11		T139	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	13		T53	6		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T53	5		T85	1		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T51	1		T222	1		T229	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T8	31		T10	12		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T149	1		T81	1		T85	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	23		T141	6		T184	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T3	12		T12	1		T47	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T231	19		T152	3		T229	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	21		T216	1		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	11		T13	15		T14	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	14		T47	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T149	1		T16	5		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T52	21		T148	8		T103	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T14	1		T139	12		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T53	17		T137	1		T143	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T273	9		T267	15		T274	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T144	1		T215	10		T275	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17834	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	8		T52	3		T83	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	11		T136	14		T83	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	9		T11	6		T139	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	12		T53	2		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T53	4		T85	16		T17	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T222	6		T148	5		T249	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	917	1			T10	9		T54	19		T79	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T149	2		T85	12		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T7	21		T141	2		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	2		T12	13		T47	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	13		T199	2		T102	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T216	11		T46	12		T213	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T6	2		T149	2		T213	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T10	5		T144	6		T141	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T149	11		T16	2		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T52	14		T148	7		T103	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T14	5		T139	2		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T53	8		T86	11		T215	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T181	15		T276	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T144	5		T215	7		T275	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T47	3		T16	1		T32	4

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T233	6		T271	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T150	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T203	1		T272	1		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	10		T52	8		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T136	12		T137	1		T83	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T3	1		T11	11		T83	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	13		T53	6		T139	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T139	8		T138	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T51	1		T149	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T10	12		T53	5		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	12		T51	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1519	1			T7	23		T8	31		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T12	1		T47	26		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T149	1		T184	5		T152	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	14		T13	21		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	11		T13	15		T231	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T52	17		T144	1		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T14	5		T149	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T47	1		T52	4		T141	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T14	1		T139	12		T136	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T53	17		T137	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T271	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	8		T52	3		T153	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T136	14		T83	11		T251	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	9		T11	6		T83	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	12		T53	2		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	8		T17	18		T46	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T149	2		T148	5		T278	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	9		T53	4		T85	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T3	2		T85	12		T199	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	918	1			T7	21		T54	19		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T12	13		T47	16		T86	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T149	2		T152	13		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	5		T83	11		T216	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	65	1			T6	2		T263	2		T88	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T52	12		T144	6		T86	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T149	11		T16	2		T26	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T52	2		T141	3		T227	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T14	5		T139	2		T136	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T53	8		T144	5		T86	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	9		T52	4		T150	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T139	12		T136	15		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	10		T11	7		T139	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	13		T53	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T53	5		T85	17		T138	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T51	1		T222	7		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1234	1			T8	3		T10	10		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T149	3		T81	1		T85	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T7	23		T141	3		T184	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	3		T12	14		T47	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T231	1		T152	14		T229	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	2		T216	12		T46	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T6	3		T13	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T10	6		T47	1		T144	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T149	12		T16	5		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T52	16		T148	8		T103	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T14	6		T139	3		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T53	9		T137	1		T143	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T273	1		T267	1		T274	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T144	6		T215	8		T275	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17973	1			T1	156		T2	13		T3	39
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	9		T52	7		T150	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T139	13		T136	11		T83	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T11	10		T139	7		T33	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T11	12		T53	5		T17	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T53	4		T17	16		T46	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T229	17		T148	6		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T8	28		T10	11		T232	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T191	15		T279	12		T280	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T7	21		T141	5		T184	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	11		T47	21		T83	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T231	18		T152	2		T229	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T13	19		T211	6		T22	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	10		T13	14		T14	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	13		T141	8		T32	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T16	2		T18	3		T191	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T52	19		T148	7		T103	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T139	11		T136	6		T48	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T53	16		T143	15		T215	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T273	8		T267	14		T274	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T215	9		T275	13		T281	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T282	9		T283	3		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T233	1		T271	11		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T270	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T150	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T203	1		T272	1		T277	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	9		T52	4		T36	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T136	15		T137	1		T83	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	10		T11	7		T83	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	13		T53	3		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T139	9		T138	1		T163	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T51	1		T149	3		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T10	10		T53	5		T85	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	3		T51	1		T81	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1240	1			T7	23		T8	3		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T12	14		T47	21		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T149	3		T184	1		T152	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T10	6		T13	2		T81	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T6	3		T13	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T52	13		T144	7		T86	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T14	1		T149	12		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T47	1		T52	3		T141	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T14	6		T139	3		T136	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T53	9		T137	1		T144	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T233	5		T271	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T150	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	9		T52	7		T153	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T136	11		T83	11		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T11	10		T33	15		T192	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T11	12		T53	5		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T139	7		T17	16		T46	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T229	17		T148	6		T278	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T10	11		T53	4		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	11		T191	8		T165	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1197	1			T7	21		T8	28		T232	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T47	21		T191	7		T164	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T184	4		T152	2		T229	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T10	13		T13	19		T83	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T6	10		T13	14		T231	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T52	16		T32	4		T110	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	4		T16	2		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T52	3		T141	8		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	327	1			T139	11		T136	6		T191	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T53	16		T143	13		T215	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30