Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23274

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3593

1

T3

14

T10

19

T11

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21004

1

T1

156

T2

13

T3

39

auto[1]

5863

1

T3

24

T6

13

T7

15

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	261	1			T53	25		T139	14		T136	15
values[0]	2	1			T203	1		T272	1		-	-
values[1]	619	1			T7	18		T52	11		T136	26
values[2]	725	1			T3	10		T11	42		T53	8
values[3]	790	1			T51	1		T138	1		T163	1
values[4]	580	1			T3	14		T10	21		T51	1
values[5]	2917	1			T7	44		T8	31		T12	14
values[6]	737	1			T10	19		T13	21		T149	3
values[7]	504	1			T6	13		T13	15		T47	1
values[8]	837	1			T14	5		T52	35		T149	12
values[9]	941	1			T14	6		T137	1		T144	6
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	615	1			T7	18		T139	25		T136	26
values[1]	800	1			T3	10		T11	42		T53	8
values[2]	776	1			T51	1		T53	9		T222	7
values[3]	2740	1			T8	31		T10	21		T49	2
values[4]	749	1			T3	14		T7	44		T12	14
values[5]	683	1			T10	19		T13	21		T149	3
values[6]	624	1			T6	13		T13	15		T14	5
values[7]	769	1			T52	35		T149	12		T143	3
values[8]	862	1			T14	6		T139	14		T136	15
values[9]	182	1			T53	25		T144	6		T48	4
minimum	18067	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	10		T150	9		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T139	14		T136	12		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	1		T11	11		T139	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T11	13		T53	6		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T53	5		T138	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T51	1		T222	1		T229	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T8	31		T10	12		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T51	1		T149	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	23		T141	6		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T3	12		T12	1		T47	26
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	1		T184	5		T231	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T10	14		T13	21		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T6	11		T13	15		T14	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T47	1		T144	1		T141	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T149	1		T16	5		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T52	21		T143	3		T214	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T14	1		T139	12		T136	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T137	1		T143	14		T86	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T48	3		T273	9		T267	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T53	17		T144	1		T215	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17851	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T228	10		T251	1		T256	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	8		T45	12		T153	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T139	11		T136	14		T83	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T3	9		T11	6		T139	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T11	12		T53	2		T144	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T53	4		T17	18		T46	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T222	6		T148	5		T249	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	929	1			T10	9		T54	19		T79	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T149	2		T85	12		T86	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T7	21		T141	2		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T3	2		T12	13		T47	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T149	2		T152	13		T199	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T10	5		T216	11		T46	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T6	2		T263	2		T88	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T144	6		T141	3		T86	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T149	11		T16	2		T18	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	14		T214	13		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T14	5		T139	2		T136	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T86	11		T215	8		T164	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T48	1		T276	7		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T53	8		T144	5		T215	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T47	3		T52	3		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T251	9		T256	5		T284	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T139	12		T136	7		T44	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T53	17		T215	10		T279	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T203	1		T272	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	10		T52	8		T150	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T136	12		T137	1		T83	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T3	1		T11	11		T139	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T11	13		T53	6		T139	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T138	1		T163	1		T17	19
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T51	1		T229	18		T148	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T10	12		T53	5		T85	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T3	12		T51	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T7	23		T8	31		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T12	1		T47	26		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T149	1		T184	5		T152	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	14		T13	21		T83	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	11		T13	15		T231	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T47	1		T144	1		T86	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T14	5		T149	1		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T52	21		T141	9		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T14	1		T138	1		T26	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T137	1		T144	1		T143	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T139	2		T136	8		T285	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T53	8		T215	7		T275	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T7	8		T52	3		T153	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T136	14		T83	11		T251	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	9		T11	6		T139	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	12		T53	2		T139	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T17	18		T46	17		T217	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T148	5		T240	12		T23	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T10	9		T53	4		T85	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	2		T149	2		T85	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	932	1			T7	21		T54	19		T141	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T12	13		T47	16		T86	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T149	2		T152	13		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	5		T83	11		T216	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T6	2		T263	2		T88	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T144	6		T86	6		T32	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	11		T16	2		T36	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T52	14		T141	3		T153	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T14	5		T26	1		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T144	5		T86	11		T215	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T7	9		T150	1		T36	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T139	12		T136	15		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	10		T11	7		T139	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T11	13		T53	3		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T53	5		T138	1		T163	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T51	1		T222	7		T229	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T8	3		T10	10		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T51	1		T149	3		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	23		T141	3		T152	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T3	3		T12	14		T47	21
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T149	3		T184	1		T231	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	6		T13	2		T138	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T6	3		T13	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T47	1		T144	7		T141	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T149	12		T16	5		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T52	16		T143	1		T214	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T14	6		T139	3		T136	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T137	1		T143	1		T86	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T48	2		T273	1		T267	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T53	9		T144	6		T215	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17997	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T228	1		T251	10		T256	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T7	9		T150	8		T153	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T139	13		T136	11		T83	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T11	10		T139	7		T33	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T11	12		T53	5		T17	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T53	4		T17	16		T46	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T229	17		T148	6		T165	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T8	28		T10	11		T232	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T191	15		T279	12		T280	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T7	21		T141	5		T56	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T3	11		T47	21		T83	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T184	4		T231	18		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T10	13		T13	19		T211	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T6	10		T13	14		T14	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T141	8		T32	4		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T16	2		T18	3		T191	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T52	19		T143	2		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T139	11		T136	6		T20	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T143	13		T215	2		T164	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T48	2		T273	8		T267	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T53	16		T215	9		T275	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T52	7		T21	11		T286	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T228	9		T256	9		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T139	3		T136	9		T44	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T53	9		T215	8		T279	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T203	1		T272	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T7	9		T52	4		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T136	15		T137	1		T83	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	10		T11	7		T139	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T11	13		T53	3		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T138	1		T163	1		T17	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T51	1		T229	1		T148	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	10		T53	5		T85	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	3		T51	1		T149	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1261	1			T7	23		T8	3		T49	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T12	14		T47	21		T140	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T149	3		T184	1		T152	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T10	6		T13	2		T83	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T6	3		T13	1		T231	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T47	1		T144	7		T86	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T14	1		T149	12		T16	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T52	16		T141	4		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T14	6		T138	1		T26	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T137	1		T144	6		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	71	1			T139	11		T136	6		T233	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T53	16		T215	9		T279	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T7	9		T52	7		T150	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T136	11		T83	11		T228	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T11	10		T139	7		T33	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T11	12		T53	5		T139	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T17	16		T46	13		T217	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T229	17		T148	6		T172	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T10	11		T53	4		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	11		T191	8		T165	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T7	21		T8	28		T232	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T47	21		T191	7		T164	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T184	4		T152	2		T229	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	13		T13	19		T83	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T6	10		T13	14		T231	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T32	4		T227	10		T110	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T14	4		T16	2		T18	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T52	19		T141	8		T143	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T191	2		T48	2		T20	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T143	13		T215	2		T164	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30