Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23403

1

T1

156

T2

13

T3

49

auto[ADC_CTRL_FILTER_COND_OUT]

3464

1

T3

14

T7

33

T10

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21025

1

T1

156

T2

13

T3

39

auto[1]

5842

1

T3

24

T6

13

T8

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	290	1			T6	13		T144	6		T152	1
values[0]	11	1			T235	9		T171	2		-	-
values[1]	612	1			T7	33		T10	19		T11	17
values[2]	830	1			T10	21		T136	15		T144	15
values[3]	651	1			T3	24		T13	15		T53	25
values[4]	644	1			T13	12		T47	42		T51	1
values[5]	498	1			T11	25		T13	9		T83	23
values[6]	792	1			T149	12		T139	25		T140	1
values[7]	780	1			T14	5		T149	3		T136	26
values[8]	2890	1			T8	31		T49	2		T52	40
values[9]	915	1			T7	29		T47	1		T52	6
minimum	17954	1			T1	156		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	659	1			T7	15		T11	17		T12	14
values[1]	787	1			T3	10		T10	21		T139	14
values[2]	664	1			T3	14		T13	27		T53	25
values[3]	560	1			T47	42		T51	1		T81	1
values[4]	565	1			T11	25		T13	9		T83	23
values[5]	867	1			T149	15		T139	25		T140	1
values[6]	2953	1			T8	31		T14	5		T49	2
values[7]	729	1			T52	11		T149	3		T137	1
values[8]	859	1			T7	29		T47	1		T52	6
values[9]	108	1			T6	13		T144	7		T45	1
minimum	18116	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	11		T14	1		T53	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	6		T12	1		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T3	1		T139	12		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T10	12		T136	7		T17	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	12		T53	17		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	12		T13	15		T141	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T81	1		T86	1		T17	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T47	26		T51	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T11	13		T83	12		T213	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T13	9		T138	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T149	1		T139	14		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T149	1		T151	1		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1560	1			T8	31		T14	5		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T83	1		T86	1		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T17	1		T36	4		T227	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T52	8		T149	1		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T7	17		T52	4		T53	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T47	1		T144	1		T143	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T6	11		T144	1		T88	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T45	1		T213	1		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17869	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T7	10		T48	3		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	6		T14	5		T53	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	9		T12	13		T85	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	9		T139	2		T144	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T10	9		T136	8		T17	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T53	8		T215	8		T256	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T3	2		T141	2		T32	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T86	11		T17	15		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	16		T40	8		T147	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	12		T83	11		T213	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T148	5		T88	1		T205	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T149	2		T139	11		T18	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T149	11		T151	10		T45	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T52	12		T54	19		T139	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T83	1		T86	6		T16	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T36	18		T227	9		T155	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T52	3		T149	2		T141	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	12		T52	2		T53	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T144	5		T214	13		T251	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T6	2		T144	6		T88	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T213	8		T288	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T10	5		T47	3		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T7	8		T48	1		T148	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T6	11		T152	1		T21	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T144	1		T45	1		T213	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T235	9		T171	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T10	14		T11	11		T14	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	16		T12	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T144	1		T83	5		T26	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T10	12		T136	7		T17	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	1		T53	17		T139	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T3	12		T13	15		T141	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	12		T137	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T47	26		T51	1		T143	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	13		T83	12		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	9		T138	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T139	14		T140	1		T150	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	1		T151	1		T191	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T14	5		T149	1		T136	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T83	1		T86	1		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1524	1			T8	31		T49	2		T52	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T52	8		T137	1		T141	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T7	17		T52	4		T53	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T47	1		T149	1		T143	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17817	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T6	2		T199	2		T89	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T144	5		T213	8		T251	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T171	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T10	5		T11	6		T14	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	17		T12	13		T85	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T144	14		T83	11		T26	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T10	9		T136	8		T17	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T3	9		T53	8		T139	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	2		T141	2		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T86	11		T17	15		T238	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T47	16		T40	8		T217	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T11	12		T83	11		T213	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T88	1		T205	3		T239	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T139	11		T18	2		T192	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T149	11		T151	10		T45	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T149	2		T136	14		T20	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T83	1		T86	6		T46	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	955	1			T52	12		T54	19		T139	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T52	3		T141	3		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T7	12		T52	2		T53	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T149	2		T214	13		T103	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T11	7		T14	6		T53	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T7	10		T12	14		T137	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T3	10		T139	3		T144	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	10		T136	9		T17	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	1		T53	9		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	3		T13	1		T141	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T81	1		T86	12		T17	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T47	21		T51	1		T163	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T11	13		T83	12		T213	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T13	1		T138	1		T36	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T149	3		T139	12		T140	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T149	12		T151	11		T45	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1270	1			T8	3		T14	1		T49	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T83	2		T86	7		T16	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T17	1		T36	22		T227	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T52	4		T149	3		T137	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T7	13		T52	3		T53	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	288	1			T47	1		T144	6		T143	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T6	3		T144	7		T88	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T45	1		T213	9		T287	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17966	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T7	9		T48	2		T46	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T11	10		T53	4		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T7	5		T32	4		T229	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T139	11		T83	4		T191	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	11		T136	6		T17	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	11		T53	16		T184	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	11		T13	14		T141	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T17	16		T148	9		T199	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T47	21		T40	7		T234	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T11	12		T83	11		T164	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T13	8		T191	8		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T139	13		T150	8		T18	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T217	4		T110	12		T165	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1225	1			T8	28		T14	4		T52	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T16	2		T46	13		T153	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T227	10		T155	4		T167	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T52	7		T141	8		T56	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T7	16		T52	3		T53	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T143	2		T229	17		T162	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T6	10		T88	1		T243	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T244	4		T288	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T10	13		T289	15		T180	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T7	9		T48	2		T148	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T6	3		T152	1		T21	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T144	6		T45	1		T213	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T235	1		T171	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T10	6		T11	7		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	19		T12	14		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T144	15		T83	12		T26	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T10	10		T136	9		T17	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T3	10		T53	9		T139	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	3		T13	1		T141	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	1		T137	1		T81	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T47	21		T51	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T11	13		T83	12		T213	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T13	1		T138	1		T151	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T139	12		T140	1		T150	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T149	12		T151	11		T191	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T14	1		T149	3		T136	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T83	2		T86	7		T27	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1285	1			T8	3		T49	2		T52	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T52	4		T137	1		T141	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T7	13		T52	3		T53	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T47	1		T149	3		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17954	1			T1	156		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T6	10		T89	3		T230	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T106	11		T171	15		T290	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T235	8		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T10	13		T11	10		T53	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T7	14		T32	4		T48	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T83	4		T191	2		T48	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T10	11		T136	6		T17	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T53	16		T139	11		T231	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	11		T13	14		T141	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	11		T184	4		T17	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T47	21		T143	13		T40	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T11	12		T83	11		T164	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T13	8		T205	1		T245	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T139	13		T150	8		T18	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T191	8		T217	4		T148	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	4		T136	11		T33	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T46	13		T153	12		T211	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1194	1			T8	28		T52	16		T232	19
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T52	7		T141	8		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T7	16		T52	3		T53	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T143	2		T229	17		T162	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30