Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26867

1

T1

156

T2

13

T3

63

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23484

1

T1

156

T2

13

T3

63

auto[ADC_CTRL_FILTER_COND_OUT]

3383

1

T6

13

T10

21

T11

42

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20788

1

T1

155

T2

13

T3

49

auto[1]

6079

1

T1

1

T3

14

T7

44

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22878

1

T1

156

T2

13

T3

52

auto[1]

3989

1

T3

11

T6

2

T7

29

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	684	1			T1	1		T7	29		T9	8
values[0]	43	1			T246	23		T291	9		T248	11
values[1]	761	1			T11	25		T53	9		T139	25
values[2]	2815	1			T8	31		T10	21		T47	42
values[3]	746	1			T11	17		T13	12		T144	7
values[4]	739	1			T7	18		T52	29		T139	16
values[5]	611	1			T7	15		T51	1		T149	3
values[6]	773	1			T10	19		T14	6		T47	1
values[7]	667	1			T3	14		T12	14		T13	15
values[8]	591	1			T6	13		T137	1		T81	1
values[9]	918	1			T3	10		T13	9		T51	1
minimum	17519	1			T1	155		T2	13		T3	39

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	747	1			T11	25		T139	25		T143	3
values[1]	2785	1			T8	31		T10	21		T47	42
values[2]	765	1			T11	17		T13	12		T139	16
values[3]	826	1			T7	18		T52	29		T149	3
values[4]	565	1			T7	15		T51	1		T149	3
values[5]	713	1			T3	14		T10	19		T14	6
values[6]	686	1			T12	14		T13	15		T149	12
values[7]	606	1			T6	13		T81	1		T83	2
values[8]	762	1			T7	29		T13	9		T14	5
values[9]	233	1			T3	10		T16	7		T41	1
minimum	18179	1			T1	156		T2	13		T3	39

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

3980

1

T3

11

T6

10

T7

30

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T139	14		T143	3		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	13		T17	1		T40	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1553	1			T8	31		T47	26		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	12		T52	4		T136	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T139	8		T144	1		T141	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T11	11		T13	12		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	10		T144	1		T141	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T52	17		T149	1		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T7	6		T51	1		T136	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T149	1		T150	9		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	12		T10	14		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T53	6		T139	12		T85	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T13	15		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T83	12		T44	1		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T138	1		T36	4		T153	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T6	11		T81	1		T83	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	17		T14	5		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	9		T85	1		T86	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T3	1		T16	5		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T151	1		T56	5		T21	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17886	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T140	1		T81	1		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T139	11		T152	13		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T11	12		T17	3		T40	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T47	16		T54	19		T79	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T10	9		T52	2		T136	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T139	8		T144	6		T141	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	6		T32	1		T17	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	8		T144	14		T141	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T52	12		T149	2		T32	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	9		T136	14		T83	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T149	2		T86	6		T26	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T3	2		T10	5		T14	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T53	2		T139	2		T85	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T12	13		T149	11		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T83	11		T216	11		T227	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	18		T153	1		T215	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T6	2		T83	1		T199	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T7	12		T52	3		T53	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T86	11		T151	15		T214	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T3	9		T16	2		T48	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T151	10		T21	10		T242	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T47	3		T53	4		T16	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T214	10		T246	10		T292	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	504	1			T1	1		T7	17		T9	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T151	1		T214	1		T21	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T291	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T246	13		T248	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T53	5		T139	14		T143	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	13		T140	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T8	31		T47	26		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T10	12		T52	4		T136	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T144	1		T141	6		T86	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T11	11		T13	12		T193	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	10		T139	8		T144	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T52	17		T32	1		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T7	6		T51	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T149	1		T86	1		T26	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T10	14		T14	1		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T149	1		T139	12		T150	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	12		T12	1		T13	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T53	6		T83	12		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T137	1		T153	1		T217	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T6	11		T81	1		T83	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	1		T51	1		T52	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T13	9		T85	1		T86	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17382	1			T1	155		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T7	12		T48	1		T214	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T151	10		T214	6		T21	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T246	10		T248	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T53	4		T139	11		T152	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T11	12		T17	3		T40	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	900	1			T47	16		T54	19		T79	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	9		T52	2		T136	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T144	6		T141	2		T86	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	6		T32	1		T17	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T7	8		T139	8		T144	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T52	12		T32	6		T251	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T7	9		T141	3		T83	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T149	2		T86	6		T26	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T10	5		T14	5		T136	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T149	2		T139	2		T85	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	2		T12	13		T149	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T53	2		T83	11		T216	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T153	1		T217	12		T148	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T6	2		T83	1		T162	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T3	9		T52	3		T53	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T86	11		T151	15		T205	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T47	3		T16	1		T32	4

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T139	12		T143	1		T152	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T11	13		T17	4		T40	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1235	1			T8	3		T47	21		T49	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	10		T52	3		T136	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T139	9		T144	7		T141	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T11	7		T13	1		T193	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T7	9		T144	15		T141	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T52	13		T149	3		T32	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T7	10		T51	1		T136	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T149	3		T150	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	3		T10	6		T14	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T53	3		T139	3		T85	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T12	14		T13	1		T149	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T83	12		T44	1		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T138	1		T36	22		T153	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T6	3		T81	1		T83	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T7	13		T14	1		T51	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	1		T85	1		T86	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T3	10		T16	5		T41	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T151	11		T56	3		T21	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	18018	1			T1	156		T2	13		T3	39
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T140	1		T81	1		T27	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T139	13		T143	2		T152	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	12		T40	7		T18	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1218	1			T8	28		T47	21		T232	19
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T10	11		T52	3		T136	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T139	7		T141	5		T33	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	10		T13	11		T32	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T7	9		T141	8		T191	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T52	16		T148	7		T103	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T7	5		T136	11		T83	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T150	8		T143	13		T278	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T3	11		T10	13		T231	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T53	5		T139	11		T46	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	14		T184	4		T20	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T83	11		T229	13		T227	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T215	9		T217	4		T148	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T6	10		T191	2		T229	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	16		T14	4		T52	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T13	8		T165	4		T205	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T16	2		T48	2		T174	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T56	2		T21	11		T242	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T53	4		T102	1		T233	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T246	12		T293	12		T292	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	532	1			T1	1		T7	13		T9	8
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T151	11		T214	7		T21	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T291	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T246	11		T248	11		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T53	5		T139	12		T143	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	13		T140	1		T81	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1233	1			T8	3		T47	21		T49	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T10	10		T52	3		T136	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T144	7		T141	3		T86	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T11	7		T13	1		T193	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T7	9		T139	9		T144	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T52	13		T32	7		T41	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T7	10		T51	1		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T149	3		T86	7		T26	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T10	6		T14	6		T47	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T149	3		T139	3		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T3	3		T12	14		T13	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T53	3		T83	12		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T137	1		T153	2		T217	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	3		T81	1		T83	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T3	10		T51	1		T52	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T13	1		T85	1		T86	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17519	1			T1	155		T2	13		T3	39
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T7	16		T14	4		T48	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T21	11		T223	11		T253	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T291	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T246	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T53	4		T139	13		T143	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T11	12		T40	7		T18	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1204	1			T8	28		T47	21		T232	19
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T10	11		T52	3		T136	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T141	5		T33	15		T191	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	10		T13	11		T32	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	9		T139	7		T191	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T52	16		T103	1		T88	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T7	5		T141	8		T83	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T148	7		T294	10		T278	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T10	13		T136	11		T231	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T139	11		T150	8		T143	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T3	11		T13	14		T184	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T53	5		T83	11		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T217	4		T148	9		T106	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T6	10		T191	2		T229	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T52	7		T53	16		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	8		T56	2		T110	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22887

1

T1

156

T2

13

T3

52

auto[1]

auto[0]

3980

1

T3

11

T6

10

T7

30