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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.73 99.07 96.67 100.00 100.00 98.83 98.33 91.19


Total test records in report: 919
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T792 /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2140502736 Jul 10 06:20:05 PM PDT 24 Jul 10 06:24:01 PM PDT 24 197606137292 ps
T793 /workspace/coverage/default/34.adc_ctrl_stress_all.968031680 Jul 10 06:17:29 PM PDT 24 Jul 10 06:17:55 PM PDT 24 12046643504 ps
T794 /workspace/coverage/default/13.adc_ctrl_filters_polled.1670790162 Jul 10 06:15:58 PM PDT 24 Jul 10 06:20:06 PM PDT 24 500900724209 ps
T795 /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2485122268 Jul 10 06:15:41 PM PDT 24 Jul 10 06:18:45 PM PDT 24 332330854144 ps
T60 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2990368003 Jul 10 06:14:52 PM PDT 24 Jul 10 06:14:59 PM PDT 24 2323117435 ps
T61 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2479538911 Jul 10 06:14:41 PM PDT 24 Jul 10 06:14:54 PM PDT 24 4955726263 ps
T114 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4278063718 Jul 10 06:14:00 PM PDT 24 Jul 10 06:14:08 PM PDT 24 1969466760 ps
T796 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1927532832 Jul 10 06:14:54 PM PDT 24 Jul 10 06:14:58 PM PDT 24 366045723 ps
T797 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2311892760 Jul 10 06:14:25 PM PDT 24 Jul 10 06:14:31 PM PDT 24 393553434 ps
T115 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3365546443 Jul 10 06:14:21 PM PDT 24 Jul 10 06:14:27 PM PDT 24 1164928961 ps
T63 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3504180152 Jul 10 06:14:49 PM PDT 24 Jul 10 06:15:01 PM PDT 24 4031801389 ps
T116 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2930553006 Jul 10 06:14:19 PM PDT 24 Jul 10 06:14:27 PM PDT 24 1277073935 ps
T124 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1496795328 Jul 10 06:14:35 PM PDT 24 Jul 10 06:14:38 PM PDT 24 388580023 ps
T117 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1815099682 Jul 10 06:14:12 PM PDT 24 Jul 10 06:14:18 PM PDT 24 1179140267 ps
T129 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2293218338 Jul 10 06:14:37 PM PDT 24 Jul 10 06:14:40 PM PDT 24 548739745 ps
T798 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3311669809 Jul 10 06:15:07 PM PDT 24 Jul 10 06:15:12 PM PDT 24 317496675 ps
T66 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3031032231 Jul 10 06:14:49 PM PDT 24 Jul 10 06:14:55 PM PDT 24 467566381 ps
T799 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1773452721 Jul 10 06:14:04 PM PDT 24 Jul 10 06:14:12 PM PDT 24 310900450 ps
T64 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3268160846 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:58 PM PDT 24 8871928495 ps
T72 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1411853461 Jul 10 06:14:32 PM PDT 24 Jul 10 06:14:36 PM PDT 24 346589646 ps
T800 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.860355650 Jul 10 06:14:35 PM PDT 24 Jul 10 06:14:37 PM PDT 24 313976709 ps
T801 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4138410429 Jul 10 06:14:42 PM PDT 24 Jul 10 06:14:44 PM PDT 24 399593717 ps
T74 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4228043158 Jul 10 06:14:30 PM PDT 24 Jul 10 06:14:36 PM PDT 24 399564885 ps
T802 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1275853381 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:53 PM PDT 24 494818765 ps
T62 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1550207333 Jul 10 06:14:22 PM PDT 24 Jul 10 06:14:28 PM PDT 24 2745047237 ps
T803 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1175805301 Jul 10 06:14:55 PM PDT 24 Jul 10 06:15:00 PM PDT 24 323167361 ps
T130 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3842326482 Jul 10 06:14:59 PM PDT 24 Jul 10 06:15:14 PM PDT 24 4981597916 ps
T73 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2719667853 Jul 10 06:14:01 PM PDT 24 Jul 10 06:14:09 PM PDT 24 499520507 ps
T71 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.106522107 Jul 10 06:14:19 PM PDT 24 Jul 10 06:14:28 PM PDT 24 4208915950 ps
T90 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3068481917 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:56 PM PDT 24 895962136 ps
T804 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1754736219 Jul 10 06:14:49 PM PDT 24 Jul 10 06:14:52 PM PDT 24 410160001 ps
T91 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2516354025 Jul 10 06:14:03 PM PDT 24 Jul 10 06:14:11 PM PDT 24 481692772 ps
T805 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3676126995 Jul 10 06:14:05 PM PDT 24 Jul 10 06:14:14 PM PDT 24 531814465 ps
T806 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1625939225 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:51 PM PDT 24 439641480 ps
T131 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.931805268 Jul 10 06:14:42 PM PDT 24 Jul 10 06:14:51 PM PDT 24 2155777346 ps
T118 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.179688212 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:32 PM PDT 24 970798453 ps
T132 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2411578869 Jul 10 06:14:17 PM PDT 24 Jul 10 06:14:30 PM PDT 24 4568259665 ps
T807 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3376976132 Jul 10 06:15:00 PM PDT 24 Jul 10 06:15:05 PM PDT 24 420130714 ps
T808 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.135582634 Jul 10 06:14:56 PM PDT 24 Jul 10 06:15:02 PM PDT 24 432348252 ps
T809 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2316463033 Jul 10 06:14:54 PM PDT 24 Jul 10 06:14:59 PM PDT 24 405709237 ps
T92 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.852260543 Jul 10 06:14:57 PM PDT 24 Jul 10 06:15:04 PM PDT 24 401151545 ps
T65 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3951410598 Jul 10 06:14:42 PM PDT 24 Jul 10 06:14:51 PM PDT 24 8344039601 ps
T119 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1271977795 Jul 10 06:14:03 PM PDT 24 Jul 10 06:15:07 PM PDT 24 26886401963 ps
T810 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1213972233 Jul 10 06:14:01 PM PDT 24 Jul 10 06:14:09 PM PDT 24 439854074 ps
T120 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2002329967 Jul 10 06:14:46 PM PDT 24 Jul 10 06:14:50 PM PDT 24 513240692 ps
T811 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1710078153 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:52 PM PDT 24 388540397 ps
T812 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4254406519 Jul 10 06:14:38 PM PDT 24 Jul 10 06:14:42 PM PDT 24 591335739 ps
T813 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1482753397 Jul 10 06:15:05 PM PDT 24 Jul 10 06:15:10 PM PDT 24 526153678 ps
T814 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.841265313 Jul 10 06:14:58 PM PDT 24 Jul 10 06:15:04 PM PDT 24 974077353 ps
T133 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.247073617 Jul 10 06:14:03 PM PDT 24 Jul 10 06:14:16 PM PDT 24 5289623611 ps
T815 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.752007345 Jul 10 06:14:37 PM PDT 24 Jul 10 06:14:39 PM PDT 24 371907665 ps
T816 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1251485319 Jul 10 06:14:54 PM PDT 24 Jul 10 06:14:58 PM PDT 24 352032210 ps
T817 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1602603102 Jul 10 06:14:18 PM PDT 24 Jul 10 06:14:23 PM PDT 24 379867572 ps
T67 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1002546378 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:56 PM PDT 24 4539624528 ps
T121 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2467646502 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:50 PM PDT 24 491771066 ps
T818 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.422503166 Jul 10 06:14:00 PM PDT 24 Jul 10 06:14:08 PM PDT 24 1205361100 ps
T819 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1014173070 Jul 10 06:14:54 PM PDT 24 Jul 10 06:14:59 PM PDT 24 691917999 ps
T820 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1211468623 Jul 10 06:14:57 PM PDT 24 Jul 10 06:15:02 PM PDT 24 383068717 ps
T122 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3619466480 Jul 10 06:14:03 PM PDT 24 Jul 10 06:15:43 PM PDT 24 40806105975 ps
T336 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3239154862 Jul 10 06:14:11 PM PDT 24 Jul 10 06:14:20 PM PDT 24 4892029770 ps
T821 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2650123141 Jul 10 06:14:34 PM PDT 24 Jul 10 06:14:37 PM PDT 24 395123019 ps
T822 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1640189487 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:50 PM PDT 24 503588474 ps
T823 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.825137089 Jul 10 06:14:39 PM PDT 24 Jul 10 06:14:43 PM PDT 24 2728056197 ps
T824 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2806297670 Jul 10 06:14:14 PM PDT 24 Jul 10 06:14:21 PM PDT 24 331727544 ps
T825 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2166756021 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:53 PM PDT 24 1021602950 ps
T826 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2550342650 Jul 10 06:14:27 PM PDT 24 Jul 10 06:14:34 PM PDT 24 481778920 ps
T827 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1506554521 Jul 10 06:14:46 PM PDT 24 Jul 10 06:14:51 PM PDT 24 731420176 ps
T828 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4148944588 Jul 10 06:14:17 PM PDT 24 Jul 10 06:14:23 PM PDT 24 575441965 ps
T829 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2475954999 Jul 10 06:14:46 PM PDT 24 Jul 10 06:14:52 PM PDT 24 2293872052 ps
T830 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1965259738 Jul 10 06:14:15 PM PDT 24 Jul 10 06:14:42 PM PDT 24 26705689321 ps
T831 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2896318937 Jul 10 06:14:32 PM PDT 24 Jul 10 06:14:36 PM PDT 24 539871041 ps
T832 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.86706760 Jul 10 06:15:08 PM PDT 24 Jul 10 06:15:13 PM PDT 24 527622288 ps
T833 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3267442817 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:57 PM PDT 24 4413423727 ps
T834 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1183915130 Jul 10 06:14:54 PM PDT 24 Jul 10 06:15:00 PM PDT 24 390499907 ps
T835 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3095575836 Jul 10 06:14:31 PM PDT 24 Jul 10 06:14:42 PM PDT 24 8272184385 ps
T836 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3350841805 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:49 PM PDT 24 491060235 ps
T837 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1284823738 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:30 PM PDT 24 330705592 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1154271776 Jul 10 06:14:46 PM PDT 24 Jul 10 06:14:55 PM PDT 24 8308444786 ps
T839 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1035432827 Jul 10 06:14:59 PM PDT 24 Jul 10 06:15:05 PM PDT 24 319683048 ps
T840 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3976892705 Jul 10 06:14:32 PM PDT 24 Jul 10 06:14:38 PM PDT 24 447955493 ps
T841 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4140320271 Jul 10 06:14:27 PM PDT 24 Jul 10 06:14:34 PM PDT 24 331085569 ps
T842 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.302292294 Jul 10 06:14:59 PM PDT 24 Jul 10 06:15:05 PM PDT 24 354324551 ps
T843 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1490138144 Jul 10 06:14:37 PM PDT 24 Jul 10 06:14:40 PM PDT 24 603858058 ps
T844 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4293279098 Jul 10 06:14:01 PM PDT 24 Jul 10 06:15:17 PM PDT 24 52952234280 ps
T845 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.783552683 Jul 10 06:14:02 PM PDT 24 Jul 10 06:14:08 PM PDT 24 510753184 ps
T337 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2538564729 Jul 10 06:14:44 PM PDT 24 Jul 10 06:14:57 PM PDT 24 4178964300 ps
T846 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3582619732 Jul 10 06:14:56 PM PDT 24 Jul 10 06:15:01 PM PDT 24 499948701 ps
T847 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1364910983 Jul 10 06:14:26 PM PDT 24 Jul 10 06:14:32 PM PDT 24 500196875 ps
T123 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.840827520 Jul 10 06:14:00 PM PDT 24 Jul 10 06:14:05 PM PDT 24 1060583832 ps
T848 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2990206037 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:33 PM PDT 24 4220832747 ps
T849 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1629239214 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:55 PM PDT 24 343680261 ps
T850 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.682087385 Jul 10 06:14:55 PM PDT 24 Jul 10 06:15:00 PM PDT 24 329275705 ps
T851 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2190516147 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:51 PM PDT 24 534549815 ps
T125 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1734495497 Jul 10 06:14:51 PM PDT 24 Jul 10 06:14:55 PM PDT 24 464512269 ps
T852 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1682314491 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:52 PM PDT 24 570618444 ps
T853 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3134875101 Jul 10 06:14:51 PM PDT 24 Jul 10 06:14:55 PM PDT 24 386406681 ps
T126 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3074092097 Jul 10 06:14:18 PM PDT 24 Jul 10 06:14:24 PM PDT 24 870702357 ps
T854 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1690920298 Jul 10 06:14:37 PM PDT 24 Jul 10 06:14:40 PM PDT 24 475345635 ps
T855 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1095739702 Jul 10 06:14:41 PM PDT 24 Jul 10 06:14:44 PM PDT 24 404026281 ps
T856 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3991520544 Jul 10 06:14:37 PM PDT 24 Jul 10 06:14:41 PM PDT 24 365148134 ps
T857 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1943382853 Jul 10 06:15:05 PM PDT 24 Jul 10 06:15:10 PM PDT 24 397852763 ps
T858 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3571719170 Jul 10 06:14:57 PM PDT 24 Jul 10 06:15:03 PM PDT 24 430828508 ps
T859 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1464718281 Jul 10 06:14:25 PM PDT 24 Jul 10 06:14:31 PM PDT 24 454422267 ps
T860 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3894807754 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:52 PM PDT 24 526370699 ps
T861 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2841673983 Jul 10 06:14:16 PM PDT 24 Jul 10 06:14:29 PM PDT 24 2361656825 ps
T862 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.857738447 Jul 10 06:14:40 PM PDT 24 Jul 10 06:14:43 PM PDT 24 366700441 ps
T863 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1937495261 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:55 PM PDT 24 468187647 ps
T864 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.146345035 Jul 10 06:14:31 PM PDT 24 Jul 10 06:14:37 PM PDT 24 515079719 ps
T865 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1198505480 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:55 PM PDT 24 422983221 ps
T866 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2932593618 Jul 10 06:14:30 PM PDT 24 Jul 10 06:14:47 PM PDT 24 4251062317 ps
T127 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.705352044 Jul 10 06:14:04 PM PDT 24 Jul 10 06:14:17 PM PDT 24 1193574214 ps
T867 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4036101004 Jul 10 06:14:48 PM PDT 24 Jul 10 06:14:51 PM PDT 24 403020059 ps
T868 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.259430653 Jul 10 06:14:58 PM PDT 24 Jul 10 06:15:03 PM PDT 24 378183894 ps
T869 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2259218052 Jul 10 06:14:03 PM PDT 24 Jul 10 06:14:17 PM PDT 24 2115246701 ps
T870 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.82700869 Jul 10 06:14:11 PM PDT 24 Jul 10 06:14:17 PM PDT 24 373220071 ps
T871 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3565562900 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:30 PM PDT 24 473571361 ps
T872 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4099101487 Jul 10 06:14:45 PM PDT 24 Jul 10 06:14:49 PM PDT 24 559825932 ps
T128 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3001769730 Jul 10 06:14:35 PM PDT 24 Jul 10 06:14:38 PM PDT 24 441732201 ps
T873 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.295856327 Jul 10 06:14:55 PM PDT 24 Jul 10 06:15:01 PM PDT 24 285803248 ps
T874 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3844532668 Jul 10 06:14:04 PM PDT 24 Jul 10 06:14:13 PM PDT 24 1292264544 ps
T875 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3983340604 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:55 PM PDT 24 2896146135 ps
T876 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1044268860 Jul 10 06:14:25 PM PDT 24 Jul 10 06:14:32 PM PDT 24 461025647 ps
T877 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2802747327 Jul 10 06:14:50 PM PDT 24 Jul 10 06:14:55 PM PDT 24 361756044 ps
T878 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.986261031 Jul 10 06:14:07 PM PDT 24 Jul 10 06:14:15 PM PDT 24 526987369 ps
T879 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3525589821 Jul 10 06:14:52 PM PDT 24 Jul 10 06:14:56 PM PDT 24 279161368 ps
T880 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3129650277 Jul 10 06:15:01 PM PDT 24 Jul 10 06:15:06 PM PDT 24 304050421 ps
T881 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1728028025 Jul 10 06:14:38 PM PDT 24 Jul 10 06:14:55 PM PDT 24 4123332939 ps
T882 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1108830827 Jul 10 06:14:01 PM PDT 24 Jul 10 06:14:07 PM PDT 24 638337869 ps
T334 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.627243793 Jul 10 06:14:51 PM PDT 24 Jul 10 06:15:05 PM PDT 24 4698554624 ps
T883 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.615206356 Jul 10 06:14:42 PM PDT 24 Jul 10 06:14:50 PM PDT 24 8090285091 ps
T75 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.612339061 Jul 10 06:14:20 PM PDT 24 Jul 10 06:14:31 PM PDT 24 8561629036 ps
T884 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3189719139 Jul 10 06:14:26 PM PDT 24 Jul 10 06:14:37 PM PDT 24 8316418570 ps
T885 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1945621439 Jul 10 06:13:59 PM PDT 24 Jul 10 06:14:07 PM PDT 24 4462912385 ps
T886 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.903557496 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:31 PM PDT 24 427878538 ps
T887 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1315739506 Jul 10 06:14:52 PM PDT 24 Jul 10 06:14:57 PM PDT 24 452823074 ps
T888 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.108499686 Jul 10 06:14:32 PM PDT 24 Jul 10 06:14:36 PM PDT 24 402858321 ps
T889 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3791781269 Jul 10 06:14:39 PM PDT 24 Jul 10 06:14:44 PM PDT 24 579359687 ps
T890 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3380062432 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:29 PM PDT 24 511342785 ps
T335 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.357938721 Jul 10 06:14:14 PM PDT 24 Jul 10 06:14:21 PM PDT 24 4527978792 ps
T891 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.897167815 Jul 10 06:14:17 PM PDT 24 Jul 10 06:14:22 PM PDT 24 382397567 ps
T892 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.817645693 Jul 10 06:15:05 PM PDT 24 Jul 10 06:15:10 PM PDT 24 527676958 ps
T893 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3726755563 Jul 10 06:14:18 PM PDT 24 Jul 10 06:14:35 PM PDT 24 8705416445 ps
T894 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1049519504 Jul 10 06:14:34 PM PDT 24 Jul 10 06:14:39 PM PDT 24 529780889 ps
T895 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2872026755 Jul 10 06:14:47 PM PDT 24 Jul 10 06:15:10 PM PDT 24 8364381478 ps
T896 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3649006655 Jul 10 06:14:14 PM PDT 24 Jul 10 06:14:19 PM PDT 24 324169172 ps
T897 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.857905779 Jul 10 06:14:24 PM PDT 24 Jul 10 06:14:29 PM PDT 24 468900227 ps
T898 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.188064434 Jul 10 06:14:52 PM PDT 24 Jul 10 06:15:04 PM PDT 24 4465007273 ps
T899 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2004904802 Jul 10 06:14:47 PM PDT 24 Jul 10 06:14:50 PM PDT 24 841036895 ps
T900 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1245476138 Jul 10 06:14:53 PM PDT 24 Jul 10 06:14:57 PM PDT 24 353660923 ps
T901 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4157454182 Jul 10 06:14:04 PM PDT 24 Jul 10 06:14:13 PM PDT 24 525019885 ps
T902 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3403627462 Jul 10 06:14:46 PM PDT 24 Jul 10 06:14:49 PM PDT 24 448965738 ps
T903 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.992597431 Jul 10 06:14:22 PM PDT 24 Jul 10 06:14:30 PM PDT 24 482290734 ps
T904 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2690681274 Jul 10 06:14:55 PM PDT 24 Jul 10 06:15:00 PM PDT 24 441994453 ps
T905 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3839843638 Jul 10 06:14:10 PM PDT 24 Jul 10 06:14:21 PM PDT 24 2511464287 ps
T906 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2938958911 Jul 10 06:14:52 PM PDT 24 Jul 10 06:14:57 PM PDT 24 327531284 ps
T907 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3278604621 Jul 10 06:14:38 PM PDT 24 Jul 10 06:14:40 PM PDT 24 357174436 ps
T908 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.638687943 Jul 10 06:14:42 PM PDT 24 Jul 10 06:14:45 PM PDT 24 589899966 ps
T909 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3448864357 Jul 10 06:14:03 PM PDT 24 Jul 10 06:14:11 PM PDT 24 428988430 ps
T910 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2077627822 Jul 10 06:14:39 PM PDT 24 Jul 10 06:14:52 PM PDT 24 5023347291 ps
T911 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.553061987 Jul 10 06:14:13 PM PDT 24 Jul 10 06:14:24 PM PDT 24 4597751636 ps
T912 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2631306892 Jul 10 06:14:11 PM PDT 24 Jul 10 06:14:17 PM PDT 24 553048360 ps
T913 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.300994225 Jul 10 06:14:15 PM PDT 24 Jul 10 06:14:20 PM PDT 24 558301077 ps
T914 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1747632128 Jul 10 06:14:12 PM PDT 24 Jul 10 06:14:19 PM PDT 24 906864069 ps
T915 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1676395800 Jul 10 06:14:01 PM PDT 24 Jul 10 06:14:30 PM PDT 24 33660699758 ps
T916 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4201855451 Jul 10 06:14:27 PM PDT 24 Jul 10 06:14:35 PM PDT 24 2306841844 ps
T917 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2042680455 Jul 10 06:14:49 PM PDT 24 Jul 10 06:14:53 PM PDT 24 2232347267 ps
T918 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.653913981 Jul 10 06:14:57 PM PDT 24 Jul 10 06:15:03 PM PDT 24 505821323 ps
T919 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3324345226 Jul 10 06:14:05 PM PDT 24 Jul 10 06:14:13 PM PDT 24 354091678 ps
T76 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.130064530 Jul 10 06:14:07 PM PDT 24 Jul 10 06:14:37 PM PDT 24 8722348198 ps

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.1379894065
Short name T7
Test name
Test status
Simulation time 519435344071 ps
CPU time 1199.27 seconds
Started Jul 10 06:17:25 PM PDT 24
Finished Jul 10 06:37:25 PM PDT 24
Peak memory 201932 kb
Host smart-e10b3555-941c-4953-9fb3-1029e767c31d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379894065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.1379894065
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.574047814
Short name T47
Test name
Test status
Simulation time 483694250340 ps
CPU time 594.51 seconds
Started Jul 10 06:17:15 PM PDT 24
Finished Jul 10 06:27:10 PM PDT 24
Peak memory 218428 kb
Host smart-942329e0-b832-473f-b665-6cc9799876a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574047814 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.574047814
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.735980582
Short name T17
Test name
Test status
Simulation time 737317458877 ps
CPU time 663.17 seconds
Started Jul 10 06:17:24 PM PDT 24
Finished Jul 10 06:28:28 PM PDT 24
Peak memory 210536 kb
Host smart-dea4d5af-7fdc-47d5-a90f-37b299e32998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735980582 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.735980582
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.1102424164
Short name T53
Test name
Test status
Simulation time 531472934969 ps
CPU time 1245.45 seconds
Started Jul 10 06:18:28 PM PDT 24
Finished Jul 10 06:39:14 PM PDT 24
Peak memory 201976 kb
Host smart-623ea66c-9118-4d8e-a344-953a1aa9d8c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102424164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.1102424164
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.249969538
Short name T83
Test name
Test status
Simulation time 544586074917 ps
CPU time 58.26 seconds
Started Jul 10 06:16:03 PM PDT 24
Finished Jul 10 06:17:03 PM PDT 24
Peak memory 201880 kb
Host smart-4e233df4-ad03-4de4-a496-c4f8a06d5c53
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249969538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.249969538
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.3931126631
Short name T32
Test name
Test status
Simulation time 216074203765 ps
CPU time 227.23 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:19:49 PM PDT 24
Peak memory 210524 kb
Host smart-8e2e9d94-bf26-4a4f-9818-2f4eee282862
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931126631 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.3931126631
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.3862032453
Short name T89
Test name
Test status
Simulation time 208512223776 ps
CPU time 352.32 seconds
Started Jul 10 06:15:25 PM PDT 24
Finished Jul 10 06:21:19 PM PDT 24
Peak memory 211540 kb
Host smart-94f662fd-0cfe-4b70-a137-26c795091cfe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862032453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.3862032453
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2081823919
Short name T52
Test name
Test status
Simulation time 509024919415 ps
CPU time 573.76 seconds
Started Jul 10 06:15:22 PM PDT 24
Finished Jul 10 06:24:58 PM PDT 24
Peak memory 201888 kb
Host smart-c7e0ce2b-1e3a-4136-b7c8-d16e24efb555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081823919 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2081823919
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.3085973922
Short name T149
Test name
Test status
Simulation time 493507613226 ps
CPU time 1120.05 seconds
Started Jul 10 06:16:22 PM PDT 24
Finished Jul 10 06:35:03 PM PDT 24
Peak memory 201908 kb
Host smart-1beb539e-2dcc-4c18-b49c-b2f10637e497
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085973922 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.3085973922
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.2242896924
Short name T164
Test name
Test status
Simulation time 502379707609 ps
CPU time 286.46 seconds
Started Jul 10 06:17:25 PM PDT 24
Finished Jul 10 06:22:12 PM PDT 24
Peak memory 201948 kb
Host smart-5562c278-114a-4364-86a7-f2765d2bc887
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242896924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.2242896924
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.320954582
Short name T139
Test name
Test status
Simulation time 511036219405 ps
CPU time 248.76 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:20:28 PM PDT 24
Peak memory 201968 kb
Host smart-734719b9-3864-4f0b-86e8-d3aef5633fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320954582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.320954582
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.1544419624
Short name T68
Test name
Test status
Simulation time 8162960608 ps
CPU time 20.06 seconds
Started Jul 10 06:15:26 PM PDT 24
Finished Jul 10 06:15:47 PM PDT 24
Peak memory 218092 kb
Host smart-1dc489a2-7ed0-4f57-ab52-2cb871c6342f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544419624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.1544419624
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.2336821583
Short name T13
Test name
Test status
Simulation time 537848627292 ps
CPU time 216.46 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:19:43 PM PDT 24
Peak memory 201972 kb
Host smart-455d8a0d-46f9-48c0-9d3d-152dd13acb0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336821583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.2336821583
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.1338826320
Short name T155
Test name
Test status
Simulation time 531459021113 ps
CPU time 162.16 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:18:28 PM PDT 24
Peak memory 201940 kb
Host smart-33f965e2-504c-4698-9c33-53b18335b872
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338826320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.1338826320
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.3876258921
Short name T21
Test name
Test status
Simulation time 441140125407 ps
CPU time 171.33 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:18:44 PM PDT 24
Peak memory 210280 kb
Host smart-8ec0a7c0-ea0d-4991-a555-d5286a361893
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876258921 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.3876258921
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.2002329967
Short name T120
Test name
Test status
Simulation time 513240692 ps
CPU time 1.8 seconds
Started Jul 10 06:14:46 PM PDT 24
Finished Jul 10 06:14:50 PM PDT 24
Peak memory 201476 kb
Host smart-3fc8986e-f745-48c6-9426-431db71b8358
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002329967 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.2002329967
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.910725885
Short name T229
Test name
Test status
Simulation time 559573211055 ps
CPU time 234.51 seconds
Started Jul 10 06:18:26 PM PDT 24
Finished Jul 10 06:22:21 PM PDT 24
Peak memory 201916 kb
Host smart-0dfa405f-509a-4226-9356-62c6288c3634
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910725885 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_
wakeup.910725885
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2719667853
Short name T73
Test name
Test status
Simulation time 499520507 ps
CPU time 2.77 seconds
Started Jul 10 06:14:01 PM PDT 24
Finished Jul 10 06:14:09 PM PDT 24
Peak memory 201732 kb
Host smart-f3506440-b2b7-4e98-a764-4f68d3e49447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719667853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2719667853
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.912698322
Short name T171
Test name
Test status
Simulation time 496738536081 ps
CPU time 92.23 seconds
Started Jul 10 06:17:56 PM PDT 24
Finished Jul 10 06:19:29 PM PDT 24
Peak memory 201948 kb
Host smart-2aeb7e58-56f8-4e2d-b6a8-029c3caf2305
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912698322 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gati
ng.912698322
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.486126726
Short name T265
Test name
Test status
Simulation time 513298338180 ps
CPU time 304.52 seconds
Started Jul 10 06:15:55 PM PDT 24
Finished Jul 10 06:21:02 PM PDT 24
Peak memory 201960 kb
Host smart-cd8be137-8109-4989-990b-8f6170dbac8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486126726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gati
ng.486126726
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.3653338877
Short name T137
Test name
Test status
Simulation time 492559335765 ps
CPU time 221.69 seconds
Started Jul 10 06:17:26 PM PDT 24
Finished Jul 10 06:21:08 PM PDT 24
Peak memory 201892 kb
Host smart-a055f80f-53a6-4287-bbc6-cea80c1b0df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653338877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.3653338877
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.1646443228
Short name T48
Test name
Test status
Simulation time 103653911373 ps
CPU time 208.93 seconds
Started Jul 10 06:15:39 PM PDT 24
Finished Jul 10 06:19:11 PM PDT 24
Peak memory 218392 kb
Host smart-1ad61961-86d4-498b-949e-3c16ae8e359b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646443228 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.1646443228
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.1258966792
Short name T148
Test name
Test status
Simulation time 526574947517 ps
CPU time 155.04 seconds
Started Jul 10 06:19:14 PM PDT 24
Finished Jul 10 06:21:50 PM PDT 24
Peak memory 201964 kb
Host smart-340ff05c-6137-4234-bc42-dadf78563290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1258966792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.1258966792
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.815019326
Short name T234
Test name
Test status
Simulation time 492125794619 ps
CPU time 551.43 seconds
Started Jul 10 06:17:36 PM PDT 24
Finished Jul 10 06:26:48 PM PDT 24
Peak memory 201948 kb
Host smart-f128bb34-6e73-45c6-8a99-52b7415a1138
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815019326 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gati
ng.815019326
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.77409316
Short name T321
Test name
Test status
Simulation time 520527626353 ps
CPU time 85.68 seconds
Started Jul 10 06:18:17 PM PDT 24
Finished Jul 10 06:19:43 PM PDT 24
Peak memory 201872 kb
Host smart-f30da0f0-9a97-4164-8986-5ddc855f4e41
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77409316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gatin
g.77409316
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3415335283
Short name T85
Test name
Test status
Simulation time 493722132239 ps
CPU time 288.33 seconds
Started Jul 10 06:15:42 PM PDT 24
Finished Jul 10 06:20:33 PM PDT 24
Peak memory 201888 kb
Host smart-00064cca-797c-4b1f-8015-3a1f5380214e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415335283 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3415335283
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2636372818
Short name T246
Test name
Test status
Simulation time 509678217730 ps
CPU time 283.82 seconds
Started Jul 10 06:16:17 PM PDT 24
Finished Jul 10 06:21:03 PM PDT 24
Peak memory 201944 kb
Host smart-210a5739-6e21-41ef-8ac8-a07282a09c31
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636372818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2636372818
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1555417138
Short name T88
Test name
Test status
Simulation time 180581885265 ps
CPU time 102.43 seconds
Started Jul 10 06:16:41 PM PDT 24
Finished Jul 10 06:18:25 PM PDT 24
Peak memory 210188 kb
Host smart-37ba4617-e2bf-43fb-8fb1-c8a48f8ce962
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555417138 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1555417138
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.1780672432
Short name T8
Test name
Test status
Simulation time 633647437367 ps
CPU time 385.11 seconds
Started Jul 10 06:15:21 PM PDT 24
Finished Jul 10 06:21:48 PM PDT 24
Peak memory 201608 kb
Host smart-cd43bbd4-35ae-4db2-a856-a3d6e69956a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780672432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.1780672432
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.602230391
Short name T348
Test name
Test status
Simulation time 356566669 ps
CPU time 1.11 seconds
Started Jul 10 06:15:23 PM PDT 24
Finished Jul 10 06:15:26 PM PDT 24
Peak memory 201656 kb
Host smart-b13f4c2c-6a0d-49d5-a8f3-a37ac75fff90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602230391 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.602230391
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1154405308
Short name T14
Test name
Test status
Simulation time 351714558520 ps
CPU time 194.48 seconds
Started Jul 10 06:17:14 PM PDT 24
Finished Jul 10 06:20:29 PM PDT 24
Peak memory 201952 kb
Host smart-f77458be-53d9-47ff-993e-d034bd824ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154405308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1154405308
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3268160846
Short name T64
Test name
Test status
Simulation time 8871928495 ps
CPU time 7.28 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:58 PM PDT 24
Peak memory 201800 kb
Host smart-4bc0f90a-af40-4345-984a-96537c40a566
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3268160846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3268160846
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.1827404952
Short name T300
Test name
Test status
Simulation time 423323749343 ps
CPU time 225.05 seconds
Started Jul 10 06:19:53 PM PDT 24
Finished Jul 10 06:23:38 PM PDT 24
Peak memory 210244 kb
Host smart-cad4e504-ad90-4e1b-828e-a242c89753ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827404952 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.1827404952
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1731375573
Short name T22
Test name
Test status
Simulation time 126177275233 ps
CPU time 108.31 seconds
Started Jul 10 06:17:00 PM PDT 24
Finished Jul 10 06:18:49 PM PDT 24
Peak memory 210524 kb
Host smart-0b359a0b-962e-4b34-88c2-e0de92e0b3e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731375573 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1731375573
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2930553006
Short name T116
Test name
Test status
Simulation time 1277073935 ps
CPU time 3.9 seconds
Started Jul 10 06:14:19 PM PDT 24
Finished Jul 10 06:14:27 PM PDT 24
Peak memory 201496 kb
Host smart-c948210e-649d-4c2b-8acd-623343d114d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930553006 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2930553006
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.3825531780
Short name T174
Test name
Test status
Simulation time 499044689580 ps
CPU time 131.39 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:18:03 PM PDT 24
Peak memory 201904 kb
Host smart-7a80c205-83fc-4f27-9e2d-50e97c9114fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825531780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.3825531780
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.1394704307
Short name T230
Test name
Test status
Simulation time 443231539846 ps
CPU time 929.17 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:31:31 PM PDT 24
Peak memory 201656 kb
Host smart-5fe295ab-ff9b-46f5-92d9-438c96917593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394704307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.1394704307
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.45570074
Short name T212
Test name
Test status
Simulation time 515056049762 ps
CPU time 1148.99 seconds
Started Jul 10 06:17:39 PM PDT 24
Finished Jul 10 06:36:49 PM PDT 24
Peak memory 201976 kb
Host smart-5da0d6ab-f840-4e11-b8be-cd1c34bff460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45570074 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.45570074
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.3862733829
Short name T203
Test name
Test status
Simulation time 1877631937929 ps
CPU time 4427.17 seconds
Started Jul 10 06:17:43 PM PDT 24
Finished Jul 10 07:31:31 PM PDT 24
Peak memory 212576 kb
Host smart-5da7d711-bcfe-4e15-88f9-1818ec239942
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862733829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all
.3862733829
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.80155707
Short name T305
Test name
Test status
Simulation time 368833029372 ps
CPU time 848.07 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:30:29 PM PDT 24
Peak memory 201784 kb
Host smart-77fdcafb-81a7-4681-b921-1ba18cf51469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80155707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.80155707
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.614775131
Short name T166
Test name
Test status
Simulation time 408051440314 ps
CPU time 1350.98 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:38:29 PM PDT 24
Peak memory 210416 kb
Host smart-73bc0f99-685b-4e41-8a00-804cc4c4f2e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614775131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all.
614775131
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.3814351835
Short name T244
Test name
Test status
Simulation time 516711218025 ps
CPU time 585.34 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:25:45 PM PDT 24
Peak memory 201820 kb
Host smart-09176c3f-7ce8-4e3b-8cf2-b284bc2516bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814351835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters
_wakeup.3814351835
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.78432390
Short name T262
Test name
Test status
Simulation time 357959686664 ps
CPU time 814.7 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:29:22 PM PDT 24
Peak memory 201904 kb
Host smart-9712912e-0b22-43df-8395-2d09bb3d3aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78432390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.78432390
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.2598992419
Short name T215
Test name
Test status
Simulation time 323307427344 ps
CPU time 172.52 seconds
Started Jul 10 06:15:19 PM PDT 24
Finished Jul 10 06:18:14 PM PDT 24
Peak memory 201908 kb
Host smart-97d1ef6b-4e1a-419f-891c-5241dddd68ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598992419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.2598992419
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1812132342
Short name T236
Test name
Test status
Simulation time 578681329259 ps
CPU time 463.53 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:23:40 PM PDT 24
Peak memory 201952 kb
Host smart-459fd774-70df-485b-8afc-2c0a5f2b1749
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812132342 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1812132342
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.3651187371
Short name T6
Test name
Test status
Simulation time 183763548358 ps
CPU time 54.3 seconds
Started Jul 10 06:15:52 PM PDT 24
Finished Jul 10 06:16:49 PM PDT 24
Peak memory 201920 kb
Host smart-41dd4687-0358-4e3b-a1aa-9eb66f5497ca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651187371 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.3651187371
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.1191433112
Short name T276
Test name
Test status
Simulation time 332629707937 ps
CPU time 169.8 seconds
Started Jul 10 06:16:33 PM PDT 24
Finished Jul 10 06:19:23 PM PDT 24
Peak memory 201916 kb
Host smart-23ab7f83-2f07-4419-a754-8dd09ec3e0c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191433112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.1191433112
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.2921824811
Short name T322
Test name
Test status
Simulation time 161246053481 ps
CPU time 92.28 seconds
Started Jul 10 06:18:17 PM PDT 24
Finished Jul 10 06:19:51 PM PDT 24
Peak memory 201896 kb
Host smart-f8f7d904-7620-4e2e-b2c6-b42ea138bfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921824811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.2921824811
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.2804600726
Short name T310
Test name
Test status
Simulation time 166355199493 ps
CPU time 367.29 seconds
Started Jul 10 06:15:34 PM PDT 24
Finished Jul 10 06:21:42 PM PDT 24
Peak memory 201936 kb
Host smart-ee5c873e-04fa-4ab4-a05a-16899fa4e30a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804600726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.2804600726
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.888773067
Short name T290
Test name
Test status
Simulation time 540160200811 ps
CPU time 763.44 seconds
Started Jul 10 06:16:12 PM PDT 24
Finished Jul 10 06:28:58 PM PDT 24
Peak memory 201900 kb
Host smart-b71f8794-05cc-41a2-9931-506e75c3cca4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888773067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.888773067
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.524373908
Short name T271
Test name
Test status
Simulation time 506783126692 ps
CPU time 1088.74 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:34:05 PM PDT 24
Peak memory 201924 kb
Host smart-c2b3f95b-7882-4513-bbd3-a2367a33c4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524373908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.524373908
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2421045558
Short name T256
Test name
Test status
Simulation time 393250852878 ps
CPU time 549.46 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:25:05 PM PDT 24
Peak memory 210388 kb
Host smart-e81b9ef3-00c9-4fef-be1a-89870deada48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421045558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2421045558
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.216803736
Short name T1
Test name
Test status
Simulation time 102022201512 ps
CPU time 377.34 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:22:17 PM PDT 24
Peak memory 202236 kb
Host smart-89360bdf-c2c6-46ac-833d-977c67c26498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216803736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.216803736
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.4190917099
Short name T224
Test name
Test status
Simulation time 528791703323 ps
CPU time 289.96 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:20:52 PM PDT 24
Peak memory 201768 kb
Host smart-a8250b64-0c3d-4449-ba32-c4eb88eedbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190917099 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.4190917099
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.1602071076
Short name T3
Test name
Test status
Simulation time 374831750821 ps
CPU time 879.41 seconds
Started Jul 10 06:16:36 PM PDT 24
Finished Jul 10 06:31:16 PM PDT 24
Peak memory 201924 kb
Host smart-aa8b84eb-b095-4d8d-86d0-5e0e19cab658
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602071076 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.1602071076
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1683549187
Short name T11
Test name
Test status
Simulation time 481551131844 ps
CPU time 637.35 seconds
Started Jul 10 06:15:21 PM PDT 24
Finished Jul 10 06:26:00 PM PDT 24
Peak memory 202256 kb
Host smart-8fec86de-adfe-47e2-9c6e-df9a4a5650c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683549187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1683549187
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2481427233
Short name T162
Test name
Test status
Simulation time 349951131814 ps
CPU time 807.97 seconds
Started Jul 10 06:17:48 PM PDT 24
Finished Jul 10 06:31:17 PM PDT 24
Peak memory 201880 kb
Host smart-9c6b4b1c-36e9-48b2-bc1a-ac3058306f3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481427233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2481427233
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.365523315
Short name T258
Test name
Test status
Simulation time 591061774036 ps
CPU time 1002.65 seconds
Started Jul 10 06:18:39 PM PDT 24
Finished Jul 10 06:35:23 PM PDT 24
Peak memory 202252 kb
Host smart-45aec9e3-4e15-40ab-b6d4-9df31f6f63a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365523315 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all.
365523315
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.3153302799
Short name T306
Test name
Test status
Simulation time 187166057147 ps
CPU time 422.82 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:22:56 PM PDT 24
Peak memory 211544 kb
Host smart-7c82a95a-0e64-4169-9339-d443e0596998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153302799 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.3153302799
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.1766521994
Short name T79
Test name
Test status
Simulation time 166482035210 ps
CPU time 162.1 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:18:34 PM PDT 24
Peak memory 201864 kb
Host smart-a0cf1951-ed01-44b9-9e6e-90d51d79214d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766521994 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.1766521994
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.2238052355
Short name T291
Test name
Test status
Simulation time 614091030319 ps
CPU time 1363.81 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:38:37 PM PDT 24
Peak memory 201896 kb
Host smart-9bdfa4f2-38cc-4995-9605-5c5bc06a7b7f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238052355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.2238052355
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.2392377056
Short name T225
Test name
Test status
Simulation time 327575577403 ps
CPU time 737.09 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:28:37 PM PDT 24
Peak memory 201844 kb
Host smart-b1e3ce55-b5c9-492d-9387-3fa17e242be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392377056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.2392377056
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.677223979
Short name T150
Test name
Test status
Simulation time 201488979773 ps
CPU time 473.52 seconds
Started Jul 10 06:15:23 PM PDT 24
Finished Jul 10 06:23:19 PM PDT 24
Peak memory 201904 kb
Host smart-b6c0435a-9dce-431d-87af-ae08f35e162f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677223979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_w
akeup.677223979
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2197253287
Short name T299
Test name
Test status
Simulation time 189378861500 ps
CPU time 85.31 seconds
Started Jul 10 06:18:49 PM PDT 24
Finished Jul 10 06:20:16 PM PDT 24
Peak memory 211236 kb
Host smart-9e7740f5-2447-476a-acdc-9542ed5863c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197253287 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2197253287
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.357938721
Short name T335
Test name
Test status
Simulation time 4527978792 ps
CPU time 3.79 seconds
Started Jul 10 06:14:14 PM PDT 24
Finished Jul 10 06:14:21 PM PDT 24
Peak memory 201868 kb
Host smart-b0c52590-cdd3-4739-af91-a4b84efc82f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357938721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.357938721
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.771650400
Short name T297
Test name
Test status
Simulation time 169210409556 ps
CPU time 403.09 seconds
Started Jul 10 06:15:30 PM PDT 24
Finished Jul 10 06:22:15 PM PDT 24
Peak memory 201892 kb
Host smart-5a9676a7-8650-47c9-8e02-2614018a66f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771650400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.771650400
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.4288511487
Short name T267
Test name
Test status
Simulation time 536978740764 ps
CPU time 1024.77 seconds
Started Jul 10 06:15:23 PM PDT 24
Finished Jul 10 06:32:29 PM PDT 24
Peak memory 201924 kb
Host smart-4f728f98-7b62-40ad-9113-d0df1a8a989f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288511487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_
wakeup.4288511487
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1605140672
Short name T303
Test name
Test status
Simulation time 629170720996 ps
CPU time 1348.3 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:38:45 PM PDT 24
Peak memory 201908 kb
Host smart-8d6f7769-c65f-4f6b-b1ff-7e0e46c1ddce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605140672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1605140672
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3477798551
Short name T213
Test name
Test status
Simulation time 486062679403 ps
CPU time 1155.86 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:35:22 PM PDT 24
Peak memory 201932 kb
Host smart-d5e638e0-75fa-4f80-b310-16e15ceffa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477798551 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3477798551
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.3610671279
Short name T194
Test name
Test status
Simulation time 109882823688 ps
CPU time 518.8 seconds
Started Jul 10 06:16:42 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 202136 kb
Host smart-55294b24-a5f7-4699-b77b-f69c8738a042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610671279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.3610671279
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.2894829308
Short name T207
Test name
Test status
Simulation time 123470206566 ps
CPU time 491.92 seconds
Started Jul 10 06:18:19 PM PDT 24
Finished Jul 10 06:26:31 PM PDT 24
Peak memory 202424 kb
Host smart-a4c51080-35a3-46f5-91ab-ec90988d65b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894829308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.2894829308
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.1364008195
Short name T270
Test name
Test status
Simulation time 286457945543 ps
CPU time 1017.86 seconds
Started Jul 10 06:19:02 PM PDT 24
Finished Jul 10 06:36:01 PM PDT 24
Peak memory 212668 kb
Host smart-7212c855-4ed4-4ee6-ad53-345fb6fb6b81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364008195 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.1364008195
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.1959299314
Short name T293
Test name
Test status
Simulation time 491625632814 ps
CPU time 580.51 seconds
Started Jul 10 06:19:41 PM PDT 24
Finished Jul 10 06:29:22 PM PDT 24
Peak memory 201836 kb
Host smart-e7d3f29a-bfd0-4adb-8845-e5b84d13cf3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959299314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gat
ing.1959299314
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1871114682
Short name T27
Test name
Test status
Simulation time 163189814869 ps
CPU time 350.85 seconds
Started Jul 10 06:19:47 PM PDT 24
Finished Jul 10 06:25:39 PM PDT 24
Peak memory 201960 kb
Host smart-f4b503b3-acc1-41a1-afca-dc1462549526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871114682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1871114682
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.1530319730
Short name T235
Test name
Test status
Simulation time 172102984231 ps
CPU time 99.36 seconds
Started Jul 10 06:15:40 PM PDT 24
Finished Jul 10 06:17:22 PM PDT 24
Peak memory 201904 kb
Host smart-7393abc0-c1b0-4425-826a-3ed091a94424
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530319730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.1530319730
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.1411853461
Short name T72
Test name
Test status
Simulation time 346589646 ps
CPU time 1.28 seconds
Started Jul 10 06:14:32 PM PDT 24
Finished Jul 10 06:14:36 PM PDT 24
Peak memory 201772 kb
Host smart-da9e151c-7fcd-4adf-8078-a18196ef6e62
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411853461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.1411853461
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.502672209
Short name T184
Test name
Test status
Simulation time 186548883479 ps
CPU time 195.64 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:19:04 PM PDT 24
Peak memory 201960 kb
Host smart-7bbd7e27-ee14-4dc6-9e6a-0e6b2c904196
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502672209 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_
wakeup.502672209
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.1569787339
Short name T282
Test name
Test status
Simulation time 512133538546 ps
CPU time 1097.81 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:34:19 PM PDT 24
Peak memory 201800 kb
Host smart-0ec9660b-5b50-4121-9217-8f372065f9a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569787339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.1569787339
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3130211110
Short name T254
Test name
Test status
Simulation time 518820516728 ps
CPU time 1226.09 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:36:27 PM PDT 24
Peak memory 201940 kb
Host smart-12c3a84a-9316-48cf-8847-f1891a81d831
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130211110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3130211110
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.1354527695
Short name T781
Test name
Test status
Simulation time 333420848709 ps
CPU time 632.26 seconds
Started Jul 10 06:16:21 PM PDT 24
Finished Jul 10 06:26:54 PM PDT 24
Peak memory 201908 kb
Host smart-5a4b1d13-cc91-4fa3-852d-4768c8dbcd0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354527695 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.1354527695
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.492292779
Short name T19
Test name
Test status
Simulation time 140859721123 ps
CPU time 284.33 seconds
Started Jul 10 06:16:39 PM PDT 24
Finished Jul 10 06:21:24 PM PDT 24
Peak memory 218748 kb
Host smart-6d8182ff-36f5-4c79-a5ca-5d943db7f977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492292779 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.492292779
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.3435994010
Short name T214
Test name
Test status
Simulation time 485379715740 ps
CPU time 1101.37 seconds
Started Jul 10 06:17:25 PM PDT 24
Finished Jul 10 06:35:47 PM PDT 24
Peak memory 201912 kb
Host smart-7a28205a-1bb0-4dba-9b62-e16bffc65704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435994010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.3435994010
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.962623918
Short name T206
Test name
Test status
Simulation time 116001129450 ps
CPU time 437.43 seconds
Started Jul 10 06:18:49 PM PDT 24
Finished Jul 10 06:26:07 PM PDT 24
Peak memory 202256 kb
Host smart-75f4cd78-b0dd-42d9-8c46-663ea4696f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962623918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.962623918
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.865493478
Short name T153
Test name
Test status
Simulation time 341350545810 ps
CPU time 86.98 seconds
Started Jul 10 06:19:05 PM PDT 24
Finished Jul 10 06:20:33 PM PDT 24
Peak memory 201980 kb
Host smart-6e57123a-c5d3-49a4-96b2-6b91f5dde9b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865493478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.865493478
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.403629101
Short name T309
Test name
Test status
Simulation time 350760639062 ps
CPU time 806.04 seconds
Started Jul 10 06:19:30 PM PDT 24
Finished Jul 10 06:32:57 PM PDT 24
Peak memory 201936 kb
Host smart-31cd6b2a-a9f7-41da-b8bd-f39b185693e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403629101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.403629101
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1747632128
Short name T914
Test name
Test status
Simulation time 906864069 ps
CPU time 2.75 seconds
Started Jul 10 06:14:12 PM PDT 24
Finished Jul 10 06:14:19 PM PDT 24
Peak memory 201656 kb
Host smart-8c0374ae-122f-41d0-8b9c-de32fa24e455
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747632128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1747632128
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.1271977795
Short name T119
Test name
Test status
Simulation time 26886401963 ps
CPU time 57.16 seconds
Started Jul 10 06:14:03 PM PDT 24
Finished Jul 10 06:15:07 PM PDT 24
Peak memory 201876 kb
Host smart-26f7a5af-8d97-4406-b702-7f2a2e1ff94a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271977795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_
bash.1271977795
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.3380062432
Short name T890
Test name
Test status
Simulation time 511342785 ps
CPU time 1.18 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:29 PM PDT 24
Peak memory 201048 kb
Host smart-259c24e5-b90c-41c0-8405-139242896f1b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380062432 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.3380062432
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.3649006655
Short name T896
Test name
Test status
Simulation time 324169172 ps
CPU time 1.45 seconds
Started Jul 10 06:14:14 PM PDT 24
Finished Jul 10 06:14:19 PM PDT 24
Peak memory 201496 kb
Host smart-c6c7f263-9a06-4781-8c52-65138fb3ea64
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649006655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.3649006655
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.857905779
Short name T897
Test name
Test status
Simulation time 468900227 ps
CPU time 0.68 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:29 PM PDT 24
Peak memory 200884 kb
Host smart-e4ce5dd0-8387-4487-a113-2a2b572d480e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857905779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.857905779
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.247073617
Short name T133
Test name
Test status
Simulation time 5289623611 ps
CPU time 7.02 seconds
Started Jul 10 06:14:03 PM PDT 24
Finished Jul 10 06:14:16 PM PDT 24
Peak memory 201812 kb
Host smart-3994f675-956d-42f5-911c-9e770c83a773
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247073617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ct
rl_same_csr_outstanding.247073617
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.3448864357
Short name T909
Test name
Test status
Simulation time 428988430 ps
CPU time 1.94 seconds
Started Jul 10 06:14:03 PM PDT 24
Finished Jul 10 06:14:11 PM PDT 24
Peak memory 201496 kb
Host smart-8f1ba51a-ce2d-47a2-8862-c2b3232d4c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448864357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.3448864357
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.4278063718
Short name T114
Test name
Test status
Simulation time 1969466760 ps
CPU time 2.65 seconds
Started Jul 10 06:14:00 PM PDT 24
Finished Jul 10 06:14:08 PM PDT 24
Peak memory 201732 kb
Host smart-1355fe04-68d4-43a7-a8e9-a7746586df5e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278063718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.4278063718
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.4293279098
Short name T844
Test name
Test status
Simulation time 52952234280 ps
CPU time 70.33 seconds
Started Jul 10 06:14:01 PM PDT 24
Finished Jul 10 06:15:17 PM PDT 24
Peak memory 201828 kb
Host smart-fb3ff276-7f53-4c5f-8d23-b7ec1867ef78
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293279098 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.4293279098
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.840827520
Short name T123
Test name
Test status
Simulation time 1060583832 ps
CPU time 1.31 seconds
Started Jul 10 06:14:00 PM PDT 24
Finished Jul 10 06:14:05 PM PDT 24
Peak memory 201504 kb
Host smart-337e2026-78ae-46a8-9ce7-6c65f1af9ddb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840827520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_re
set.840827520
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1213972233
Short name T810
Test name
Test status
Simulation time 439854074 ps
CPU time 1.91 seconds
Started Jul 10 06:14:01 PM PDT 24
Finished Jul 10 06:14:09 PM PDT 24
Peak memory 201544 kb
Host smart-1ae6c89a-0d5d-43a1-a6ca-9a140ed2b27e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213972233 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1213972233
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.2631306892
Short name T912
Test name
Test status
Simulation time 553048360 ps
CPU time 1.14 seconds
Started Jul 10 06:14:11 PM PDT 24
Finished Jul 10 06:14:17 PM PDT 24
Peak memory 201508 kb
Host smart-63ef0c19-a8d2-4095-aa4a-5ff24176cfa8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631306892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.2631306892
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.783552683
Short name T845
Test name
Test status
Simulation time 510753184 ps
CPU time 0.76 seconds
Started Jul 10 06:14:02 PM PDT 24
Finished Jul 10 06:14:08 PM PDT 24
Peak memory 201432 kb
Host smart-4c634507-71f6-4b4a-8a8d-1396a136a51d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783552683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.783552683
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.2259218052
Short name T869
Test name
Test status
Simulation time 2115246701 ps
CPU time 8.39 seconds
Started Jul 10 06:14:03 PM PDT 24
Finished Jul 10 06:14:17 PM PDT 24
Peak memory 201504 kb
Host smart-81718dd5-b7e5-4a7a-b517-207ef29c2883
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259218052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.2259218052
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.1108830827
Short name T882
Test name
Test status
Simulation time 638337869 ps
CPU time 1.72 seconds
Started Jul 10 06:14:01 PM PDT 24
Finished Jul 10 06:14:07 PM PDT 24
Peak memory 201800 kb
Host smart-23499d7d-d7e1-406b-bb5b-dc404593a239
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108830827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.1108830827
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.1945621439
Short name T885
Test name
Test status
Simulation time 4462912385 ps
CPU time 4.08 seconds
Started Jul 10 06:13:59 PM PDT 24
Finished Jul 10 06:14:07 PM PDT 24
Peak memory 201812 kb
Host smart-a9e0da78-046e-49e5-be9c-eae36cb9ff3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945621439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.1945621439
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.1490138144
Short name T843
Test name
Test status
Simulation time 603858058 ps
CPU time 1.9 seconds
Started Jul 10 06:14:37 PM PDT 24
Finished Jul 10 06:14:40 PM PDT 24
Peak memory 201576 kb
Host smart-500aad4f-67da-4563-b165-ce99f0eec12e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490138144 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.1490138144
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.1496795328
Short name T124
Test name
Test status
Simulation time 388580023 ps
CPU time 1.63 seconds
Started Jul 10 06:14:35 PM PDT 24
Finished Jul 10 06:14:38 PM PDT 24
Peak memory 201504 kb
Host smart-43fed785-9c85-4b27-be83-99d8c2033a8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496795328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.1496795328
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.860355650
Short name T800
Test name
Test status
Simulation time 313976709 ps
CPU time 1 seconds
Started Jul 10 06:14:35 PM PDT 24
Finished Jul 10 06:14:37 PM PDT 24
Peak memory 201428 kb
Host smart-bf611d07-06c9-4bf0-b1e8-387c7205eff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860355650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.860355650
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.1728028025
Short name T881
Test name
Test status
Simulation time 4123332939 ps
CPU time 15.33 seconds
Started Jul 10 06:14:38 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201888 kb
Host smart-6abba306-97d4-4e14-8320-6100389f762b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728028025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.1728028025
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.3189719139
Short name T884
Test name
Test status
Simulation time 8316418570 ps
CPU time 6.52 seconds
Started Jul 10 06:14:26 PM PDT 24
Finished Jul 10 06:14:37 PM PDT 24
Peak memory 201844 kb
Host smart-f32122f3-7e3d-4304-8e75-d3cac388ce1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189719139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.3189719139
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.1710078153
Short name T811
Test name
Test status
Simulation time 388540397 ps
CPU time 1.16 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:52 PM PDT 24
Peak memory 201568 kb
Host smart-55768cc1-c390-45f1-a42c-b67bc4849590
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710078153 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.1710078153
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.857738447
Short name T862
Test name
Test status
Simulation time 366700441 ps
CPU time 1.04 seconds
Started Jul 10 06:14:40 PM PDT 24
Finished Jul 10 06:14:43 PM PDT 24
Peak memory 201504 kb
Host smart-c2f4677f-2fa1-4606-85b8-c4c451bd66e2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857738447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.857738447
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1275853381
Short name T802
Test name
Test status
Simulation time 494818765 ps
CPU time 1.85 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:53 PM PDT 24
Peak memory 201468 kb
Host smart-212351e6-a740-4fe8-8893-a6c55c754c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275853381 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1275853381
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.2475954999
Short name T829
Test name
Test status
Simulation time 2293872052 ps
CPU time 5.22 seconds
Started Jul 10 06:14:46 PM PDT 24
Finished Jul 10 06:14:52 PM PDT 24
Peak memory 201628 kb
Host smart-935fd6da-385a-4592-b1a0-46299a3b2140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475954999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.2475954999
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.3976892705
Short name T840
Test name
Test status
Simulation time 447955493 ps
CPU time 2.51 seconds
Started Jul 10 06:14:32 PM PDT 24
Finished Jul 10 06:14:38 PM PDT 24
Peak memory 202016 kb
Host smart-eafede9b-15c6-4463-9241-97507c17d3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976892705 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.3976892705
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.615206356
Short name T883
Test name
Test status
Simulation time 8090285091 ps
CPU time 6.17 seconds
Started Jul 10 06:14:42 PM PDT 24
Finished Jul 10 06:14:50 PM PDT 24
Peak memory 201844 kb
Host smart-398f9324-f53a-4f08-a833-b1ff7137bf39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615206356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_in
tg_err.615206356
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.1640189487
Short name T822
Test name
Test status
Simulation time 503588474 ps
CPU time 1.18 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:50 PM PDT 24
Peak memory 201572 kb
Host smart-4ee4e248-2a75-4788-aec2-68be30cb79eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640189487 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.1640189487
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.1734495497
Short name T125
Test name
Test status
Simulation time 464512269 ps
CPU time 1.01 seconds
Started Jul 10 06:14:51 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201504 kb
Host smart-18d95c67-f203-4ea9-a718-82efe7817343
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734495497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.1734495497
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.3134875101
Short name T853
Test name
Test status
Simulation time 386406681 ps
CPU time 0.8 seconds
Started Jul 10 06:14:51 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201476 kb
Host smart-2eb47c9b-c330-4db5-a242-4992ef612ae7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134875101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.3134875101
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.2077627822
Short name T910
Test name
Test status
Simulation time 5023347291 ps
CPU time 10.91 seconds
Started Jul 10 06:14:39 PM PDT 24
Finished Jul 10 06:14:52 PM PDT 24
Peak memory 201812 kb
Host smart-0dd9acee-4b31-405b-86fd-48b8e58cd0cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077627822 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.2077627822
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.2166756021
Short name T825
Test name
Test status
Simulation time 1021602950 ps
CPU time 2.57 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:53 PM PDT 24
Peak memory 218116 kb
Host smart-c3d92287-df95-43ff-946e-8298e5d4f28e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166756021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.2166756021
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.1364910983
Short name T847
Test name
Test status
Simulation time 500196875 ps
CPU time 1.15 seconds
Started Jul 10 06:14:26 PM PDT 24
Finished Jul 10 06:14:32 PM PDT 24
Peak memory 201624 kb
Host smart-6d9e8050-853a-4211-8b87-ba95333313c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364910983 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.1364910983
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.4138410429
Short name T801
Test name
Test status
Simulation time 399593717 ps
CPU time 0.88 seconds
Started Jul 10 06:14:42 PM PDT 24
Finished Jul 10 06:14:44 PM PDT 24
Peak memory 201428 kb
Host smart-74085596-2869-489c-ae76-07467c00e377
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138410429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.4138410429
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.825137089
Short name T823
Test name
Test status
Simulation time 2728056197 ps
CPU time 1.67 seconds
Started Jul 10 06:14:39 PM PDT 24
Finished Jul 10 06:14:43 PM PDT 24
Peak memory 201604 kb
Host smart-d9f589e6-1a2c-4c5c-95e6-1d15c148e307
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=825137089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_c
trl_same_csr_outstanding.825137089
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.4099101487
Short name T872
Test name
Test status
Simulation time 559825932 ps
CPU time 2.78 seconds
Started Jul 10 06:14:45 PM PDT 24
Finished Jul 10 06:14:49 PM PDT 24
Peak memory 201752 kb
Host smart-7903c351-6429-4fd8-bd96-eeb0c65ba44c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099101487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.4099101487
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3095575836
Short name T835
Test name
Test status
Simulation time 8272184385 ps
CPU time 7.21 seconds
Started Jul 10 06:14:31 PM PDT 24
Finished Jul 10 06:14:42 PM PDT 24
Peak memory 201812 kb
Host smart-c54a6dff-d09c-4fc3-94dc-5c0926337433
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095575836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3095575836
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.3991520544
Short name T856
Test name
Test status
Simulation time 365148134 ps
CPU time 1.36 seconds
Started Jul 10 06:14:37 PM PDT 24
Finished Jul 10 06:14:41 PM PDT 24
Peak memory 201576 kb
Host smart-e008a639-4b05-41d8-8d3e-475cbd648bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991520544 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.3991520544
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.638687943
Short name T908
Test name
Test status
Simulation time 589899966 ps
CPU time 1.17 seconds
Started Jul 10 06:14:42 PM PDT 24
Finished Jul 10 06:14:45 PM PDT 24
Peak memory 201500 kb
Host smart-50894b8f-101a-4dc0-b400-b091e3383b42
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638687943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.638687943
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.752007345
Short name T815
Test name
Test status
Simulation time 371907665 ps
CPU time 1.01 seconds
Started Jul 10 06:14:37 PM PDT 24
Finished Jul 10 06:14:39 PM PDT 24
Peak memory 201428 kb
Host smart-f179c262-a7fe-4c61-9bc0-0e14403e1922
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752007345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.752007345
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.931805268
Short name T131
Test name
Test status
Simulation time 2155777346 ps
CPU time 7.19 seconds
Started Jul 10 06:14:42 PM PDT 24
Finished Jul 10 06:14:51 PM PDT 24
Peak memory 201628 kb
Host smart-e4ec140a-d53a-418c-a70b-064b668b6c25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931805268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_c
trl_same_csr_outstanding.931805268
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.3791781269
Short name T889
Test name
Test status
Simulation time 579359687 ps
CPU time 2.81 seconds
Started Jul 10 06:14:39 PM PDT 24
Finished Jul 10 06:14:44 PM PDT 24
Peak memory 201796 kb
Host smart-0980b21d-7ccd-4548-b762-0e9184552257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791781269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.3791781269
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.1154271776
Short name T838
Test name
Test status
Simulation time 8308444786 ps
CPU time 7.2 seconds
Started Jul 10 06:14:46 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201844 kb
Host smart-74c30e35-3384-4f28-b527-9b110db51526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154271776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.1154271776
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1690920298
Short name T854
Test name
Test status
Simulation time 475345635 ps
CPU time 1.15 seconds
Started Jul 10 06:14:37 PM PDT 24
Finished Jul 10 06:14:40 PM PDT 24
Peak memory 201584 kb
Host smart-96e0413b-feb4-46da-ac22-017e27a83f98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690920298 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1690920298
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.2293218338
Short name T129
Test name
Test status
Simulation time 548739745 ps
CPU time 0.98 seconds
Started Jul 10 06:14:37 PM PDT 24
Finished Jul 10 06:14:40 PM PDT 24
Peak memory 201480 kb
Host smart-89059fe1-7ea8-413d-a0df-d1707da0df66
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293218338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.2293218338
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.3350841805
Short name T836
Test name
Test status
Simulation time 491060235 ps
CPU time 0.95 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:49 PM PDT 24
Peak memory 201428 kb
Host smart-1ee107f9-1cbd-43e3-a65c-a05f5aa70109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350841805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.3350841805
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.3842326482
Short name T130
Test name
Test status
Simulation time 4981597916 ps
CPU time 10.73 seconds
Started Jul 10 06:14:59 PM PDT 24
Finished Jul 10 06:15:14 PM PDT 24
Peak memory 201856 kb
Host smart-6240840e-bc83-4096-8d06-b3cf63df4754
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842326482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_
ctrl_same_csr_outstanding.3842326482
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.4254406519
Short name T812
Test name
Test status
Simulation time 591335739 ps
CPU time 2.76 seconds
Started Jul 10 06:14:38 PM PDT 24
Finished Jul 10 06:14:42 PM PDT 24
Peak memory 209940 kb
Host smart-3ab7bfd7-1201-4743-9ccc-2d642af469c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254406519 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.4254406519
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.3951410598
Short name T65
Test name
Test status
Simulation time 8344039601 ps
CPU time 7.71 seconds
Started Jul 10 06:14:42 PM PDT 24
Finished Jul 10 06:14:51 PM PDT 24
Peak memory 201812 kb
Host smart-e94e4cdb-0416-49e6-a026-0d56cdee3e7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951410598 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.3951410598
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.841265313
Short name T814
Test name
Test status
Simulation time 974077353 ps
CPU time 1.79 seconds
Started Jul 10 06:14:58 PM PDT 24
Finished Jul 10 06:15:04 PM PDT 24
Peak memory 201764 kb
Host smart-5ab99055-89ed-469f-9d45-7222fcc50356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841265313 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.841265313
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2004904802
Short name T899
Test name
Test status
Simulation time 841036895 ps
CPU time 0.9 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:50 PM PDT 24
Peak memory 201504 kb
Host smart-ea8c31fd-f6dd-4fd5-b848-e6366122e96b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004904802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2004904802
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.3525589821
Short name T879
Test name
Test status
Simulation time 279161368 ps
CPU time 1.27 seconds
Started Jul 10 06:14:52 PM PDT 24
Finished Jul 10 06:14:56 PM PDT 24
Peak memory 201376 kb
Host smart-d866c2c7-a7b0-43b7-b401-824ff300cf0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525589821 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.3525589821
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2042680455
Short name T917
Test name
Test status
Simulation time 2232347267 ps
CPU time 1.88 seconds
Started Jul 10 06:14:49 PM PDT 24
Finished Jul 10 06:14:53 PM PDT 24
Peak memory 201628 kb
Host smart-84fad7c0-9f21-4b2f-b1ab-410edec43ad6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042680455 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2042680455
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3068481917
Short name T90
Test name
Test status
Simulation time 895962136 ps
CPU time 2.59 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:56 PM PDT 24
Peak memory 209968 kb
Host smart-f51eaae7-6c9b-4a4e-96a3-565ea0d265bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068481917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3068481917
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.2872026755
Short name T895
Test name
Test status
Simulation time 8364381478 ps
CPU time 21.02 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:15:10 PM PDT 24
Peak memory 201824 kb
Host smart-a1dc7691-6454-402b-892f-c233eee0e25c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872026755 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_i
ntg_err.2872026755
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.1014173070
Short name T819
Test name
Test status
Simulation time 691917999 ps
CPU time 1.1 seconds
Started Jul 10 06:14:54 PM PDT 24
Finished Jul 10 06:14:59 PM PDT 24
Peak memory 201576 kb
Host smart-da30ae5b-80fe-4634-888b-afd5c511b1e5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014173070 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.1014173070
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1937495261
Short name T863
Test name
Test status
Simulation time 468187647 ps
CPU time 1.63 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201536 kb
Host smart-fb6083e2-ddf1-4a70-8643-a4f7bb07194c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937495261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1937495261
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.1198505480
Short name T865
Test name
Test status
Simulation time 422983221 ps
CPU time 1.62 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201432 kb
Host smart-25225065-ab7d-4348-ae4e-4904ff28b977
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198505480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.1198505480
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3983340604
Short name T875
Test name
Test status
Simulation time 2896146135 ps
CPU time 2.84 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201844 kb
Host smart-e2ad45cb-ea84-45ae-8d29-97e2c39bdd21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983340604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3983340604
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3031032231
Short name T66
Test name
Test status
Simulation time 467566381 ps
CPU time 3.74 seconds
Started Jul 10 06:14:49 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201836 kb
Host smart-514621fc-8953-4d85-8d8d-d3325e3b35e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031032231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3031032231
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.1002546378
Short name T67
Test name
Test status
Simulation time 4539624528 ps
CPU time 7.15 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:56 PM PDT 24
Peak memory 201824 kb
Host smart-6a58f85b-6aa4-4816-aca2-d6f7aa981704
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002546378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.1002546378
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.1682314491
Short name T852
Test name
Test status
Simulation time 570618444 ps
CPU time 1.47 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:52 PM PDT 24
Peak memory 201564 kb
Host smart-1147b7cf-25b9-4488-8e9b-212550f7c836
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682314491 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.1682314491
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.4036101004
Short name T867
Test name
Test status
Simulation time 403020059 ps
CPU time 1.07 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:51 PM PDT 24
Peak memory 201516 kb
Host smart-70b37ec3-8354-4ab2-a78d-1a44d04019e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036101004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.4036101004
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.2316463033
Short name T809
Test name
Test status
Simulation time 405709237 ps
CPU time 1.12 seconds
Started Jul 10 06:14:54 PM PDT 24
Finished Jul 10 06:14:59 PM PDT 24
Peak memory 201444 kb
Host smart-32ce43c9-0950-4f49-b4e8-c461026129bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316463033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.2316463033
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.2990368003
Short name T60
Test name
Test status
Simulation time 2323117435 ps
CPU time 3.33 seconds
Started Jul 10 06:14:52 PM PDT 24
Finished Jul 10 06:14:59 PM PDT 24
Peak memory 201476 kb
Host smart-8de43070-f38b-4fa4-b8ff-db08dd42eb87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990368003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.2990368003
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1183915130
Short name T834
Test name
Test status
Simulation time 390499907 ps
CPU time 2.22 seconds
Started Jul 10 06:14:54 PM PDT 24
Finished Jul 10 06:15:00 PM PDT 24
Peak memory 201820 kb
Host smart-a3f38076-2f8e-472b-bfb8-dc239c006e48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183915130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1183915130
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.3504180152
Short name T63
Test name
Test status
Simulation time 4031801389 ps
CPU time 10.29 seconds
Started Jul 10 06:14:49 PM PDT 24
Finished Jul 10 06:15:01 PM PDT 24
Peak memory 201844 kb
Host smart-0a07c17f-7de0-4a8c-8357-934e121cea8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504180152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.3504180152
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.852260543
Short name T92
Test name
Test status
Simulation time 401151545 ps
CPU time 1.8 seconds
Started Jul 10 06:14:57 PM PDT 24
Finished Jul 10 06:15:04 PM PDT 24
Peak memory 201588 kb
Host smart-a315df1a-c232-4bf4-9646-2e58836299ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852260543 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.852260543
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.2467646502
Short name T121
Test name
Test status
Simulation time 491771066 ps
CPU time 0.91 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:50 PM PDT 24
Peak memory 201504 kb
Host smart-332f19b9-e516-4e73-8565-273a56e3d783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467646502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.2467646502
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.2190516147
Short name T851
Test name
Test status
Simulation time 534549815 ps
CPU time 0.84 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:51 PM PDT 24
Peak memory 201412 kb
Host smart-11f104ad-9d0b-4a19-a7f4-90b65bc05400
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190516147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.2190516147
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3267442817
Short name T833
Test name
Test status
Simulation time 4413423727 ps
CPU time 3.52 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:57 PM PDT 24
Peak memory 201880 kb
Host smart-dd219cfc-71ca-4779-af47-9fd6fb83f29c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267442817 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3267442817
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.1506554521
Short name T827
Test name
Test status
Simulation time 731420176 ps
CPU time 3.13 seconds
Started Jul 10 06:14:46 PM PDT 24
Finished Jul 10 06:14:51 PM PDT 24
Peak memory 217708 kb
Host smart-0af27e40-e3d1-4873-9078-8fdbceb83c15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506554521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.1506554521
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.627243793
Short name T334
Test name
Test status
Simulation time 4698554624 ps
CPU time 10.9 seconds
Started Jul 10 06:14:51 PM PDT 24
Finished Jul 10 06:15:05 PM PDT 24
Peak memory 201852 kb
Host smart-0b1125fa-6c2a-48c9-87cf-0d010eee97f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627243793 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_in
tg_err.627243793
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.3074092097
Short name T126
Test name
Test status
Simulation time 870702357 ps
CPU time 1.95 seconds
Started Jul 10 06:14:18 PM PDT 24
Finished Jul 10 06:14:24 PM PDT 24
Peak memory 201708 kb
Host smart-6ed8de47-051e-4df4-a52f-40e7e89610f8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074092097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alia
sing.3074092097
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.1676395800
Short name T915
Test name
Test status
Simulation time 33660699758 ps
CPU time 23.54 seconds
Started Jul 10 06:14:01 PM PDT 24
Finished Jul 10 06:14:30 PM PDT 24
Peak memory 201844 kb
Host smart-117e7503-f191-463e-aace-d7fe3df21beb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676395800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.1676395800
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.1815099682
Short name T117
Test name
Test status
Simulation time 1179140267 ps
CPU time 1.92 seconds
Started Jul 10 06:14:12 PM PDT 24
Finished Jul 10 06:14:18 PM PDT 24
Peak memory 201552 kb
Host smart-fe2ab030-e504-4f3f-9378-e233deb1d59f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815099682 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.1815099682
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.82700869
Short name T870
Test name
Test status
Simulation time 373220071 ps
CPU time 1.54 seconds
Started Jul 10 06:14:11 PM PDT 24
Finished Jul 10 06:14:17 PM PDT 24
Peak memory 201564 kb
Host smart-98101e1f-4af6-44d3-82a6-93fe68c61e36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82700869 -assert nopostproc +UVM_TESTNAME=a
dc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -
cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.82700869
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.986261031
Short name T878
Test name
Test status
Simulation time 526987369 ps
CPU time 1.68 seconds
Started Jul 10 06:14:07 PM PDT 24
Finished Jul 10 06:14:15 PM PDT 24
Peak memory 201504 kb
Host smart-e2611c7f-e0be-48be-9fad-64703d199d62
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986261031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.986261031
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.1773452721
Short name T799
Test name
Test status
Simulation time 310900450 ps
CPU time 1.4 seconds
Started Jul 10 06:14:04 PM PDT 24
Finished Jul 10 06:14:12 PM PDT 24
Peak memory 201436 kb
Host smart-8e6989e5-f49d-4424-8c90-6c01103c55de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773452721 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.1773452721
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.3839843638
Short name T905
Test name
Test status
Simulation time 2511464287 ps
CPU time 5.99 seconds
Started Jul 10 06:14:10 PM PDT 24
Finished Jul 10 06:14:21 PM PDT 24
Peak memory 201648 kb
Host smart-8c304cab-aa54-43b7-aa0c-60df297c12f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839843638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.3839843638
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.3844532668
Short name T874
Test name
Test status
Simulation time 1292264544 ps
CPU time 2.47 seconds
Started Jul 10 06:14:04 PM PDT 24
Finished Jul 10 06:14:13 PM PDT 24
Peak memory 201744 kb
Host smart-0a84f263-f0a9-4c1e-b4bc-09f7e3dfea3b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844532668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.3844532668
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.106522107
Short name T71
Test name
Test status
Simulation time 4208915950 ps
CPU time 5.07 seconds
Started Jul 10 06:14:19 PM PDT 24
Finished Jul 10 06:14:28 PM PDT 24
Peak memory 201844 kb
Host smart-b4dbb6e3-78ac-4ba4-93bd-cec702a95d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106522107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_int
g_err.106522107
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.1035432827
Short name T839
Test name
Test status
Simulation time 319683048 ps
CPU time 1.36 seconds
Started Jul 10 06:14:59 PM PDT 24
Finished Jul 10 06:15:05 PM PDT 24
Peak memory 201376 kb
Host smart-094d5a7e-7cfe-4b88-8721-7785ef5b369a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035432827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.1035432827
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3311669809
Short name T798
Test name
Test status
Simulation time 317496675 ps
CPU time 0.82 seconds
Started Jul 10 06:15:07 PM PDT 24
Finished Jul 10 06:15:12 PM PDT 24
Peak memory 201428 kb
Host smart-40f870ed-15fd-4565-9e38-92849454e6f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311669809 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3311669809
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3571719170
Short name T858
Test name
Test status
Simulation time 430828508 ps
CPU time 0.72 seconds
Started Jul 10 06:14:57 PM PDT 24
Finished Jul 10 06:15:03 PM PDT 24
Peak memory 201440 kb
Host smart-e11fb3b5-d358-4bba-bf9f-812964510055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571719170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3571719170
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.2802747327
Short name T877
Test name
Test status
Simulation time 361756044 ps
CPU time 1.51 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201428 kb
Host smart-2b167422-b519-4801-bfa4-96e3f93ebba1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802747327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.2802747327
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.653913981
Short name T918
Test name
Test status
Simulation time 505821323 ps
CPU time 0.87 seconds
Started Jul 10 06:14:57 PM PDT 24
Finished Jul 10 06:15:03 PM PDT 24
Peak memory 201424 kb
Host smart-190166e0-a9a7-49d9-ada7-f6b0a63ac5a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653913981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.653913981
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.1211468623
Short name T820
Test name
Test status
Simulation time 383068717 ps
CPU time 1.12 seconds
Started Jul 10 06:14:57 PM PDT 24
Finished Jul 10 06:15:02 PM PDT 24
Peak memory 201440 kb
Host smart-2f41fcfa-fee9-44ea-b05f-f0c5a44b0aa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211468623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.1211468623
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.259430653
Short name T868
Test name
Test status
Simulation time 378183894 ps
CPU time 1.02 seconds
Started Jul 10 06:14:58 PM PDT 24
Finished Jul 10 06:15:03 PM PDT 24
Peak memory 201420 kb
Host smart-ea4de484-e83d-4292-8fd5-c22bbbc49c6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259430653 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.259430653
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.3894807754
Short name T860
Test name
Test status
Simulation time 526370699 ps
CPU time 1.93 seconds
Started Jul 10 06:14:47 PM PDT 24
Finished Jul 10 06:14:52 PM PDT 24
Peak memory 201416 kb
Host smart-b9f251b1-5c35-45d3-a217-8d950e2623ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894807754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.3894807754
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1315739506
Short name T887
Test name
Test status
Simulation time 452823074 ps
CPU time 1.78 seconds
Started Jul 10 06:14:52 PM PDT 24
Finished Jul 10 06:14:57 PM PDT 24
Peak memory 201364 kb
Host smart-6d7d81cb-b330-43a9-b265-fbd9859ea9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315739506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1315739506
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.817645693
Short name T892
Test name
Test status
Simulation time 527676958 ps
CPU time 1.22 seconds
Started Jul 10 06:15:05 PM PDT 24
Finished Jul 10 06:15:10 PM PDT 24
Peak memory 201428 kb
Host smart-21f5ff0d-4ffa-40ff-997e-5ff9535b29b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817645693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.817645693
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.705352044
Short name T127
Test name
Test status
Simulation time 1193574214 ps
CPU time 5.77 seconds
Started Jul 10 06:14:04 PM PDT 24
Finished Jul 10 06:14:17 PM PDT 24
Peak memory 201732 kb
Host smart-efdb8e9e-2936-43f4-bdcd-cd60cc0339cd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705352044 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alias
ing.705352044
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3619466480
Short name T122
Test name
Test status
Simulation time 40806105975 ps
CPU time 93.81 seconds
Started Jul 10 06:14:03 PM PDT 24
Finished Jul 10 06:15:43 PM PDT 24
Peak memory 201844 kb
Host smart-f4dc9e71-a3ee-4ac0-aedd-c730b5aff83a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619466480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3619466480
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.422503166
Short name T818
Test name
Test status
Simulation time 1205361100 ps
CPU time 3.45 seconds
Started Jul 10 06:14:00 PM PDT 24
Finished Jul 10 06:14:08 PM PDT 24
Peak memory 201504 kb
Host smart-060cef27-2881-4f1d-861c-d847af435c65
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422503166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_re
set.422503166
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.4148944588
Short name T828
Test name
Test status
Simulation time 575441965 ps
CPU time 1.79 seconds
Started Jul 10 06:14:17 PM PDT 24
Finished Jul 10 06:14:23 PM PDT 24
Peak memory 201588 kb
Host smart-853135cc-5c5d-46f5-9257-1840f010b1e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148944588 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.4148944588
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3324345226
Short name T919
Test name
Test status
Simulation time 354091678 ps
CPU time 1.57 seconds
Started Jul 10 06:14:05 PM PDT 24
Finished Jul 10 06:14:13 PM PDT 24
Peak memory 201504 kb
Host smart-01712a8a-3dfb-4c55-be91-75b1a8172bb8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324345226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3324345226
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3676126995
Short name T805
Test name
Test status
Simulation time 531814465 ps
CPU time 1.91 seconds
Started Jul 10 06:14:05 PM PDT 24
Finished Jul 10 06:14:14 PM PDT 24
Peak memory 201452 kb
Host smart-14282d8f-7285-4b43-8273-775da3e59010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676126995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3676126995
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.4201855451
Short name T916
Test name
Test status
Simulation time 2306841844 ps
CPU time 2.06 seconds
Started Jul 10 06:14:27 PM PDT 24
Finished Jul 10 06:14:35 PM PDT 24
Peak memory 201648 kb
Host smart-cb982c5c-7868-44b4-b6ae-061aca1ac1af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201855451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_c
trl_same_csr_outstanding.4201855451
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.130064530
Short name T76
Test name
Test status
Simulation time 8722348198 ps
CPU time 23.8 seconds
Started Jul 10 06:14:07 PM PDT 24
Finished Jul 10 06:14:37 PM PDT 24
Peak memory 201844 kb
Host smart-ab0232ba-4b80-401b-906e-57082ee5a7bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130064530 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.130064530
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.302292294
Short name T842
Test name
Test status
Simulation time 354324551 ps
CPU time 1.41 seconds
Started Jul 10 06:14:59 PM PDT 24
Finished Jul 10 06:15:05 PM PDT 24
Peak memory 201428 kb
Host smart-f29a81d8-576a-436c-bcbc-8d85830f9880
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302292294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.302292294
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.1175805301
Short name T803
Test name
Test status
Simulation time 323167361 ps
CPU time 0.74 seconds
Started Jul 10 06:14:55 PM PDT 24
Finished Jul 10 06:15:00 PM PDT 24
Peak memory 201448 kb
Host smart-1663e974-0bff-4f2e-8cbf-444be3e3882c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175805301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.1175805301
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.1927532832
Short name T796
Test name
Test status
Simulation time 366045723 ps
CPU time 0.84 seconds
Started Jul 10 06:14:54 PM PDT 24
Finished Jul 10 06:14:58 PM PDT 24
Peak memory 201420 kb
Host smart-d924f06b-7424-4228-a5e3-751179e246cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927532832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.1927532832
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3403627462
Short name T902
Test name
Test status
Simulation time 448965738 ps
CPU time 1.16 seconds
Started Jul 10 06:14:46 PM PDT 24
Finished Jul 10 06:14:49 PM PDT 24
Peak memory 201128 kb
Host smart-030f63f3-8cf8-4189-9a47-06ccce87fc69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403627462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3403627462
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.1625939225
Short name T806
Test name
Test status
Simulation time 439641480 ps
CPU time 0.86 seconds
Started Jul 10 06:14:48 PM PDT 24
Finished Jul 10 06:14:51 PM PDT 24
Peak memory 201376 kb
Host smart-7deefffa-9506-4cf0-b8da-4ada80aa8669
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625939225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.1625939225
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.682087385
Short name T850
Test name
Test status
Simulation time 329275705 ps
CPU time 0.8 seconds
Started Jul 10 06:14:55 PM PDT 24
Finished Jul 10 06:15:00 PM PDT 24
Peak memory 201428 kb
Host smart-03a9dc4a-a117-421f-bc98-60aedc12b892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682087385 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.682087385
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.295856327
Short name T873
Test name
Test status
Simulation time 285803248 ps
CPU time 1.33 seconds
Started Jul 10 06:14:55 PM PDT 24
Finished Jul 10 06:15:01 PM PDT 24
Peak memory 201432 kb
Host smart-6d590c58-9896-4980-b12e-3dbef6f63040
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295856327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.295856327
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.1943382853
Short name T857
Test name
Test status
Simulation time 397852763 ps
CPU time 1.51 seconds
Started Jul 10 06:15:05 PM PDT 24
Finished Jul 10 06:15:10 PM PDT 24
Peak memory 201428 kb
Host smart-8cd39488-5011-49b5-bb3a-b42146a9028d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943382853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.1943382853
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.1629239214
Short name T849
Test name
Test status
Simulation time 343680261 ps
CPU time 1.49 seconds
Started Jul 10 06:14:50 PM PDT 24
Finished Jul 10 06:14:55 PM PDT 24
Peak memory 201424 kb
Host smart-9b27eefb-8fb7-4f79-ba7e-34e44c6227ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629239214 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.1629239214
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.1245476138
Short name T900
Test name
Test status
Simulation time 353660923 ps
CPU time 0.85 seconds
Started Jul 10 06:14:53 PM PDT 24
Finished Jul 10 06:14:57 PM PDT 24
Peak memory 201424 kb
Host smart-1b4d1b91-52d0-4ec2-8e80-a5e95d4c3bc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245476138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.1245476138
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.179688212
Short name T118
Test name
Test status
Simulation time 970798453 ps
CPU time 2.95 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:32 PM PDT 24
Peak memory 201712 kb
Host smart-73a64602-68ce-4e88-9f8e-2273c6e34aa2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179688212 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.179688212
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.1965259738
Short name T830
Test name
Test status
Simulation time 26705689321 ps
CPU time 23.87 seconds
Started Jul 10 06:14:15 PM PDT 24
Finished Jul 10 06:14:42 PM PDT 24
Peak memory 201760 kb
Host smart-ca196556-0528-4e4b-a63f-84b200ded1b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965259738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.1965259738
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.3365546443
Short name T115
Test name
Test status
Simulation time 1164928961 ps
CPU time 2.5 seconds
Started Jul 10 06:14:21 PM PDT 24
Finished Jul 10 06:14:27 PM PDT 24
Peak memory 201540 kb
Host smart-b77ddc12-2362-4d50-8d0f-a4c4218891ea
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365546443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.3365546443
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2516354025
Short name T91
Test name
Test status
Simulation time 481692772 ps
CPU time 2.12 seconds
Started Jul 10 06:14:03 PM PDT 24
Finished Jul 10 06:14:11 PM PDT 24
Peak memory 201564 kb
Host smart-e057a0bb-4e8f-4e20-a413-d98491ba6af6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516354025 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2516354025
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.300994225
Short name T913
Test name
Test status
Simulation time 558301077 ps
CPU time 1.44 seconds
Started Jul 10 06:14:15 PM PDT 24
Finished Jul 10 06:14:20 PM PDT 24
Peak memory 201496 kb
Host smart-11f7fa08-bd60-4da5-8212-41bf5bb99f5b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300994225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.300994225
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.1602603102
Short name T817
Test name
Test status
Simulation time 379867572 ps
CPU time 0.89 seconds
Started Jul 10 06:14:18 PM PDT 24
Finished Jul 10 06:14:23 PM PDT 24
Peak memory 201432 kb
Host smart-4c3a4c18-07cf-4f36-a6d5-23f79b53ca74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602603102 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.1602603102
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.1550207333
Short name T62
Test name
Test status
Simulation time 2745047237 ps
CPU time 2.21 seconds
Started Jul 10 06:14:22 PM PDT 24
Finished Jul 10 06:14:28 PM PDT 24
Peak memory 201644 kb
Host smart-abf0c65e-e027-48a1-886e-1380c9ff3f23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550207333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.1550207333
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.2806297670
Short name T824
Test name
Test status
Simulation time 331727544 ps
CPU time 3.02 seconds
Started Jul 10 06:14:14 PM PDT 24
Finished Jul 10 06:14:21 PM PDT 24
Peak memory 218056 kb
Host smart-98badcea-f0ec-43ec-8c73-04240ef5ebfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806297670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.2806297670
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3239154862
Short name T336
Test name
Test status
Simulation time 4892029770 ps
CPU time 4.14 seconds
Started Jul 10 06:14:11 PM PDT 24
Finished Jul 10 06:14:20 PM PDT 24
Peak memory 201788 kb
Host smart-2f4a8154-e7ce-482d-846c-44a905ea7538
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239154862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3239154862
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1251485319
Short name T816
Test name
Test status
Simulation time 352032210 ps
CPU time 0.82 seconds
Started Jul 10 06:14:54 PM PDT 24
Finished Jul 10 06:14:58 PM PDT 24
Peak memory 201432 kb
Host smart-1e8b2af2-2567-44ea-9629-6987b10237e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251485319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1251485319
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1482753397
Short name T813
Test name
Test status
Simulation time 526153678 ps
CPU time 0.95 seconds
Started Jul 10 06:15:05 PM PDT 24
Finished Jul 10 06:15:10 PM PDT 24
Peak memory 201428 kb
Host smart-4b3b22a0-b8c8-4d9b-9f6a-cf1d89489dc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482753397 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1482753397
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.2938958911
Short name T906
Test name
Test status
Simulation time 327531284 ps
CPU time 1.43 seconds
Started Jul 10 06:14:52 PM PDT 24
Finished Jul 10 06:14:57 PM PDT 24
Peak memory 201440 kb
Host smart-7f380feb-03c1-4418-8ece-775dadb332f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938958911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.2938958911
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.2690681274
Short name T904
Test name
Test status
Simulation time 441994453 ps
CPU time 0.8 seconds
Started Jul 10 06:14:55 PM PDT 24
Finished Jul 10 06:15:00 PM PDT 24
Peak memory 201424 kb
Host smart-ec9136cf-2783-4d5d-b754-9a8f8c1c1481
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690681274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.2690681274
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.86706760
Short name T832
Test name
Test status
Simulation time 527622288 ps
CPU time 0.95 seconds
Started Jul 10 06:15:08 PM PDT 24
Finished Jul 10 06:15:13 PM PDT 24
Peak memory 201460 kb
Host smart-ba4100c6-bbe8-4788-ad24-b449f3ce53b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86706760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.86706760
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.3129650277
Short name T880
Test name
Test status
Simulation time 304050421 ps
CPU time 0.85 seconds
Started Jul 10 06:15:01 PM PDT 24
Finished Jul 10 06:15:06 PM PDT 24
Peak memory 201440 kb
Host smart-4d2c3096-b567-4de4-abe9-a1a56259febd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129650277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.3129650277
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.135582634
Short name T808
Test name
Test status
Simulation time 432348252 ps
CPU time 1.17 seconds
Started Jul 10 06:14:56 PM PDT 24
Finished Jul 10 06:15:02 PM PDT 24
Peak memory 201420 kb
Host smart-e48717df-42ad-4a77-96fd-34eb909e29cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135582634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.135582634
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1754736219
Short name T804
Test name
Test status
Simulation time 410160001 ps
CPU time 0.86 seconds
Started Jul 10 06:14:49 PM PDT 24
Finished Jul 10 06:14:52 PM PDT 24
Peak memory 201352 kb
Host smart-4c1d3dbd-403b-4ef4-879b-8a0958d2217c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754736219 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1754736219
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.3582619732
Short name T846
Test name
Test status
Simulation time 499948701 ps
CPU time 1.02 seconds
Started Jul 10 06:14:56 PM PDT 24
Finished Jul 10 06:15:01 PM PDT 24
Peak memory 201420 kb
Host smart-78fa0339-0a1e-4bcd-9e59-914f672bb819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582619732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.3582619732
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.3376976132
Short name T807
Test name
Test status
Simulation time 420130714 ps
CPU time 0.87 seconds
Started Jul 10 06:15:00 PM PDT 24
Finished Jul 10 06:15:05 PM PDT 24
Peak memory 201440 kb
Host smart-089e75df-a6ce-4024-b4ce-25ccfc9e0b73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376976132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.3376976132
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.3565562900
Short name T871
Test name
Test status
Simulation time 473571361 ps
CPU time 1.99 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:30 PM PDT 24
Peak memory 201560 kb
Host smart-39f411e5-2f92-4056-b60f-9671468332a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565562900 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.3565562900
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.897167815
Short name T891
Test name
Test status
Simulation time 382397567 ps
CPU time 1.04 seconds
Started Jul 10 06:14:17 PM PDT 24
Finished Jul 10 06:14:22 PM PDT 24
Peak memory 201504 kb
Host smart-f243b07e-737f-4427-95c4-0f00dc2d5e04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897167815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.897167815
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.1044268860
Short name T876
Test name
Test status
Simulation time 461025647 ps
CPU time 1.67 seconds
Started Jul 10 06:14:25 PM PDT 24
Finished Jul 10 06:14:32 PM PDT 24
Peak memory 201428 kb
Host smart-280097db-cd71-4479-8adc-dbc623095d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044268860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.1044268860
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.2841673983
Short name T861
Test name
Test status
Simulation time 2361656825 ps
CPU time 9.32 seconds
Started Jul 10 06:14:16 PM PDT 24
Finished Jul 10 06:14:29 PM PDT 24
Peak memory 201548 kb
Host smart-1384ccf0-3622-44af-b45a-f757252e1f3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841673983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.2841673983
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.4157454182
Short name T901
Test name
Test status
Simulation time 525019885 ps
CPU time 3 seconds
Started Jul 10 06:14:04 PM PDT 24
Finished Jul 10 06:14:13 PM PDT 24
Peak memory 211036 kb
Host smart-ba557eae-ced4-44b3-b4d2-42c726b71fb1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157454182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.4157454182
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.553061987
Short name T911
Test name
Test status
Simulation time 4597751636 ps
CPU time 7.24 seconds
Started Jul 10 06:14:13 PM PDT 24
Finished Jul 10 06:14:24 PM PDT 24
Peak memory 201844 kb
Host smart-9429fce9-acdb-4d26-b4b6-8e96353a227f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553061987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.553061987
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.146345035
Short name T864
Test name
Test status
Simulation time 515079719 ps
CPU time 2 seconds
Started Jul 10 06:14:31 PM PDT 24
Finished Jul 10 06:14:37 PM PDT 24
Peak memory 201564 kb
Host smart-05d1c41a-2f1b-4869-9636-17f900b4a387
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146345035 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.146345035
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.4140320271
Short name T841
Test name
Test status
Simulation time 331085569 ps
CPU time 1.47 seconds
Started Jul 10 06:14:27 PM PDT 24
Finished Jul 10 06:14:34 PM PDT 24
Peak memory 201516 kb
Host smart-410f226d-d6cd-4a00-855c-f34673b7aa12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140320271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.4140320271
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.2311892760
Short name T797
Test name
Test status
Simulation time 393553434 ps
CPU time 0.89 seconds
Started Jul 10 06:14:25 PM PDT 24
Finished Jul 10 06:14:31 PM PDT 24
Peak memory 201436 kb
Host smart-65e65d96-4604-4c0e-8eb1-825f56ac8229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311892760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.2311892760
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2932593618
Short name T866
Test name
Test status
Simulation time 4251062317 ps
CPU time 12.71 seconds
Started Jul 10 06:14:30 PM PDT 24
Finished Jul 10 06:14:47 PM PDT 24
Peak memory 201816 kb
Host smart-bd67de94-71fc-437b-8e79-abfedd5910f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932593618 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2932593618
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.1284823738
Short name T837
Test name
Test status
Simulation time 330705592 ps
CPU time 1.58 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:30 PM PDT 24
Peak memory 201776 kb
Host smart-a3f65b8a-3100-4faf-9e08-f41cf06942b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284823738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.1284823738
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.612339061
Short name T75
Test name
Test status
Simulation time 8561629036 ps
CPU time 7.17 seconds
Started Jul 10 06:14:20 PM PDT 24
Finished Jul 10 06:14:31 PM PDT 24
Peak memory 201788 kb
Host smart-4e62820a-d989-47f2-a58a-8391052f3eab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612339061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_int
g_err.612339061
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.108499686
Short name T888
Test name
Test status
Simulation time 402858321 ps
CPU time 1.01 seconds
Started Jul 10 06:14:32 PM PDT 24
Finished Jul 10 06:14:36 PM PDT 24
Peak memory 201480 kb
Host smart-5d529139-ff9c-4889-9864-bf0c701b6f78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108499686 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.108499686
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.1464718281
Short name T859
Test name
Test status
Simulation time 454422267 ps
CPU time 1.51 seconds
Started Jul 10 06:14:25 PM PDT 24
Finished Jul 10 06:14:31 PM PDT 24
Peak memory 201516 kb
Host smart-6408c270-1f69-430f-a13d-5769f2c94af0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464718281 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.1464718281
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.2650123141
Short name T821
Test name
Test status
Simulation time 395123019 ps
CPU time 0.87 seconds
Started Jul 10 06:14:34 PM PDT 24
Finished Jul 10 06:14:37 PM PDT 24
Peak memory 201448 kb
Host smart-095cc6b8-b1f3-478c-8115-d16913bcce56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650123141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.2650123141
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.2411578869
Short name T132
Test name
Test status
Simulation time 4568259665 ps
CPU time 9.06 seconds
Started Jul 10 06:14:17 PM PDT 24
Finished Jul 10 06:14:30 PM PDT 24
Peak memory 201844 kb
Host smart-08d96773-de31-4781-92f2-2c7e0f3ebf40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411578869 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.2411578869
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.992597431
Short name T903
Test name
Test status
Simulation time 482290734 ps
CPU time 3.71 seconds
Started Jul 10 06:14:22 PM PDT 24
Finished Jul 10 06:14:30 PM PDT 24
Peak memory 210964 kb
Host smart-24c1af87-4490-466a-b573-03d5e1599ecd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992597431 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.992597431
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.3726755563
Short name T893
Test name
Test status
Simulation time 8705416445 ps
CPU time 13.06 seconds
Started Jul 10 06:14:18 PM PDT 24
Finished Jul 10 06:14:35 PM PDT 24
Peak memory 201844 kb
Host smart-d43c9e79-d825-4289-8fc1-a29233a8175e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726755563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.3726755563
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.903557496
Short name T886
Test name
Test status
Simulation time 427878538 ps
CPU time 1.46 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:31 PM PDT 24
Peak memory 201564 kb
Host smart-69aa40d0-ea02-4c1b-b5b1-f6a1aba71840
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903557496 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.903557496
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.2896318937
Short name T831
Test name
Test status
Simulation time 539871041 ps
CPU time 1.36 seconds
Started Jul 10 06:14:32 PM PDT 24
Finished Jul 10 06:14:36 PM PDT 24
Peak memory 201504 kb
Host smart-49a9ff1f-1978-4c55-b9bd-cc2760f6e298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896318937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.2896318937
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.1095739702
Short name T855
Test name
Test status
Simulation time 404026281 ps
CPU time 0.82 seconds
Started Jul 10 06:14:41 PM PDT 24
Finished Jul 10 06:14:44 PM PDT 24
Peak memory 201432 kb
Host smart-13ee2869-9f75-4494-9e36-f59a6c157a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095739702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.1095739702
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2990206037
Short name T848
Test name
Test status
Simulation time 4220832747 ps
CPU time 5.07 seconds
Started Jul 10 06:14:24 PM PDT 24
Finished Jul 10 06:14:33 PM PDT 24
Peak memory 201796 kb
Host smart-91181815-4b25-4584-9762-e29c16a29e41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990206037 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2990206037
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.1049519504
Short name T894
Test name
Test status
Simulation time 529780889 ps
CPU time 3.15 seconds
Started Jul 10 06:14:34 PM PDT 24
Finished Jul 10 06:14:39 PM PDT 24
Peak memory 211052 kb
Host smart-8029185d-390e-4857-88b4-d70f9235facb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049519504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.1049519504
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.188064434
Short name T898
Test name
Test status
Simulation time 4465007273 ps
CPU time 9.15 seconds
Started Jul 10 06:14:52 PM PDT 24
Finished Jul 10 06:15:04 PM PDT 24
Peak memory 201892 kb
Host smart-f50bd46a-b289-4cd9-8866-66ccd4216bbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188064434 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_int
g_err.188064434
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.2550342650
Short name T826
Test name
Test status
Simulation time 481778920 ps
CPU time 2.02 seconds
Started Jul 10 06:14:27 PM PDT 24
Finished Jul 10 06:14:34 PM PDT 24
Peak memory 201608 kb
Host smart-c5b4704a-cbdd-4b22-9478-df12fb2eea2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550342650 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.2550342650
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.3001769730
Short name T128
Test name
Test status
Simulation time 441732201 ps
CPU time 1.06 seconds
Started Jul 10 06:14:35 PM PDT 24
Finished Jul 10 06:14:38 PM PDT 24
Peak memory 201516 kb
Host smart-9a8f81ca-50ea-4a7d-8aec-d9f13c5abb03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001769730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.3001769730
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.3278604621
Short name T907
Test name
Test status
Simulation time 357174436 ps
CPU time 0.78 seconds
Started Jul 10 06:14:38 PM PDT 24
Finished Jul 10 06:14:40 PM PDT 24
Peak memory 201432 kb
Host smart-97613c65-2fac-49a1-ae04-949f42bf973a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278604621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.3278604621
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.2479538911
Short name T61
Test name
Test status
Simulation time 4955726263 ps
CPU time 11.91 seconds
Started Jul 10 06:14:41 PM PDT 24
Finished Jul 10 06:14:54 PM PDT 24
Peak memory 201864 kb
Host smart-4d2f3202-9ab9-4e70-81de-eff799e71947
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479538911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.2479538911
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.4228043158
Short name T74
Test name
Test status
Simulation time 399564885 ps
CPU time 1.64 seconds
Started Jul 10 06:14:30 PM PDT 24
Finished Jul 10 06:14:36 PM PDT 24
Peak memory 201792 kb
Host smart-2f5a35e2-a6a7-4245-aa65-1b6726b90cf5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228043158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.4228043158
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.2538564729
Short name T337
Test name
Test status
Simulation time 4178964300 ps
CPU time 11.67 seconds
Started Jul 10 06:14:44 PM PDT 24
Finished Jul 10 06:14:57 PM PDT 24
Peak memory 201812 kb
Host smart-952fded9-49d3-40b5-83de-b17709b5d6d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538564729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.2538564729
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.979005200
Short name T489
Test name
Test status
Simulation time 341348272 ps
CPU time 0.81 seconds
Started Jul 10 06:15:18 PM PDT 24
Finished Jul 10 06:15:21 PM PDT 24
Peak memory 201660 kb
Host smart-1b207e9b-d24b-4880-98ee-aec2e548edf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979005200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.979005200
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.273408823
Short name T93
Test name
Test status
Simulation time 158912945397 ps
CPU time 222.36 seconds
Started Jul 10 06:15:21 PM PDT 24
Finished Jul 10 06:19:05 PM PDT 24
Peak memory 201936 kb
Host smart-cc97363a-2f5d-46b8-bba3-783af7c7d3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273408823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.273408823
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.1513493494
Short name T556
Test name
Test status
Simulation time 333600582277 ps
CPU time 721.56 seconds
Started Jul 10 06:15:23 PM PDT 24
Finished Jul 10 06:27:27 PM PDT 24
Peak memory 201860 kb
Host smart-507dee5e-db48-4514-ac48-386c55b6ac44
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513493494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.1513493494
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.3643913824
Short name T450
Test name
Test status
Simulation time 161426161874 ps
CPU time 91.46 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:17:03 PM PDT 24
Peak memory 201900 kb
Host smart-d8233c06-c852-4682-907f-a17fcf1c3446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643913824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.3643913824
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.1866745540
Short name T666
Test name
Test status
Simulation time 163255282516 ps
CPU time 392.83 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:22:28 PM PDT 24
Peak memory 201864 kb
Host smart-6a82376f-1315-4372-905b-81e15a0b1150
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866745540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixe
d.1866745540
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.3045116190
Short name T326
Test name
Test status
Simulation time 530047798364 ps
CPU time 1205.41 seconds
Started Jul 10 06:15:18 PM PDT 24
Finished Jul 10 06:35:26 PM PDT 24
Peak memory 201896 kb
Host smart-36f66b14-0af7-4244-989d-8f8859e18728
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045116190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_
wakeup.3045116190
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.2789973443
Short name T502
Test name
Test status
Simulation time 203281862502 ps
CPU time 463.96 seconds
Started Jul 10 06:15:20 PM PDT 24
Finished Jul 10 06:23:06 PM PDT 24
Peak memory 201856 kb
Host smart-3f0a4897-f12e-497d-b41e-13b9eb198a62
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789973443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.2789973443
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.277792825
Short name T459
Test name
Test status
Simulation time 66972326543 ps
CPU time 352.88 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:21:24 PM PDT 24
Peak memory 202280 kb
Host smart-df1f8686-d9ee-4d21-b6b0-8b66da081cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277792825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.277792825
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3106572079
Short name T157
Test name
Test status
Simulation time 25973329288 ps
CPU time 57.16 seconds
Started Jul 10 06:15:19 PM PDT 24
Finished Jul 10 06:16:19 PM PDT 24
Peak memory 201688 kb
Host smart-4c562d8d-f431-41c3-afa0-342860be43ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106572079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3106572079
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.381229741
Short name T614
Test name
Test status
Simulation time 3145435806 ps
CPU time 8.01 seconds
Started Jul 10 06:15:23 PM PDT 24
Finished Jul 10 06:15:33 PM PDT 24
Peak memory 201696 kb
Host smart-aff78512-453d-4292-84ee-f3f66feafc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381229741 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.381229741
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.2283832019
Short name T77
Test name
Test status
Simulation time 4017708001 ps
CPU time 3.18 seconds
Started Jul 10 06:15:24 PM PDT 24
Finished Jul 10 06:15:29 PM PDT 24
Peak memory 217184 kb
Host smart-77946357-2556-4f32-8e31-4c3008ad3466
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283832019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.2283832019
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.1946859537
Short name T391
Test name
Test status
Simulation time 5645552427 ps
CPU time 13.94 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:15:44 PM PDT 24
Peak memory 201704 kb
Host smart-1b4e75d0-b4eb-4577-8e09-55dfba4c37ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946859537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.1946859537
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.935534788
Short name T768
Test name
Test status
Simulation time 497865020167 ps
CPU time 1117.25 seconds
Started Jul 10 06:15:21 PM PDT 24
Finished Jul 10 06:34:00 PM PDT 24
Peak memory 201572 kb
Host smart-bb178491-572e-49c3-a440-0da0c26db9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935534788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.935534788
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2572128751
Short name T645
Test name
Test status
Simulation time 19813518576 ps
CPU time 55.93 seconds
Started Jul 10 06:15:19 PM PDT 24
Finished Jul 10 06:16:17 PM PDT 24
Peak memory 210580 kb
Host smart-bc3f1e6b-4a2a-4808-b815-cbfb0c02d414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572128751 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2572128751
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.190828361
Short name T582
Test name
Test status
Simulation time 498016544 ps
CPU time 1.81 seconds
Started Jul 10 06:15:18 PM PDT 24
Finished Jul 10 06:15:22 PM PDT 24
Peak memory 201640 kb
Host smart-b90f22d3-16f1-4240-9422-63e58837c8d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=190828361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.190828361
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2887835270
Short name T144
Test name
Test status
Simulation time 488522157602 ps
CPU time 788.57 seconds
Started Jul 10 06:15:22 PM PDT 24
Finished Jul 10 06:28:33 PM PDT 24
Peak memory 201976 kb
Host smart-3a69047b-8a8c-4260-9bcb-d116f4b2aeff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887835270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2887835270
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.502060595
Short name T176
Test name
Test status
Simulation time 324662344484 ps
CPU time 175.72 seconds
Started Jul 10 06:15:26 PM PDT 24
Finished Jul 10 06:18:24 PM PDT 24
Peak memory 201904 kb
Host smart-20a8cb4a-78f2-42a2-8625-0b1b5541a599
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=502060595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt
_fixed.502060595
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.2126444328
Short name T168
Test name
Test status
Simulation time 486037035619 ps
CPU time 266.76 seconds
Started Jul 10 06:15:23 PM PDT 24
Finished Jul 10 06:19:52 PM PDT 24
Peak memory 201884 kb
Host smart-d662e7db-de6d-49e9-b576-b4d95ee6ea91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126444328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.2126444328
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.513411230
Short name T159
Test name
Test status
Simulation time 496924493387 ps
CPU time 1120.71 seconds
Started Jul 10 06:15:12 PM PDT 24
Finished Jul 10 06:33:56 PM PDT 24
Peak memory 202080 kb
Host smart-4e39b7e2-c001-445f-991a-f744d448dd0a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=513411230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixed
.513411230
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.1619703697
Short name T442
Test name
Test status
Simulation time 94273339699 ps
CPU time 501.52 seconds
Started Jul 10 06:15:32 PM PDT 24
Finished Jul 10 06:23:55 PM PDT 24
Peak memory 202280 kb
Host smart-4fcf6edf-2789-4bb0-a29c-5b25924585d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619703697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.1619703697
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.2918517259
Short name T5
Test name
Test status
Simulation time 38562141840 ps
CPU time 5.23 seconds
Started Jul 10 06:15:26 PM PDT 24
Finished Jul 10 06:15:33 PM PDT 24
Peak memory 201692 kb
Host smart-45228bb4-6e08-4981-a210-4a553a171892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918517259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.2918517259
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.2993974792
Short name T449
Test name
Test status
Simulation time 4003423293 ps
CPU time 5.45 seconds
Started Jul 10 06:15:19 PM PDT 24
Finished Jul 10 06:15:26 PM PDT 24
Peak memory 201724 kb
Host smart-1b09f539-c5e0-46c6-beaf-da934e6405bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993974792 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.2993974792
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.3740004373
Short name T468
Test name
Test status
Simulation time 5907584372 ps
CPU time 7.31 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:15:54 PM PDT 24
Peak memory 201724 kb
Host smart-b9974290-0382-4426-afe6-c7c04a50911d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740004373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.3740004373
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2259453155
Short name T151
Test name
Test status
Simulation time 544737173966 ps
CPU time 1302.97 seconds
Started Jul 10 06:15:17 PM PDT 24
Finished Jul 10 06:37:02 PM PDT 24
Peak memory 201892 kb
Host smart-bfadb646-6a31-495b-acd8-0d484cc220c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259453155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2259453155
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.4001365650
Short name T42
Test name
Test status
Simulation time 441023150 ps
CPU time 1.1 seconds
Started Jul 10 06:15:57 PM PDT 24
Finished Jul 10 06:15:59 PM PDT 24
Peak memory 201640 kb
Host smart-a396956b-a7a3-473c-9794-44f099ef34ac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001365650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.4001365650
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.20559718
Short name T692
Test name
Test status
Simulation time 168167155932 ps
CPU time 47.81 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:16:37 PM PDT 24
Peak memory 201900 kb
Host smart-94a842a9-474e-4b35-9cf3-bd2a0e470cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20559718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.20559718
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3756696237
Short name T86
Test name
Test status
Simulation time 484358446093 ps
CPU time 335.55 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:21:27 PM PDT 24
Peak memory 201996 kb
Host smart-ed3214d5-bf2a-4d16-8589-15578148dbe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756696237 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3756696237
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.3694076847
Short name T715
Test name
Test status
Simulation time 165515945834 ps
CPU time 91.78 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:17:25 PM PDT 24
Peak memory 201880 kb
Host smart-1687e04b-3894-42f0-9228-3ea27590c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694076847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.3694076847
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.1347552675
Short name T724
Test name
Test status
Simulation time 490428193284 ps
CPU time 251.31 seconds
Started Jul 10 06:15:55 PM PDT 24
Finished Jul 10 06:20:08 PM PDT 24
Peak memory 201864 kb
Host smart-9ef5416b-802e-4a09-81c9-f1c715707169
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347552675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.1347552675
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.4131801662
Short name T503
Test name
Test status
Simulation time 450114292754 ps
CPU time 1035.08 seconds
Started Jul 10 06:15:38 PM PDT 24
Finished Jul 10 06:32:55 PM PDT 24
Peak memory 201884 kb
Host smart-59a2f5aa-4eb3-4199-a763-2a7ea5f85f55
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131801662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.4131801662
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.641247191
Short name T554
Test name
Test status
Simulation time 196507983970 ps
CPU time 87.61 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:17:21 PM PDT 24
Peak memory 201868 kb
Host smart-525d1e94-4d9d-461e-98aa-20b7abdf00da
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641247191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.641247191
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.1760484299
Short name T476
Test name
Test status
Simulation time 99175591616 ps
CPU time 357.75 seconds
Started Jul 10 06:15:48 PM PDT 24
Finished Jul 10 06:21:48 PM PDT 24
Peak memory 202280 kb
Host smart-e4fcbd57-dd05-47ee-a4aa-b5ba47f0ee47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760484299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.1760484299
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.847691696
Short name T598
Test name
Test status
Simulation time 21618390531 ps
CPU time 25.37 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:16:23 PM PDT 24
Peak memory 201692 kb
Host smart-3c299524-af3b-499b-8422-45cee336dd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847691696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.847691696
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.1169326092
Short name T646
Test name
Test status
Simulation time 2890757417 ps
CPU time 7.25 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:15:56 PM PDT 24
Peak memory 201616 kb
Host smart-f82d3de2-5d35-4dd6-a8f4-0ab62a292130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169326092 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.1169326092
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.3442323930
Short name T725
Test name
Test status
Simulation time 6002786320 ps
CPU time 3.93 seconds
Started Jul 10 06:15:42 PM PDT 24
Finished Jul 10 06:15:48 PM PDT 24
Peak memory 201688 kb
Host smart-40cd3c35-8b60-4f9a-89a7-e1fd488418fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442323930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.3442323930
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.3919396111
Short name T45
Test name
Test status
Simulation time 494616448299 ps
CPU time 997.96 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:32:21 PM PDT 24
Peak memory 201876 kb
Host smart-fa3efa16-d572-4f01-a18c-610e8a8d603b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919396111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.3919396111
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.2574114555
Short name T56
Test name
Test status
Simulation time 308600528289 ps
CPU time 302.59 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:20:52 PM PDT 24
Peak memory 210640 kb
Host smart-d01360b8-9b79-4c34-8a4f-ea016dc47875
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574114555 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.2574114555
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.1872166501
Short name T596
Test name
Test status
Simulation time 521449724 ps
CPU time 0.75 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:15:52 PM PDT 24
Peak memory 201656 kb
Host smart-d1d9a335-82ba-4620-8706-96cd26578965
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872166501 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.1872166501
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.490342615
Short name T609
Test name
Test status
Simulation time 328671704877 ps
CPU time 89.07 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:17:22 PM PDT 24
Peak memory 201868 kb
Host smart-e593528b-5770-45bd-9b4d-c57d911b6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490342615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.490342615
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.572813995
Short name T455
Test name
Test status
Simulation time 330159071313 ps
CPU time 773.8 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:28:42 PM PDT 24
Peak memory 201864 kb
Host smart-dccf4dcb-8ad6-4de1-ac5f-b75e35d0339f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=572813995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrup
t_fixed.572813995
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.3985243344
Short name T189
Test name
Test status
Simulation time 495566577689 ps
CPU time 259.48 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:20:11 PM PDT 24
Peak memory 201968 kb
Host smart-117631b9-b58b-4790-921e-da7dd3643e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985243344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.3985243344
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.2396054485
Short name T43
Test name
Test status
Simulation time 322951219778 ps
CPU time 349.84 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:21:33 PM PDT 24
Peak memory 201860 kb
Host smart-b6a8e475-cddd-4913-a8b0-82344dee918e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396054485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.2396054485
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.1388364229
Short name T364
Test name
Test status
Simulation time 601548185099 ps
CPU time 1211.7 seconds
Started Jul 10 06:15:57 PM PDT 24
Finished Jul 10 06:36:10 PM PDT 24
Peak memory 201900 kb
Host smart-6299dcd5-5520-44d4-a2f1-56ffb5763c77
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388364229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.1388364229
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.263838031
Short name T531
Test name
Test status
Simulation time 118911781210 ps
CPU time 588.92 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:25:55 PM PDT 24
Peak memory 202300 kb
Host smart-b7f49d5d-93ab-4ed8-9502-0bd795765e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263838031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.263838031
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2192161704
Short name T399
Test name
Test status
Simulation time 30983013750 ps
CPU time 72.11 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:17:04 PM PDT 24
Peak memory 201692 kb
Host smart-04048e89-219b-42bc-a056-82b7668ca452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192161704 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2192161704
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.2296035423
Short name T729
Test name
Test status
Simulation time 3414567442 ps
CPU time 2.64 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:16:11 PM PDT 24
Peak memory 201692 kb
Host smart-e1d6785a-611e-402f-845a-0465717fe415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296035423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.2296035423
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.3921153218
Short name T419
Test name
Test status
Simulation time 5626048265 ps
CPU time 3.97 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:15:54 PM PDT 24
Peak memory 201688 kb
Host smart-abc0b231-5499-4f6e-b350-c54355863d62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921153218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.3921153218
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.2425577090
Short name T498
Test name
Test status
Simulation time 389559198 ps
CPU time 0.82 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:15:57 PM PDT 24
Peak memory 201640 kb
Host smart-aea359ef-4778-4857-9719-723852744118
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425577090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.2425577090
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3252937502
Short name T173
Test name
Test status
Simulation time 500079553116 ps
CPU time 298.11 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:20:53 PM PDT 24
Peak memory 201784 kb
Host smart-0b061471-c871-410d-8e5a-d913dd895e05
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252937502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3252937502
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.2339010104
Short name T523
Test name
Test status
Simulation time 321904590114 ps
CPU time 664.22 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:27:06 PM PDT 24
Peak memory 201940 kb
Host smart-f54f552e-4c19-4a66-ba3c-96029d185545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339010104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.2339010104
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1094643369
Short name T460
Test name
Test status
Simulation time 325963916487 ps
CPU time 750.66 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:28:26 PM PDT 24
Peak memory 201848 kb
Host smart-bbd1deaf-3d9c-426d-9f8e-9c250a96208c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094643369 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1094643369
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2598778556
Short name T575
Test name
Test status
Simulation time 324156677051 ps
CPU time 446.14 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:23:33 PM PDT 24
Peak memory 201960 kb
Host smart-39a8000c-0647-4ad0-98d1-5de4a22d402d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598778556 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2598778556
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.649476026
Short name T673
Test name
Test status
Simulation time 165511510191 ps
CPU time 178.9 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:19:06 PM PDT 24
Peak memory 201892 kb
Host smart-53772a0f-aeb0-425c-b2fc-1e0a8f227a67
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=649476026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fixe
d.649476026
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.3033089864
Short name T456
Test name
Test status
Simulation time 204817251115 ps
CPU time 236.89 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:19:59 PM PDT 24
Peak memory 201820 kb
Host smart-d2bde2bb-e066-43e8-87bf-e8216fd5390b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033089864 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12
.adc_ctrl_filters_wakeup_fixed.3033089864
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.974862647
Short name T200
Test name
Test status
Simulation time 126128582787 ps
CPU time 395.68 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:22:31 PM PDT 24
Peak memory 202212 kb
Host smart-e7a68c7f-660a-42cb-a1bc-64c3c83c68f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974862647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.974862647
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.466320684
Short name T581
Test name
Test status
Simulation time 38053078445 ps
CPU time 16.18 seconds
Started Jul 10 06:16:09 PM PDT 24
Finished Jul 10 06:16:28 PM PDT 24
Peak memory 201712 kb
Host smart-2b244c54-2812-4c56-9ea5-8f3d1f993c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466320684 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.466320684
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1870798462
Short name T350
Test name
Test status
Simulation time 3391900756 ps
CPU time 8.89 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:16:16 PM PDT 24
Peak memory 201732 kb
Host smart-227e36fe-bc96-44f2-a5a4-18fe4d30a560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870798462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1870798462
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.770386055
Short name T29
Test name
Test status
Simulation time 5709133959 ps
CPU time 8.79 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:16:09 PM PDT 24
Peak memory 201692 kb
Host smart-7cd00099-649c-444b-a5f4-8e26cad0c746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770386055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.770386055
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.1516165364
Short name T458
Test name
Test status
Simulation time 204953328927 ps
CPU time 481.26 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:23:50 PM PDT 24
Peak memory 201884 kb
Host smart-9e6eca3c-c880-4e22-beb7-9361c91da557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516165364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.1516165364
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1573857533
Short name T34
Test name
Test status
Simulation time 226666984716 ps
CPU time 122.29 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:17:56 PM PDT 24
Peak memory 210236 kb
Host smart-4962cc19-57c5-4536-8643-5cd007a7677b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573857533 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1573857533
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.2096914916
Short name T463
Test name
Test status
Simulation time 498031513 ps
CPU time 1.8 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:16:05 PM PDT 24
Peak memory 201640 kb
Host smart-4442c614-56dc-4c03-a07f-0b4a2b5b18be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096914916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.2096914916
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.2637347095
Short name T690
Test name
Test status
Simulation time 376763403182 ps
CPU time 854.25 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:30:15 PM PDT 24
Peak memory 201956 kb
Host smart-00d083ab-8f02-49f7-a4e7-5f7a7fbcdae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637347095 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.2637347095
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.1035692962
Short name T621
Test name
Test status
Simulation time 332649933646 ps
CPU time 736.81 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:28:08 PM PDT 24
Peak memory 201956 kb
Host smart-3ee0a735-fe03-432d-b032-cf5033acc6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035692962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.1035692962
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3555267730
Short name T590
Test name
Test status
Simulation time 163962726515 ps
CPU time 25.3 seconds
Started Jul 10 06:15:48 PM PDT 24
Finished Jul 10 06:16:16 PM PDT 24
Peak memory 201876 kb
Host smart-da80235f-3fe1-42eb-b7e4-66b9826e151e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555267730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3555267730
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.1670790162
Short name T794
Test name
Test status
Simulation time 500900724209 ps
CPU time 245.41 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:20:06 PM PDT 24
Peak memory 201952 kb
Host smart-68fa0d4b-0097-4790-bc83-aa0787e83721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670790162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.1670790162
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.3408140652
Short name T486
Test name
Test status
Simulation time 481399022788 ps
CPU time 281.5 seconds
Started Jul 10 06:15:55 PM PDT 24
Finished Jul 10 06:20:39 PM PDT 24
Peak memory 201940 kb
Host smart-b4a1c6f1-b1a0-4f5d-9f27-878518e2d12c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408140652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.3408140652
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3174003952
Short name T327
Test name
Test status
Simulation time 378498578678 ps
CPU time 644.17 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:26:52 PM PDT 24
Peak memory 201916 kb
Host smart-83b895a7-8f1e-41aa-8d3b-3463c2e7d966
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174003952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3174003952
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.2495103313
Short name T628
Test name
Test status
Simulation time 203399039243 ps
CPU time 117.97 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:18:00 PM PDT 24
Peak memory 201880 kb
Host smart-388eef79-1eff-46dc-8563-3d3083f9b11b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495103313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13
.adc_ctrl_filters_wakeup_fixed.2495103313
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.3495369130
Short name T656
Test name
Test status
Simulation time 79116736019 ps
CPU time 453.4 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:23:41 PM PDT 24
Peak memory 202224 kb
Host smart-06c71b98-b283-45b8-a8af-0720d11daea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495369130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.3495369130
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.3340521679
Short name T681
Test name
Test status
Simulation time 41706505294 ps
CPU time 44.96 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:16:37 PM PDT 24
Peak memory 201696 kb
Host smart-55133e06-0320-439f-84a1-e9367986e309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340521679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.3340521679
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.4173288825
Short name T478
Test name
Test status
Simulation time 3313177356 ps
CPU time 2.61 seconds
Started Jul 10 06:16:10 PM PDT 24
Finished Jul 10 06:16:15 PM PDT 24
Peak memory 201724 kb
Host smart-bace4e22-856d-4002-b32b-15756501dd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173288825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.4173288825
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.968228568
Short name T707
Test name
Test status
Simulation time 5647540916 ps
CPU time 2.36 seconds
Started Jul 10 06:16:15 PM PDT 24
Finished Jul 10 06:16:20 PM PDT 24
Peak memory 201744 kb
Host smart-42a3b6d3-dcc0-43e9-b7b0-811bc700f3fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968228568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.968228568
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.475666991
Short name T301
Test name
Test status
Simulation time 87603321125 ps
CPU time 51.69 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:16:49 PM PDT 24
Peak memory 210136 kb
Host smart-bc05a410-e6ac-405f-b5c6-d2df619391c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475666991 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.475666991
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.3777122740
Short name T542
Test name
Test status
Simulation time 507497290 ps
CPU time 1.19 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:16:06 PM PDT 24
Peak memory 201680 kb
Host smart-dbe0b871-dc69-4f77-92d6-62bb6397ebd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777122740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.3777122740
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2815051110
Short name T571
Test name
Test status
Simulation time 170332359299 ps
CPU time 388.87 seconds
Started Jul 10 06:15:48 PM PDT 24
Finished Jul 10 06:22:20 PM PDT 24
Peak memory 201916 kb
Host smart-39e2c1c6-df4a-4158-b14e-3ff8e091b09c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815051110 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2815051110
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.577914256
Short name T250
Test name
Test status
Simulation time 337360523298 ps
CPU time 197.67 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:19:13 PM PDT 24
Peak memory 201888 kb
Host smart-64563585-2951-4863-b9c7-2937f90c9816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577914256 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.577914256
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.4114573782
Short name T537
Test name
Test status
Simulation time 334689432616 ps
CPU time 688.57 seconds
Started Jul 10 06:16:12 PM PDT 24
Finished Jul 10 06:27:43 PM PDT 24
Peak memory 201788 kb
Host smart-127b25be-4889-4fc4-bb59-3fba121dee30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114573782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interru
pt_fixed.4114573782
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.1858805408
Short name T277
Test name
Test status
Simulation time 487225360142 ps
CPU time 930.37 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:31:33 PM PDT 24
Peak memory 201960 kb
Host smart-b2a2744e-94fd-4ec5-a7b8-ee95ca5c77a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858805408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.1858805408
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.241773796
Short name T663
Test name
Test status
Simulation time 164178630591 ps
CPU time 181.76 seconds
Started Jul 10 06:16:08 PM PDT 24
Finished Jul 10 06:19:11 PM PDT 24
Peak memory 201900 kb
Host smart-28025eef-65b0-4218-a27e-2d44137c75dd
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=241773796 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.241773796
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.320685451
Short name T255
Test name
Test status
Simulation time 422835395477 ps
CPU time 238.91 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:19:57 PM PDT 24
Peak memory 201928 kb
Host smart-f4e9b068-2295-449f-ac92-072abf7246fd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320685451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_
wakeup.320685451
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2968934142
Short name T457
Test name
Test status
Simulation time 408099965616 ps
CPU time 969.49 seconds
Started Jul 10 06:16:21 PM PDT 24
Finished Jul 10 06:32:32 PM PDT 24
Peak memory 201892 kb
Host smart-148a7119-1400-4571-b2dc-483c09cd44a1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968934142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2968934142
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.3898356935
Short name T197
Test name
Test status
Simulation time 74209499141 ps
CPU time 262.72 seconds
Started Jul 10 06:16:03 PM PDT 24
Finished Jul 10 06:20:28 PM PDT 24
Peak memory 202260 kb
Host smart-7a169536-b956-4777-85d4-35302c6c20d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898356935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.3898356935
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.2881615472
Short name T600
Test name
Test status
Simulation time 31201710213 ps
CPU time 70.43 seconds
Started Jul 10 06:15:48 PM PDT 24
Finished Jul 10 06:17:01 PM PDT 24
Peak memory 201680 kb
Host smart-1f946471-fb28-4adf-a50f-61b488920d91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881615472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.2881615472
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.103860788
Short name T363
Test name
Test status
Simulation time 3034076964 ps
CPU time 2.03 seconds
Started Jul 10 06:15:52 PM PDT 24
Finished Jul 10 06:15:56 PM PDT 24
Peak memory 201680 kb
Host smart-33ed780a-36dc-45b6-bfed-8ba8788b831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103860788 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.103860788
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.1735816030
Short name T712
Test name
Test status
Simulation time 6034156540 ps
CPU time 3.62 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:16:04 PM PDT 24
Peak memory 201676 kb
Host smart-bc2ee3e8-bc79-4c1b-93fa-7bd563acc686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735816030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.1735816030
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.3043460284
Short name T585
Test name
Test status
Simulation time 171235968866 ps
CPU time 123.18 seconds
Started Jul 10 06:15:55 PM PDT 24
Finished Jul 10 06:18:00 PM PDT 24
Peak memory 201896 kb
Host smart-d12ca17d-fed8-432f-b9bc-1a86c04bbff2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043460284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.3043460284
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2856187200
Short name T583
Test name
Test status
Simulation time 168992807603 ps
CPU time 171.01 seconds
Started Jul 10 06:16:07 PM PDT 24
Finished Jul 10 06:19:00 PM PDT 24
Peak memory 210296 kb
Host smart-baf00a49-440e-4790-a1bf-c720aee89b54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856187200 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2856187200
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.2558483616
Short name T480
Test name
Test status
Simulation time 318050172 ps
CPU time 1.08 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:15:57 PM PDT 24
Peak memory 201628 kb
Host smart-b5f82264-b630-43fb-9a23-f595abf83ae6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558483616 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.2558483616
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.773893238
Short name T654
Test name
Test status
Simulation time 180672843687 ps
CPU time 433.75 seconds
Started Jul 10 06:15:52 PM PDT 24
Finished Jul 10 06:23:08 PM PDT 24
Peak memory 201884 kb
Host smart-09d7ede8-4e44-485d-811e-c3bc65445fd5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773893238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gati
ng.773893238
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.1330876536
Short name T217
Test name
Test status
Simulation time 321049494280 ps
CPU time 140.34 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:18:23 PM PDT 24
Peak memory 201964 kb
Host smart-fab9687a-c437-450c-9f22-04459f5bdad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330876536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.1330876536
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.896981526
Short name T649
Test name
Test status
Simulation time 332312494570 ps
CPU time 166.96 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:18:47 PM PDT 24
Peak memory 201956 kb
Host smart-61570026-8ac6-45f2-acc0-7d8a2041bc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896981526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.896981526
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.355400547
Short name T362
Test name
Test status
Simulation time 483508005301 ps
CPU time 279.29 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:20:39 PM PDT 24
Peak memory 201876 kb
Host smart-092c2aea-2132-4572-8447-4122a0fc57c6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=355400547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrup
t_fixed.355400547
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.1666654932
Short name T287
Test name
Test status
Simulation time 334009610379 ps
CPU time 587.19 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:25:38 PM PDT 24
Peak memory 201964 kb
Host smart-1b8c2ae1-3d95-4317-b5df-c08a65742803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666654932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.1666654932
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.776738396
Short name T473
Test name
Test status
Simulation time 481834145311 ps
CPU time 1092.06 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:34:05 PM PDT 24
Peak memory 201876 kb
Host smart-c73c3115-34c5-4a56-b300-39f23d965893
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=776738396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fixe
d.776738396
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.3318141314
Short name T603
Test name
Test status
Simulation time 394068820622 ps
CPU time 822.88 seconds
Started Jul 10 06:16:07 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 201892 kb
Host smart-fcf88e54-775c-4831-bbc9-8b9dce533ae8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318141314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15
.adc_ctrl_filters_wakeup_fixed.3318141314
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1286615417
Short name T447
Test name
Test status
Simulation time 29936071988 ps
CPU time 35.31 seconds
Started Jul 10 06:15:57 PM PDT 24
Finished Jul 10 06:16:34 PM PDT 24
Peak memory 201696 kb
Host smart-0ae1e621-74be-4b42-be57-e60f0c40920b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286615417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1286615417
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.2232724161
Short name T738
Test name
Test status
Simulation time 3071047262 ps
CPU time 7.56 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:16:16 PM PDT 24
Peak memory 201692 kb
Host smart-a7d3e07f-0165-41d1-9102-6f0b7b3702a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232724161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.2232724161
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3388370963
Short name T688
Test name
Test status
Simulation time 5835313969 ps
CPU time 7.01 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:16:05 PM PDT 24
Peak memory 201688 kb
Host smart-6621ec22-a1c4-4793-87fb-31c37fcdd708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388370963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3388370963
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.174544714
Short name T723
Test name
Test status
Simulation time 346198559496 ps
CPU time 211.01 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:19:34 PM PDT 24
Peak memory 201900 kb
Host smart-13bda788-8e97-47d8-b89a-e9fcd9b6ad02
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174544714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all.
174544714
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.945091259
Short name T18
Test name
Test status
Simulation time 205772090885 ps
CPU time 223.83 seconds
Started Jul 10 06:15:57 PM PDT 24
Finished Jul 10 06:19:43 PM PDT 24
Peak memory 210552 kb
Host smart-15ca3f99-3aa0-4d5c-a465-1fefd730443f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945091259 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.945091259
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.4135580749
Short name T714
Test name
Test status
Simulation time 363996772 ps
CPU time 1.43 seconds
Started Jul 10 06:16:07 PM PDT 24
Finished Jul 10 06:16:10 PM PDT 24
Peak memory 201652 kb
Host smart-a319f1a0-7c28-49cc-bd2b-17092e6c0c19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135580749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.4135580749
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.4167081719
Short name T179
Test name
Test status
Simulation time 559747443996 ps
CPU time 173.63 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:18:57 PM PDT 24
Peak memory 201908 kb
Host smart-9970e7e3-8df3-4f14-b26d-2d87cbe45cad
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167081719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.4167081719
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.787818350
Short name T514
Test name
Test status
Simulation time 156772746215 ps
CPU time 359.7 seconds
Started Jul 10 06:16:07 PM PDT 24
Finished Jul 10 06:22:09 PM PDT 24
Peak memory 201904 kb
Host smart-18762097-ac15-41af-907f-765f7bc08ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787818350 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.787818350
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.3701084351
Short name T488
Test name
Test status
Simulation time 161605382147 ps
CPU time 101.36 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:17:33 PM PDT 24
Peak memory 201952 kb
Host smart-7d9713e9-8854-4b06-8172-2ed5684a686f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701084351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.3701084351
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.2180019079
Short name T492
Test name
Test status
Simulation time 333646157576 ps
CPU time 177.08 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:18:57 PM PDT 24
Peak memory 201888 kb
Host smart-a901caa5-1771-4021-b6b4-4e337c57e011
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180019079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.2180019079
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.3465448825
Short name T730
Test name
Test status
Simulation time 157437085357 ps
CPU time 376.49 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:22:23 PM PDT 24
Peak memory 201892 kb
Host smart-0123cde7-d9a4-41cd-b941-18a949283c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465448825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.3465448825
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.2600990380
Short name T788
Test name
Test status
Simulation time 489321062809 ps
CPU time 217.45 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:19:46 PM PDT 24
Peak memory 201960 kb
Host smart-21ac1a9e-0838-4e79-b828-5f1e0828b81d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600990380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.2600990380
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2965291797
Short name T110
Test name
Test status
Simulation time 384995410418 ps
CPU time 269.69 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:20:21 PM PDT 24
Peak memory 201960 kb
Host smart-1fc17ea8-a65a-4b11-b7b5-c4598b664555
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965291797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2965291797
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.1605334105
Short name T528
Test name
Test status
Simulation time 585680831419 ps
CPU time 1268.61 seconds
Started Jul 10 06:15:51 PM PDT 24
Finished Jul 10 06:37:02 PM PDT 24
Peak memory 201892 kb
Host smart-33178f1e-2150-492c-8996-252d78fc6b79
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605334105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.1605334105
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.3170757966
Short name T345
Test name
Test status
Simulation time 81787131174 ps
CPU time 362.16 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:22:06 PM PDT 24
Peak memory 202260 kb
Host smart-842404c7-d32a-4d7a-a80d-f3bc074e2114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170757966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.3170757966
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.1943715050
Short name T352
Test name
Test status
Simulation time 24902415541 ps
CPU time 29.52 seconds
Started Jul 10 06:15:55 PM PDT 24
Finished Jul 10 06:16:26 PM PDT 24
Peak memory 201680 kb
Host smart-3f6208b4-c6de-44ab-96ad-ec40ddf39923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943715050 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.1943715050
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.1283750400
Short name T667
Test name
Test status
Simulation time 5171226810 ps
CPU time 4.17 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:15:59 PM PDT 24
Peak memory 201700 kb
Host smart-3eec2b81-458a-4da6-8acc-24bf49f16a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283750400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.1283750400
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.1840199607
Short name T381
Test name
Test status
Simulation time 5645500210 ps
CPU time 14.93 seconds
Started Jul 10 06:16:15 PM PDT 24
Finished Jul 10 06:16:32 PM PDT 24
Peak memory 201640 kb
Host smart-67bcbcc0-d7f4-4379-bc90-b63913b73573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840199607 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.1840199607
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.425405667
Short name T26
Test name
Test status
Simulation time 416802922664 ps
CPU time 895.34 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:31:02 PM PDT 24
Peak memory 202224 kb
Host smart-6ded3c77-097b-4d1b-b22e-142d7ade6713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425405667 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
425405667
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.3498208839
Short name T443
Test name
Test status
Simulation time 367916451 ps
CPU time 0.8 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:16:08 PM PDT 24
Peak memory 201592 kb
Host smart-d79083c7-21a6-4619-9609-780fa823c60e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498208839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.3498208839
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1235795954
Short name T685
Test name
Test status
Simulation time 163278704413 ps
CPU time 177.98 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:18:53 PM PDT 24
Peak memory 201900 kb
Host smart-2965ab7d-b7d0-4531-88fa-350b10037eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235795954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1235795954
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.116103042
Short name T156
Test name
Test status
Simulation time 488289432524 ps
CPU time 207.4 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:19:34 PM PDT 24
Peak memory 201992 kb
Host smart-52aa70cd-4c4a-494f-bb57-436520bfa9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116103042 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.116103042
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.2755564072
Short name T425
Test name
Test status
Simulation time 330672230246 ps
CPU time 728.26 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:28:08 PM PDT 24
Peak memory 201864 kb
Host smart-297b4d88-1966-46d7-ba21-5a0529a35fc5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755564072 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.2755564072
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.1351420033
Short name T589
Test name
Test status
Simulation time 485535806765 ps
CPU time 511.04 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:24:34 PM PDT 24
Peak memory 201912 kb
Host smart-75edc7d1-66b0-4bd4-b374-7aea30fa32f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351420033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.1351420033
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.753424729
Short name T624
Test name
Test status
Simulation time 320112178488 ps
CPU time 220.8 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:19:36 PM PDT 24
Peak memory 201880 kb
Host smart-70884bf7-f8b2-4713-ac5f-a8e5e4b043b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=753424729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fixe
d.753424729
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.3308705849
Short name T191
Test name
Test status
Simulation time 532100558835 ps
CPU time 1200.77 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:36:03 PM PDT 24
Peak memory 201896 kb
Host smart-2d433d08-2328-4b2a-a3ea-b2caa7d3da73
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3308705849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.3308705849
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.2186273396
Short name T771
Test name
Test status
Simulation time 598631112054 ps
CPU time 364.5 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:22:11 PM PDT 24
Peak memory 201956 kb
Host smart-562c9853-0aef-4415-9d46-8204df00130e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186273396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17
.adc_ctrl_filters_wakeup_fixed.2186273396
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.3321688324
Short name T9
Test name
Test status
Simulation time 122242735359 ps
CPU time 633.6 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:26:30 PM PDT 24
Peak memory 202268 kb
Host smart-30a4ed21-1058-4438-bc7d-47ca15fdaa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321688324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.3321688324
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.1869461274
Short name T750
Test name
Test status
Simulation time 32205313976 ps
CPU time 69.83 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:17:05 PM PDT 24
Peak memory 201704 kb
Host smart-90e203c8-b6e4-4875-a032-df01f28fe977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869461274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.1869461274
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.961494235
Short name T549
Test name
Test status
Simulation time 5140904229 ps
CPU time 3.69 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:16:10 PM PDT 24
Peak memory 201688 kb
Host smart-ea033733-c19e-4d5d-a3d3-8ad591d894f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961494235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.961494235
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.2638376328
Short name T534
Test name
Test status
Simulation time 6198665482 ps
CPU time 13.49 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:16:22 PM PDT 24
Peak memory 201640 kb
Host smart-5597b782-6e46-40f5-b5d4-7b494abeef8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638376328 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.2638376328
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2174157022
Short name T773
Test name
Test status
Simulation time 43678866531 ps
CPU time 50.13 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:16:57 PM PDT 24
Peak memory 201684 kb
Host smart-ca945b8c-a6c6-4398-a6bd-ec7b78de00a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174157022 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2174157022
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.1173376647
Short name T479
Test name
Test status
Simulation time 98501011215 ps
CPU time 150.81 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:18:31 PM PDT 24
Peak memory 217688 kb
Host smart-48556559-1b55-401a-86a7-1c37e4904e70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173376647 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.1173376647
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.95877699
Short name T642
Test name
Test status
Simulation time 382524187 ps
CPU time 0.86 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:16:01 PM PDT 24
Peak memory 201648 kb
Host smart-27f14dd3-974f-4d3b-b0a5-0fe7d6f1263b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95877699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.95877699
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2516043650
Short name T748
Test name
Test status
Simulation time 187848537373 ps
CPU time 34.47 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:16:37 PM PDT 24
Peak memory 201968 kb
Host smart-1a1bf1c9-b87a-4f1d-bb28-5d79d74ae85a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516043650 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2516043650
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.1293610952
Short name T358
Test name
Test status
Simulation time 165836771547 ps
CPU time 384.18 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:22:32 PM PDT 24
Peak memory 201816 kb
Host smart-e3cc3c2d-bb9c-4cbf-9bac-af1b0a756b3f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293610952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.1293610952
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4138172874
Short name T406
Test name
Test status
Simulation time 329651897545 ps
CPU time 173.15 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:18:48 PM PDT 24
Peak memory 201800 kb
Host smart-0196fe8f-7b44-41bb-8377-36e2a0d5f6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138172874 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4138172874
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.1996807012
Short name T359
Test name
Test status
Simulation time 175688988479 ps
CPU time 52.46 seconds
Started Jul 10 06:15:52 PM PDT 24
Finished Jul 10 06:16:47 PM PDT 24
Peak memory 201872 kb
Host smart-c190c3bd-e1b5-4674-8af4-500a2089f219
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996807012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fix
ed.1996807012
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.178965608
Short name T33
Test name
Test status
Simulation time 171768513939 ps
CPU time 342.91 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:21:41 PM PDT 24
Peak memory 201952 kb
Host smart-edd3d32d-aba3-408c-b1e2-c82a66628d45
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178965608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.178965608
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.3370721719
Short name T82
Test name
Test status
Simulation time 600400448688 ps
CPU time 1330.78 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:38:15 PM PDT 24
Peak memory 201884 kb
Host smart-10d6742c-7bf3-4a74-bd58-cd28f1348999
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370721719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.3370721719
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.4285118655
Short name T341
Test name
Test status
Simulation time 145167118948 ps
CPU time 719.09 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:27:55 PM PDT 24
Peak memory 202260 kb
Host smart-88a0382e-1e31-448d-8def-564635b70b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285118655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.4285118655
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2853300777
Short name T539
Test name
Test status
Simulation time 36381755459 ps
CPU time 16.18 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:16:24 PM PDT 24
Peak memory 201696 kb
Host smart-d4a1fea0-70df-4dbc-80ed-a177828eca08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853300777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2853300777
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.939922053
Short name T466
Test name
Test status
Simulation time 3977454794 ps
CPU time 5.3 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:16:06 PM PDT 24
Peak memory 201692 kb
Host smart-c728299d-4e60-40f0-932f-8fb9ec35c79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939922053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.939922053
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.1985129112
Short name T741
Test name
Test status
Simulation time 5743824889 ps
CPU time 2.82 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:16:02 PM PDT 24
Peak memory 201688 kb
Host smart-5ff545be-de88-4d0e-8ceb-036eec5b730f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985129112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.1985129112
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.1981904474
Short name T319
Test name
Test status
Simulation time 22402900704 ps
CPU time 49.43 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:16:46 PM PDT 24
Peak memory 210224 kb
Host smart-d87f307a-90b9-4e72-8d7f-166ceb9b24bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981904474 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.1981904474
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.2611103314
Short name T565
Test name
Test status
Simulation time 324583470 ps
CPU time 1.34 seconds
Started Jul 10 06:16:10 PM PDT 24
Finished Jul 10 06:16:14 PM PDT 24
Peak memory 201640 kb
Host smart-6a56d60a-d575-4c43-a14c-9575a2405f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611103314 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.2611103314
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.2262297505
Short name T247
Test name
Test status
Simulation time 524416410678 ps
CPU time 402.46 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:22:44 PM PDT 24
Peak memory 201888 kb
Host smart-f120a951-2738-4c86-9a77-b6e081c2d03a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262297505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.2262297505
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3956085147
Short name T219
Test name
Test status
Simulation time 163910803980 ps
CPU time 198.24 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:19:18 PM PDT 24
Peak memory 201956 kb
Host smart-68b2a844-e23f-4873-9246-384ff234085b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956085147 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3956085147
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.3902696159
Short name T378
Test name
Test status
Simulation time 328187336149 ps
CPU time 803.7 seconds
Started Jul 10 06:16:08 PM PDT 24
Finished Jul 10 06:29:34 PM PDT 24
Peak memory 201880 kb
Host smart-7af21588-1050-4f15-842c-2982353ff232
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902696159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.3902696159
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.2742487427
Short name T146
Test name
Test status
Simulation time 160073352642 ps
CPU time 73.28 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:17:11 PM PDT 24
Peak memory 201960 kb
Host smart-0a17bb5b-570e-4dae-a7ad-199ce8cb0088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742487427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.2742487427
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.4063182269
Short name T451
Test name
Test status
Simulation time 487810576845 ps
CPU time 559.6 seconds
Started Jul 10 06:15:54 PM PDT 24
Finished Jul 10 06:25:16 PM PDT 24
Peak memory 201880 kb
Host smart-c06a0a73-d436-4093-851d-5726d92b691c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063182269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fix
ed.4063182269
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.2799866915
Short name T577
Test name
Test status
Simulation time 194149234187 ps
CPU time 443.57 seconds
Started Jul 10 06:15:55 PM PDT 24
Finished Jul 10 06:23:21 PM PDT 24
Peak memory 201912 kb
Host smart-0994b505-915f-4058-9075-9e8a436ef76d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799866915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters
_wakeup.2799866915
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.3815784386
Short name T161
Test name
Test status
Simulation time 589323747780 ps
CPU time 289.28 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:20:51 PM PDT 24
Peak memory 201908 kb
Host smart-2a9c1cdd-7e5b-40c7-942a-12e329cba48d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815784386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.3815784386
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.28348687
Short name T389
Test name
Test status
Simulation time 98164378909 ps
CPU time 323.4 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:21:25 PM PDT 24
Peak memory 202276 kb
Host smart-eec946e5-61fa-4b2f-89d3-67c0cb43c478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28348687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.28348687
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.1388839436
Short name T482
Test name
Test status
Simulation time 45667197603 ps
CPU time 106.01 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:18:06 PM PDT 24
Peak memory 201696 kb
Host smart-6b6bfd12-ccd4-4bfc-8c9d-e9199f9bbfa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388839436 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.1388839436
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.3014013021
Short name T660
Test name
Test status
Simulation time 3625617084 ps
CPU time 9.23 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:16:12 PM PDT 24
Peak memory 201684 kb
Host smart-29218045-c52d-4a57-a9be-8317ceeeb527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014013021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.3014013021
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.3756039933
Short name T438
Test name
Test status
Simulation time 6041212721 ps
CPU time 15.44 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:16:18 PM PDT 24
Peak memory 201640 kb
Host smart-6697ded1-3a35-4afd-8753-2970818a85a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756039933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.3756039933
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.423930808
Short name T544
Test name
Test status
Simulation time 93744619322 ps
CPU time 339.56 seconds
Started Jul 10 06:16:00 PM PDT 24
Finished Jul 10 06:21:42 PM PDT 24
Peak memory 210356 kb
Host smart-377b3b4b-bdea-4274-b56f-3cf4225a3809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423930808 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
423930808
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.1234923848
Short name T682
Test name
Test status
Simulation time 236297494053 ps
CPU time 184.78 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:19:21 PM PDT 24
Peak memory 210400 kb
Host smart-248c3cac-2f63-4a20-909f-fedbc4eb608b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234923848 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.1234923848
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2740438951
Short name T484
Test name
Test status
Simulation time 334744415461 ps
CPU time 361.89 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:21:50 PM PDT 24
Peak memory 201944 kb
Host smart-95de5568-08cb-4ecd-88d3-253a8afa812d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740438951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2740438951
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2773370537
Short name T12
Test name
Test status
Simulation time 161298023836 ps
CPU time 76.68 seconds
Started Jul 10 06:15:30 PM PDT 24
Finished Jul 10 06:16:48 PM PDT 24
Peak memory 201888 kb
Host smart-23081642-9c08-422b-b1bf-7c10b111d106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773370537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2773370537
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.1891102775
Short name T770
Test name
Test status
Simulation time 496850561015 ps
CPU time 1064.14 seconds
Started Jul 10 06:15:13 PM PDT 24
Finished Jul 10 06:33:00 PM PDT 24
Peak memory 201864 kb
Host smart-80a59b9b-d3e6-48a0-a84b-b4e849490926
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891102775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.1891102775
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.1609046643
Short name T138
Test name
Test status
Simulation time 486482070387 ps
CPU time 1134.49 seconds
Started Jul 10 06:15:26 PM PDT 24
Finished Jul 10 06:34:22 PM PDT 24
Peak memory 201888 kb
Host smart-3af3f35a-ffb6-4395-84a4-161b44abba45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609046643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.1609046643
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1111677968
Short name T550
Test name
Test status
Simulation time 167160333823 ps
CPU time 315.16 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:20:45 PM PDT 24
Peak memory 201888 kb
Host smart-2cabec35-44f6-43f8-8b44-8a21359b1764
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111677968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1111677968
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.1534939007
Short name T320
Test name
Test status
Simulation time 195550217611 ps
CPU time 438.28 seconds
Started Jul 10 06:15:33 PM PDT 24
Finished Jul 10 06:22:53 PM PDT 24
Peak memory 201992 kb
Host smart-72f1799c-5b80-42bd-ad03-a61b57f79582
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534939007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.1534939007
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.747332678
Short name T158
Test name
Test status
Simulation time 599053236398 ps
CPU time 1237.11 seconds
Started Jul 10 06:15:20 PM PDT 24
Finished Jul 10 06:36:00 PM PDT 24
Peak memory 201920 kb
Host smart-96171091-aab2-403f-a3e6-c486647d738b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747332678 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.a
dc_ctrl_filters_wakeup_fixed.747332678
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.166599429
Short name T209
Test name
Test status
Simulation time 91155747747 ps
CPU time 481.76 seconds
Started Jul 10 06:15:40 PM PDT 24
Finished Jul 10 06:23:44 PM PDT 24
Peak memory 202276 kb
Host smart-80d2ebc4-a273-47b3-9d7b-08eb9ac5317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166599429 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.166599429
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.4092889146
Short name T462
Test name
Test status
Simulation time 36133624208 ps
CPU time 5.37 seconds
Started Jul 10 06:15:28 PM PDT 24
Finished Jul 10 06:15:35 PM PDT 24
Peak memory 201704 kb
Host smart-2c0cd4fa-f477-4b57-ba07-76559939f8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092889146 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.4092889146
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.2237140930
Short name T436
Test name
Test status
Simulation time 3566071404 ps
CPU time 2.63 seconds
Started Jul 10 06:15:32 PM PDT 24
Finished Jul 10 06:15:36 PM PDT 24
Peak memory 201692 kb
Host smart-faba050b-384a-4a8d-843a-b7eac3bcb1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237140930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.2237140930
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.3637094619
Short name T78
Test name
Test status
Simulation time 8093089664 ps
CPU time 4.89 seconds
Started Jul 10 06:15:39 PM PDT 24
Finished Jul 10 06:15:46 PM PDT 24
Peak memory 218180 kb
Host smart-6e03f030-7baa-4fd6-bb02-2040c9ad9a06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637094619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.3637094619
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.4061291927
Short name T371
Test name
Test status
Simulation time 5975720714 ps
CPU time 4.19 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:15:34 PM PDT 24
Peak memory 201616 kb
Host smart-b534e8fc-41b7-41c8-adbc-72fca8c1a8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4061291927 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.4061291927
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1566761304
Short name T784
Test name
Test status
Simulation time 822000333437 ps
CPU time 1769.13 seconds
Started Jul 10 06:15:32 PM PDT 24
Finished Jul 10 06:45:07 PM PDT 24
Peak memory 201880 kb
Host smart-37e10aad-063f-4afd-8f57-abcaebd745fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566761304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1566761304
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.3117288671
Short name T527
Test name
Test status
Simulation time 118818720541 ps
CPU time 58.98 seconds
Started Jul 10 06:15:22 PM PDT 24
Finished Jul 10 06:16:23 PM PDT 24
Peak memory 210224 kb
Host smart-4e5650f3-468d-4372-a51a-011bff83e1d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117288671 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.3117288671
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.1590143357
Short name T426
Test name
Test status
Simulation time 338367967 ps
CPU time 0.85 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:16:05 PM PDT 24
Peak memory 201640 kb
Host smart-cac376a3-5dee-4afe-a72d-bd6f928af96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590143357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.1590143357
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.4133787779
Short name T226
Test name
Test status
Simulation time 171269363793 ps
CPU time 205.38 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:19:47 PM PDT 24
Peak memory 201888 kb
Host smart-272f60d8-d606-43ca-9092-9db87be56c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133787779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.4133787779
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2075929593
Short name T683
Test name
Test status
Simulation time 333909445273 ps
CPU time 796.34 seconds
Started Jul 10 06:15:56 PM PDT 24
Finished Jul 10 06:29:15 PM PDT 24
Peak memory 201892 kb
Host smart-d87d9ff0-2279-4d8f-956e-c79519fa6158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075929593 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2075929593
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2621712384
Short name T664
Test name
Test status
Simulation time 166523345944 ps
CPU time 355.95 seconds
Started Jul 10 06:16:17 PM PDT 24
Finished Jul 10 06:22:15 PM PDT 24
Peak memory 201848 kb
Host smart-ba79a484-8a59-416e-8696-74fc127bef08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621712384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2621712384
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.3140166696
Short name T272
Test name
Test status
Simulation time 320938272656 ps
CPU time 709.52 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:27:58 PM PDT 24
Peak memory 201952 kb
Host smart-7cd3298e-5bb1-4590-bfc4-1af256ac8f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140166696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.3140166696
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.1530385354
Short name T643
Test name
Test status
Simulation time 478498536130 ps
CPU time 831.68 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:29:52 PM PDT 24
Peak memory 201944 kb
Host smart-9519b2f8-1438-4933-bc03-3472ff7c8f47
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530385354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.1530385354
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.795451336
Short name T304
Test name
Test status
Simulation time 164274218260 ps
CPU time 85.92 seconds
Started Jul 10 06:16:03 PM PDT 24
Finished Jul 10 06:17:32 PM PDT 24
Peak memory 201964 kb
Host smart-a678f237-8319-46d8-8429-d5af46b77079
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795451336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_
wakeup.795451336
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.1619837338
Short name T640
Test name
Test status
Simulation time 630492589857 ps
CPU time 349.61 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:22:06 PM PDT 24
Peak memory 201876 kb
Host smart-725318b7-61f4-4e31-9ecf-fc94d1e6609f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619837338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.1619837338
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.3659123941
Short name T701
Test name
Test status
Simulation time 127922682008 ps
CPU time 680.28 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:27:20 PM PDT 24
Peak memory 202208 kb
Host smart-81e78574-4179-4d91-b2b3-5034bc84a486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659123941 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.3659123941
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.3768821531
Short name T648
Test name
Test status
Simulation time 39701633994 ps
CPU time 43.79 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:16:50 PM PDT 24
Peak memory 201688 kb
Host smart-f669fd09-ab2c-4342-818c-9f3563e6f089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768821531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.3768821531
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.88049945
Short name T58
Test name
Test status
Simulation time 5081419589 ps
CPU time 13.22 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:16:20 PM PDT 24
Peak memory 201712 kb
Host smart-406762ec-0267-4a56-9e7a-f406b32d2f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88049945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.88049945
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.282479697
Short name T570
Test name
Test status
Simulation time 5472756626 ps
CPU time 13.57 seconds
Started Jul 10 06:16:01 PM PDT 24
Finished Jul 10 06:16:17 PM PDT 24
Peak memory 201692 kb
Host smart-6f757990-828f-40fc-9224-4a8a48bf5440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282479697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.282479697
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.3241331453
Short name T106
Test name
Test status
Simulation time 355361203126 ps
CPU time 123.7 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:18:11 PM PDT 24
Peak memory 201880 kb
Host smart-8ae7f70c-065c-400f-8ded-9fa450ca0853
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241331453 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.3241331453
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.648584989
Short name T112
Test name
Test status
Simulation time 681340335577 ps
CPU time 556.83 seconds
Started Jul 10 06:16:12 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 217724 kb
Host smart-dec6d579-d5ff-4e46-8e95-0369027e04cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648584989 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.648584989
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.2080362292
Short name T454
Test name
Test status
Simulation time 324051639 ps
CPU time 0.94 seconds
Started Jul 10 06:16:20 PM PDT 24
Finished Jul 10 06:16:22 PM PDT 24
Peak memory 201512 kb
Host smart-ff756313-ec00-4d6f-a933-79379650076b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080362292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.2080362292
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.415632418
Short name T278
Test name
Test status
Simulation time 522656287850 ps
CPU time 1178.84 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:35:44 PM PDT 24
Peak memory 201880 kb
Host smart-c3c91d98-73ea-4956-a3ac-40390d3b092c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415632418 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gati
ng.415632418
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.1618459026
Short name T237
Test name
Test status
Simulation time 166835821550 ps
CPU time 105.91 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:18:06 PM PDT 24
Peak memory 201964 kb
Host smart-abfede96-29aa-401f-93be-dce6d6d12e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618459026 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.1618459026
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.373863112
Short name T80
Test name
Test status
Simulation time 332217486286 ps
CPU time 764.07 seconds
Started Jul 10 06:16:06 PM PDT 24
Finished Jul 10 06:28:52 PM PDT 24
Peak memory 201844 kb
Host smart-0f8266d2-7710-43d3-859f-b8e5ee667767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=373863112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrup
t_fixed.373863112
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.1320180113
Short name T639
Test name
Test status
Simulation time 327990574082 ps
CPU time 700.29 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:27:40 PM PDT 24
Peak memory 201820 kb
Host smart-7400d8cf-9944-4031-9e0f-4c0e65aac7f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320180113 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.1320180113
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.4103270559
Short name T732
Test name
Test status
Simulation time 330270489151 ps
CPU time 120.27 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:18:00 PM PDT 24
Peak memory 201932 kb
Host smart-ffa040aa-78eb-4011-9d82-17958cb515b1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103270559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.4103270559
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.1373331736
Short name T572
Test name
Test status
Simulation time 390820940394 ps
CPU time 280.19 seconds
Started Jul 10 06:15:58 PM PDT 24
Finished Jul 10 06:20:41 PM PDT 24
Peak memory 201952 kb
Host smart-780386d0-a6cd-4e04-b6a9-73831aee5411
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373331736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.1373331736
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.2300047724
Short name T718
Test name
Test status
Simulation time 70227496438 ps
CPU time 283.86 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:20:48 PM PDT 24
Peak memory 202268 kb
Host smart-114f58ce-cd69-41c8-8a30-26ea1e3b024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300047724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.2300047724
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1402582143
Short name T401
Test name
Test status
Simulation time 31457230713 ps
CPU time 20.38 seconds
Started Jul 10 06:16:13 PM PDT 24
Finished Jul 10 06:16:36 PM PDT 24
Peak memory 201684 kb
Host smart-d73d6cf8-9fdc-4969-8efe-0343f99679b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402582143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1402582143
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.1540332284
Short name T411
Test name
Test status
Simulation time 3580036647 ps
CPU time 5.12 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:16:12 PM PDT 24
Peak memory 201696 kb
Host smart-a4f996c8-a8b7-478f-82ad-f60dfdbddf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540332284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.1540332284
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.966919174
Short name T383
Test name
Test status
Simulation time 6233023076 ps
CPU time 1.99 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:16:03 PM PDT 24
Peak memory 201688 kb
Host smart-686c0a94-6536-47f3-85b9-f3f8d09c99d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966919174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.966919174
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.1067306425
Short name T421
Test name
Test status
Simulation time 198761291726 ps
CPU time 63.6 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:17:21 PM PDT 24
Peak memory 201880 kb
Host smart-505c16f4-9243-48a6-9908-2f99473136fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067306425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.1067306425
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.116629582
Short name T284
Test name
Test status
Simulation time 247799198594 ps
CPU time 43.53 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:16:59 PM PDT 24
Peak memory 210240 kb
Host smart-de34f894-849a-445e-b2c1-d9adac885b06
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116629582 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.116629582
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.3607341104
Short name T635
Test name
Test status
Simulation time 303005058 ps
CPU time 1.38 seconds
Started Jul 10 06:16:13 PM PDT 24
Finished Jul 10 06:16:16 PM PDT 24
Peak memory 201620 kb
Host smart-0e9f3e00-a4e7-4d59-9c85-197506cf45fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607341104 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.3607341104
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.651056605
Short name T275
Test name
Test status
Simulation time 362951744792 ps
CPU time 112.03 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:18:08 PM PDT 24
Peak memory 201884 kb
Host smart-e64c545c-732c-4f0c-b7fb-e608a12486e7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651056605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gati
ng.651056605
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.2756585439
Short name T328
Test name
Test status
Simulation time 174742430069 ps
CPU time 200.41 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:19:39 PM PDT 24
Peak memory 201876 kb
Host smart-66e41980-8fc2-45cd-89c9-d4b45bc345f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756585439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.2756585439
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.3810880526
Short name T711
Test name
Test status
Simulation time 336248907097 ps
CPU time 272.85 seconds
Started Jul 10 06:16:03 PM PDT 24
Finished Jul 10 06:20:38 PM PDT 24
Peak memory 201904 kb
Host smart-34690079-f5ae-48b7-b52c-0c1eacef3c28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810880526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.3810880526
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.2525852124
Short name T751
Test name
Test status
Simulation time 494390554823 ps
CPU time 194.36 seconds
Started Jul 10 06:16:10 PM PDT 24
Finished Jul 10 06:19:27 PM PDT 24
Peak memory 201864 kb
Host smart-06324c14-c623-449e-88d5-9e59691329d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525852124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interru
pt_fixed.2525852124
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.542539442
Short name T140
Test name
Test status
Simulation time 164822353859 ps
CPU time 371.29 seconds
Started Jul 10 06:16:07 PM PDT 24
Finished Jul 10 06:22:21 PM PDT 24
Peak memory 201892 kb
Host smart-b4f3cd19-9fa8-4b67-9cb8-4c4fa69fa2d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542539442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.542539442
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.761542278
Short name T467
Test name
Test status
Simulation time 162977602589 ps
CPU time 34.58 seconds
Started Jul 10 06:16:13 PM PDT 24
Finished Jul 10 06:16:50 PM PDT 24
Peak memory 201876 kb
Host smart-af89afc2-62c2-418c-acd2-86bd18fdd9a5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=761542278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fixe
d.761542278
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.3293235987
Short name T737
Test name
Test status
Simulation time 356381917957 ps
CPU time 497.31 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:24:34 PM PDT 24
Peak memory 201980 kb
Host smart-6409192a-f5f3-45f8-b856-937706a4050e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293235987 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.3293235987
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.560450143
Short name T601
Test name
Test status
Simulation time 201254906686 ps
CPU time 256.61 seconds
Started Jul 10 06:16:03 PM PDT 24
Finished Jul 10 06:20:22 PM PDT 24
Peak memory 201856 kb
Host smart-85de783b-09b4-40b1-90a9-ab13e01cfedc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560450143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.
adc_ctrl_filters_wakeup_fixed.560450143
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.614416973
Short name T786
Test name
Test status
Simulation time 69787137278 ps
CPU time 389.21 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:22:36 PM PDT 24
Peak memory 202288 kb
Host smart-e1df2f38-e79b-4bba-9d20-3598e845ee3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614416973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.614416973
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.3049924132
Short name T100
Test name
Test status
Simulation time 29600967339 ps
CPU time 14.75 seconds
Started Jul 10 06:16:10 PM PDT 24
Finished Jul 10 06:16:27 PM PDT 24
Peak memory 201720 kb
Host smart-a0c87c74-d115-418e-865a-2249815fae3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049924132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.3049924132
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3835923996
Short name T536
Test name
Test status
Simulation time 3934727021 ps
CPU time 9.19 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:16:17 PM PDT 24
Peak memory 201688 kb
Host smart-014812d9-d140-4fb9-97ab-793faf0b3d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835923996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3835923996
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.900115284
Short name T677
Test name
Test status
Simulation time 5838043186 ps
CPU time 7.66 seconds
Started Jul 10 06:16:07 PM PDT 24
Finished Jul 10 06:16:17 PM PDT 24
Peak memory 201708 kb
Host smart-5c249516-6660-4d4f-8a7c-ee4937e5afab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900115284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.900115284
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2010366643
Short name T789
Test name
Test status
Simulation time 283141324861 ps
CPU time 418.32 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:23:06 PM PDT 24
Peak memory 212816 kb
Host smart-5edc8556-97ca-4cab-b293-d1de055c7665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010366643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2010366643
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.1514211433
Short name T35
Test name
Test status
Simulation time 481401282068 ps
CPU time 247.43 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:20:14 PM PDT 24
Peak memory 217932 kb
Host smart-03f5e07c-2de0-41cd-8a08-d3f6c68bd296
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514211433 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.1514211433
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.1777999518
Short name T505
Test name
Test status
Simulation time 338756020 ps
CPU time 0.97 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:16:21 PM PDT 24
Peak memory 201632 kb
Host smart-596e358a-a556-45c4-99b3-fa33fb3ea0bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777999518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.1777999518
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.2165735170
Short name T330
Test name
Test status
Simulation time 161414967780 ps
CPU time 368.78 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:22:28 PM PDT 24
Peak memory 201944 kb
Host smart-60f7e09f-6bf4-4f0e-92b0-20f6ffce548b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165735170 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.2165735170
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.2130045559
Short name T367
Test name
Test status
Simulation time 488966154055 ps
CPU time 381.73 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:22:40 PM PDT 24
Peak memory 201852 kb
Host smart-3cd6b1f0-d196-4f35-a753-d852ad9abe86
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130045559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.2130045559
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.1112347739
Short name T569
Test name
Test status
Simulation time 327609982823 ps
CPU time 388.88 seconds
Started Jul 10 06:16:11 PM PDT 24
Finished Jul 10 06:22:42 PM PDT 24
Peak memory 201900 kb
Host smart-0264ba31-a1cb-459e-9df8-b9499818c1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112347739 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.1112347739
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.3284462909
Short name T633
Test name
Test status
Simulation time 166129585093 ps
CPU time 390.51 seconds
Started Jul 10 06:16:05 PM PDT 24
Finished Jul 10 06:22:38 PM PDT 24
Peak memory 201884 kb
Host smart-0f0e7eb6-6d0a-45a0-a195-6fb1ee860ef2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284462909 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fix
ed.3284462909
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2305288286
Short name T765
Test name
Test status
Simulation time 398797227486 ps
CPU time 438.34 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:23:38 PM PDT 24
Peak memory 201876 kb
Host smart-51992c0d-2e12-49b2-bec0-767c8d2e8653
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305288286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2305288286
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.186926709
Short name T608
Test name
Test status
Simulation time 79946464303 ps
CPU time 329.42 seconds
Started Jul 10 06:16:12 PM PDT 24
Finished Jul 10 06:21:44 PM PDT 24
Peak memory 202112 kb
Host smart-70c082ed-6dbc-4a82-b5bc-20f029aa0ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186926709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.186926709
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.1924669863
Short name T360
Test name
Test status
Simulation time 28616132421 ps
CPU time 17.54 seconds
Started Jul 10 06:16:11 PM PDT 24
Finished Jul 10 06:16:31 PM PDT 24
Peak memory 201724 kb
Host smart-88e089f9-9df7-4294-908b-df31d00f60e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924669863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.1924669863
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.98260847
Short name T390
Test name
Test status
Simulation time 4169047945 ps
CPU time 10.39 seconds
Started Jul 10 06:16:02 PM PDT 24
Finished Jul 10 06:16:14 PM PDT 24
Peak memory 201712 kb
Host smart-24dc7904-3f71-4e9c-85d0-6cda6bb83e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98260847 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.98260847
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1399304863
Short name T495
Test name
Test status
Simulation time 6071564019 ps
CPU time 14.42 seconds
Started Jul 10 06:16:04 PM PDT 24
Finished Jul 10 06:16:21 PM PDT 24
Peak memory 201688 kb
Host smart-51ea6470-c091-4703-90ca-4def7feb2a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399304863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1399304863
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.234871060
Short name T713
Test name
Test status
Simulation time 361460589227 ps
CPU time 723.14 seconds
Started Jul 10 06:16:09 PM PDT 24
Finished Jul 10 06:28:15 PM PDT 24
Peak memory 201892 kb
Host smart-4f74e213-e380-43b4-b64e-cacfeba9b2c3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234871060 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
234871060
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1606175094
Short name T296
Test name
Test status
Simulation time 222091852412 ps
CPU time 130.41 seconds
Started Jul 10 06:16:21 PM PDT 24
Finished Jul 10 06:18:32 PM PDT 24
Peak memory 210276 kb
Host smart-c22b4975-b35a-4a7b-bbf0-02aca02e37f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606175094 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1606175094
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.750406769
Short name T368
Test name
Test status
Simulation time 337221281 ps
CPU time 0.94 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:16:19 PM PDT 24
Peak memory 201640 kb
Host smart-2928fa23-1530-4bab-8699-a6065eb3dab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750406769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.750406769
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.502070321
Short name T269
Test name
Test status
Simulation time 179570880153 ps
CPU time 446.68 seconds
Started Jul 10 06:16:11 PM PDT 24
Finished Jul 10 06:23:40 PM PDT 24
Peak memory 201904 kb
Host smart-26772967-0ba6-41fc-8119-4dd044c18478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502070321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.502070321
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.1796030085
Short name T220
Test name
Test status
Simulation time 495983155319 ps
CPU time 338.91 seconds
Started Jul 10 06:16:11 PM PDT 24
Finished Jul 10 06:21:52 PM PDT 24
Peak memory 201944 kb
Host smart-45502fd1-540d-4667-82d2-fadb0ebf0b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796030085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.1796030085
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.2698783907
Short name T471
Test name
Test status
Simulation time 333534373605 ps
CPU time 192.3 seconds
Started Jul 10 06:16:09 PM PDT 24
Finished Jul 10 06:19:24 PM PDT 24
Peak memory 201860 kb
Host smart-1087fdd7-c771-4f9e-a976-9d01cea9e3a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698783907 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.2698783907
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.373427034
Short name T672
Test name
Test status
Simulation time 163571680792 ps
CPU time 179.36 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:19:18 PM PDT 24
Peak memory 201916 kb
Host smart-cb0f4757-dfce-4aba-8ab8-05e4dfab7e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373427034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.373427034
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2405034508
Short name T767
Test name
Test status
Simulation time 169822672446 ps
CPU time 83.55 seconds
Started Jul 10 06:16:27 PM PDT 24
Finished Jul 10 06:17:52 PM PDT 24
Peak memory 200844 kb
Host smart-09e4584f-9d20-4834-b132-b141d8799630
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405034508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2405034508
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.3081371955
Short name T266
Test name
Test status
Simulation time 355213388608 ps
CPU time 409.97 seconds
Started Jul 10 06:16:10 PM PDT 24
Finished Jul 10 06:23:02 PM PDT 24
Peak memory 201876 kb
Host smart-f2dc8f18-9d7e-49b3-99ae-6609188e7ea2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081371955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters
_wakeup.3081371955
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.798304220
Short name T94
Test name
Test status
Simulation time 205171727990 ps
CPU time 353.74 seconds
Started Jul 10 06:16:08 PM PDT 24
Finished Jul 10 06:22:04 PM PDT 24
Peak memory 201880 kb
Host smart-1317709c-9be8-4022-8f6b-3fb3b084a2d8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798304220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.798304220
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.4158559474
Short name T55
Test name
Test status
Simulation time 86631960599 ps
CPU time 418.8 seconds
Started Jul 10 06:16:17 PM PDT 24
Finished Jul 10 06:23:18 PM PDT 24
Peak memory 202212 kb
Host smart-57a500e4-8f01-475a-bbd6-cf5ec741bbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158559474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.4158559474
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3862892288
Short name T470
Test name
Test status
Simulation time 32845142662 ps
CPU time 37.81 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:16:56 PM PDT 24
Peak memory 201696 kb
Host smart-1500af5f-3ec1-4a34-aea4-692446fc02f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862892288 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3862892288
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.359097367
Short name T402
Test name
Test status
Simulation time 3457293706 ps
CPU time 2.71 seconds
Started Jul 10 06:16:20 PM PDT 24
Finished Jul 10 06:16:24 PM PDT 24
Peak memory 201684 kb
Host smart-5011ec8c-bf22-451b-93d5-59469f92426a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359097367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.359097367
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.1972489339
Short name T134
Test name
Test status
Simulation time 5985260949 ps
CPU time 7.8 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:16:24 PM PDT 24
Peak memory 201688 kb
Host smart-72b459a2-71d1-43f2-9c02-cd029e84bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972489339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.1972489339
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.919706481
Short name T434
Test name
Test status
Simulation time 81647638130 ps
CPU time 417.43 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:23:14 PM PDT 24
Peak memory 210400 kb
Host smart-09d55bb4-7b6c-40b2-b336-48f066f05cc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919706481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all.
919706481
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.3241799780
Short name T313
Test name
Test status
Simulation time 64629841424 ps
CPU time 127.14 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:18:28 PM PDT 24
Peak memory 210228 kb
Host smart-af53389e-6b76-48e9-ba69-7356ec7e777b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241799780 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.3241799780
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.3390490787
Short name T722
Test name
Test status
Simulation time 457801476 ps
CPU time 0.9 seconds
Started Jul 10 06:16:21 PM PDT 24
Finished Jul 10 06:16:23 PM PDT 24
Peak memory 201692 kb
Host smart-e0aa5277-2a68-4042-bfc1-fce53c445893
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390490787 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.3390490787
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2736366443
Short name T739
Test name
Test status
Simulation time 178541953172 ps
CPU time 61.35 seconds
Started Jul 10 06:16:15 PM PDT 24
Finished Jul 10 06:17:19 PM PDT 24
Peak memory 201784 kb
Host smart-ae86b029-9623-4ec1-b670-7bbf4097fbc1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736366443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2736366443
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.2081502784
Short name T152
Test name
Test status
Simulation time 501375583337 ps
CPU time 531.33 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:25:12 PM PDT 24
Peak memory 201924 kb
Host smart-d964471c-a586-42ae-b03a-fab8839ba61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081502784 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.2081502784
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.1121595561
Short name T251
Test name
Test status
Simulation time 323283054779 ps
CPU time 726.9 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:28:26 PM PDT 24
Peak memory 201892 kb
Host smart-fdf151f6-631c-4e16-9567-31082ec8d412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121595561 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.1121595561
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.1429905295
Short name T377
Test name
Test status
Simulation time 164497523358 ps
CPU time 377.9 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:22:39 PM PDT 24
Peak memory 201876 kb
Host smart-f2b66b32-90d1-4623-921d-da68c766acbe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429905295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.1429905295
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.694927666
Short name T142
Test name
Test status
Simulation time 162428425304 ps
CPU time 387.64 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:22:49 PM PDT 24
Peak memory 201920 kb
Host smart-45546d41-f414-4c3b-bee7-fa41eff2359c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694927666 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.694927666
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.1767271634
Short name T605
Test name
Test status
Simulation time 161988827006 ps
CPU time 268.31 seconds
Started Jul 10 06:16:19 PM PDT 24
Finished Jul 10 06:20:50 PM PDT 24
Peak memory 201860 kb
Host smart-962a1bb1-11cf-4fe4-b165-5b6da045987b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767271634 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.1767271634
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.1076160608
Short name T231
Test name
Test status
Simulation time 173542866785 ps
CPU time 88.23 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:17:49 PM PDT 24
Peak memory 201928 kb
Host smart-98a9553b-f5d1-4955-8667-04b967d4d241
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076160608 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.1076160608
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1202594510
Short name T746
Test name
Test status
Simulation time 428944734728 ps
CPU time 1003.78 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:33:02 PM PDT 24
Peak memory 201872 kb
Host smart-881331fc-e49d-4567-90e5-8f494d0887e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202594510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1202594510
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.658276831
Short name T208
Test name
Test status
Simulation time 123786887458 ps
CPU time 661.02 seconds
Started Jul 10 06:16:15 PM PDT 24
Finished Jul 10 06:27:19 PM PDT 24
Peak memory 202224 kb
Host smart-a16b6b69-d4ce-4e7c-8804-a1e746da56b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658276831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.658276831
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.997517581
Short name T346
Test name
Test status
Simulation time 40455757470 ps
CPU time 24.39 seconds
Started Jul 10 06:16:18 PM PDT 24
Finished Jul 10 06:16:45 PM PDT 24
Peak memory 201724 kb
Host smart-30d2cc82-2cf8-445e-8408-dd544a717925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997517581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.997517581
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.61808218
Short name T515
Test name
Test status
Simulation time 5187186225 ps
CPU time 1.64 seconds
Started Jul 10 06:16:22 PM PDT 24
Finished Jul 10 06:16:25 PM PDT 24
Peak memory 201688 kb
Host smart-654545c9-3b02-4e24-a940-bc7d7ca8d204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61808218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.61808218
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.3064390745
Short name T95
Test name
Test status
Simulation time 6062929418 ps
CPU time 15.06 seconds
Started Jul 10 06:16:14 PM PDT 24
Finished Jul 10 06:16:32 PM PDT 24
Peak memory 201672 kb
Host smart-5fcac045-270e-40ec-b98c-3425a3453636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064390745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.3064390745
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.1914225056
Short name T298
Test name
Test status
Simulation time 347668254766 ps
CPU time 772.48 seconds
Started Jul 10 06:16:22 PM PDT 24
Finished Jul 10 06:29:16 PM PDT 24
Peak memory 201876 kb
Host smart-df47887c-a521-47a6-9ffc-832cf22f25ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914225056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all
.1914225056
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.736232738
Short name T490
Test name
Test status
Simulation time 40965695906 ps
CPU time 51.07 seconds
Started Jul 10 06:16:16 PM PDT 24
Finished Jul 10 06:17:10 PM PDT 24
Peak memory 202068 kb
Host smart-f5fc2ea9-9bd8-4ca7-960d-c0205a4ae04f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736232738 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.736232738
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.4285779079
Short name T508
Test name
Test status
Simulation time 444371246 ps
CPU time 1.36 seconds
Started Jul 10 06:16:27 PM PDT 24
Finished Jul 10 06:16:30 PM PDT 24
Peak memory 201636 kb
Host smart-293ae0ea-6deb-428b-9f20-38ad335fce68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285779079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.4285779079
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3823293745
Short name T192
Test name
Test status
Simulation time 368062995464 ps
CPU time 182.75 seconds
Started Jul 10 06:16:21 PM PDT 24
Finished Jul 10 06:19:25 PM PDT 24
Peak memory 201912 kb
Host smart-600e376e-a37b-4c28-bff4-5954b7787029
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823293745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3823293745
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2998876464
Short name T281
Test name
Test status
Simulation time 226877859797 ps
CPU time 136.67 seconds
Started Jul 10 06:16:27 PM PDT 24
Finished Jul 10 06:18:45 PM PDT 24
Peak memory 201952 kb
Host smart-de84ce71-606d-4300-8951-951f37b1f7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998876464 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2998876464
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.77147451
Short name T512
Test name
Test status
Simulation time 487173844873 ps
CPU time 295.8 seconds
Started Jul 10 06:16:26 PM PDT 24
Finished Jul 10 06:21:22 PM PDT 24
Peak memory 201848 kb
Host smart-7e20f2ac-9fd4-4734-92bf-da4e2705be05
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=77147451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt
_fixed.77147451
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.2025302004
Short name T772
Test name
Test status
Simulation time 491353147781 ps
CPU time 994.51 seconds
Started Jul 10 06:16:25 PM PDT 24
Finished Jul 10 06:33:01 PM PDT 24
Peak memory 201900 kb
Host smart-75a1e47e-fa66-4ecf-be57-244478994e3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025302004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.2025302004
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.4061495868
Short name T400
Test name
Test status
Simulation time 496933545948 ps
CPU time 1211.23 seconds
Started Jul 10 06:16:21 PM PDT 24
Finished Jul 10 06:36:34 PM PDT 24
Peak memory 201880 kb
Host smart-877fb876-830a-4859-beec-344a246a485f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061495868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.4061495868
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.2750677055
Short name T513
Test name
Test status
Simulation time 599953225739 ps
CPU time 316.25 seconds
Started Jul 10 06:16:24 PM PDT 24
Finished Jul 10 06:21:41 PM PDT 24
Peak memory 201860 kb
Host smart-d78365f8-3728-4516-9317-eaf4ce611ccc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750677055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.2750677055
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.1544611931
Short name T339
Test name
Test status
Simulation time 80513740216 ps
CPU time 263.01 seconds
Started Jul 10 06:16:35 PM PDT 24
Finished Jul 10 06:20:59 PM PDT 24
Peak memory 202200 kb
Host smart-095d8415-9cb7-499f-ac9c-7d531058a866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544611931 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.1544611931
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.2978643517
Short name T697
Test name
Test status
Simulation time 35058418608 ps
CPU time 5.57 seconds
Started Jul 10 06:16:26 PM PDT 24
Finished Jul 10 06:16:33 PM PDT 24
Peak memory 201688 kb
Host smart-d5ad68f3-c6be-4be7-bebb-e7bd23a01ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978643517 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.2978643517
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.1143564930
Short name T382
Test name
Test status
Simulation time 4755470116 ps
CPU time 6.17 seconds
Started Jul 10 06:16:31 PM PDT 24
Finished Jul 10 06:16:38 PM PDT 24
Peak memory 201692 kb
Host smart-c94adf63-d82e-45cb-8327-c45523be0ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143564930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.1143564930
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.408300297
Short name T703
Test name
Test status
Simulation time 5802574098 ps
CPU time 2.24 seconds
Started Jul 10 06:16:23 PM PDT 24
Finished Jul 10 06:16:26 PM PDT 24
Peak memory 201712 kb
Host smart-e446abea-fe96-4430-bfd0-039502b43378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408300297 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.408300297
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.2219376151
Short name T669
Test name
Test status
Simulation time 1171065328768 ps
CPU time 339.33 seconds
Started Jul 10 06:16:27 PM PDT 24
Finished Jul 10 06:22:08 PM PDT 24
Peak memory 209264 kb
Host smart-92a3af61-102a-443d-af1a-57330e33fa69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219376151 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.2219376151
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2224205276
Short name T790
Test name
Test status
Simulation time 419514953 ps
CPU time 0.67 seconds
Started Jul 10 06:16:31 PM PDT 24
Finished Jul 10 06:16:32 PM PDT 24
Peak memory 201640 kb
Host smart-be0fc957-7767-4db1-bf95-3bce974520da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224205276 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2224205276
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1363429981
Short name T292
Test name
Test status
Simulation time 523752364107 ps
CPU time 1224.47 seconds
Started Jul 10 06:16:28 PM PDT 24
Finished Jul 10 06:36:54 PM PDT 24
Peak memory 201936 kb
Host smart-f38838b5-43e1-48d2-b526-515bd0181ad6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363429981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1363429981
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.1727148144
Short name T777
Test name
Test status
Simulation time 162269640502 ps
CPU time 178.55 seconds
Started Jul 10 06:16:27 PM PDT 24
Finished Jul 10 06:19:27 PM PDT 24
Peak memory 201912 kb
Host smart-608ec4de-192a-491e-905d-80285d0bdb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727148144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.1727148144
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.19958351
Short name T485
Test name
Test status
Simulation time 167854967242 ps
CPU time 99.53 seconds
Started Jul 10 06:16:32 PM PDT 24
Finished Jul 10 06:18:12 PM PDT 24
Peak memory 201900 kb
Host smart-e78e2584-491d-4f6f-b303-f7185ca6a7a2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=19958351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt
_fixed.19958351
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.1185778624
Short name T105
Test name
Test status
Simulation time 166629234750 ps
CPU time 380.85 seconds
Started Jul 10 06:16:32 PM PDT 24
Finished Jul 10 06:22:54 PM PDT 24
Peak memory 201948 kb
Host smart-27406529-0922-4eb2-ab79-9c4dd57c22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185778624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.1185778624
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.4122660370
Short name T511
Test name
Test status
Simulation time 167466622942 ps
CPU time 81.77 seconds
Started Jul 10 06:16:31 PM PDT 24
Finished Jul 10 06:17:54 PM PDT 24
Peak memory 201912 kb
Host smart-b62d3df2-bdc7-44c5-8397-d9bf4e2d23b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122660370 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.4122660370
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.3699630615
Short name T163
Test name
Test status
Simulation time 179743956613 ps
CPU time 116.57 seconds
Started Jul 10 06:16:29 PM PDT 24
Finished Jul 10 06:18:26 PM PDT 24
Peak memory 201968 kb
Host smart-0de78468-a340-4305-96ee-eb63cf2dd7f4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699630615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.3699630615
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.1008672888
Short name T445
Test name
Test status
Simulation time 403623333116 ps
CPU time 866.97 seconds
Started Jul 10 06:16:28 PM PDT 24
Finished Jul 10 06:30:56 PM PDT 24
Peak memory 201884 kb
Host smart-0ba7cda9-1a5f-4f01-97cd-49844323ad7f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008672888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.1008672888
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1121289989
Short name T702
Test name
Test status
Simulation time 93034873875 ps
CPU time 507.06 seconds
Started Jul 10 06:16:40 PM PDT 24
Finished Jul 10 06:25:08 PM PDT 24
Peak memory 202216 kb
Host smart-7af5bd58-cc2b-48af-8155-f782a8cb2d8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121289989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1121289989
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.4281766900
Short name T558
Test name
Test status
Simulation time 25138837783 ps
CPU time 26.47 seconds
Started Jul 10 06:16:32 PM PDT 24
Finished Jul 10 06:17:00 PM PDT 24
Peak memory 201704 kb
Host smart-fd14b00d-40e7-4561-9d07-9b3fc3252a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281766900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.4281766900
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2202340926
Short name T661
Test name
Test status
Simulation time 4382348423 ps
CPU time 11.87 seconds
Started Jul 10 06:16:38 PM PDT 24
Finished Jul 10 06:16:50 PM PDT 24
Peak memory 201684 kb
Host smart-cb7346a3-4673-4dd6-af10-d89501a8bc16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202340926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2202340926
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.2334986168
Short name T481
Test name
Test status
Simulation time 5992818994 ps
CPU time 7.28 seconds
Started Jul 10 06:16:33 PM PDT 24
Finished Jul 10 06:16:41 PM PDT 24
Peak memory 201708 kb
Host smart-213d6c40-fe3b-4538-b6e6-64b7eff0c074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334986168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.2334986168
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.3457409330
Short name T566
Test name
Test status
Simulation time 38426143542 ps
CPU time 90.55 seconds
Started Jul 10 06:16:33 PM PDT 24
Finished Jul 10 06:18:04 PM PDT 24
Peak memory 201700 kb
Host smart-05469aa5-680a-4d7d-98e5-9f71586759cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457409330 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.3457409330
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.1189858367
Short name T756
Test name
Test status
Simulation time 520748397 ps
CPU time 1.88 seconds
Started Jul 10 06:16:40 PM PDT 24
Finished Jul 10 06:16:42 PM PDT 24
Peak memory 201644 kb
Host smart-b5b9f864-cfb5-4d57-a35b-378e10db1c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189858367 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.1189858367
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.3863871232
Short name T268
Test name
Test status
Simulation time 165869257731 ps
CPU time 99.35 seconds
Started Jul 10 06:16:40 PM PDT 24
Finished Jul 10 06:18:20 PM PDT 24
Peak memory 201924 kb
Host smart-1e420991-7a9a-4a78-b454-adb53e88eb10
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863871232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gat
ing.3863871232
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.3412610933
Short name T10
Test name
Test status
Simulation time 323671958616 ps
CPU time 197.42 seconds
Started Jul 10 06:16:37 PM PDT 24
Finished Jul 10 06:19:55 PM PDT 24
Peak memory 201900 kb
Host smart-3dcf2132-08c0-4c51-a53d-9c03b229d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412610933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.3412610933
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.2637381579
Short name T518
Test name
Test status
Simulation time 158788585031 ps
CPU time 368.02 seconds
Started Jul 10 06:16:32 PM PDT 24
Finished Jul 10 06:22:41 PM PDT 24
Peak memory 201904 kb
Host smart-204d7a1b-e582-48c7-b8df-8a05d7848169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637381579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.2637381579
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3276067749
Short name T579
Test name
Test status
Simulation time 320608846887 ps
CPU time 766.35 seconds
Started Jul 10 06:16:33 PM PDT 24
Finished Jul 10 06:29:20 PM PDT 24
Peak memory 201864 kb
Host smart-a3006b93-1c4f-4e97-9279-03923f3f7ee8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276067749 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3276067749
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.3964207428
Short name T311
Test name
Test status
Simulation time 161065479259 ps
CPU time 372.21 seconds
Started Jul 10 06:16:32 PM PDT 24
Finished Jul 10 06:22:45 PM PDT 24
Peak memory 201928 kb
Host smart-cdc9690b-2911-49f1-b932-29030310e73c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964207428 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.3964207428
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.4244668924
Short name T394
Test name
Test status
Simulation time 163756874814 ps
CPU time 387.44 seconds
Started Jul 10 06:16:30 PM PDT 24
Finished Jul 10 06:22:58 PM PDT 24
Peak memory 201860 kb
Host smart-2307542f-5cc2-4600-a34b-c5d06363ab32
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244668924 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.4244668924
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.4160943375
Short name T295
Test name
Test status
Simulation time 554460646864 ps
CPU time 858.78 seconds
Started Jul 10 06:16:39 PM PDT 24
Finished Jul 10 06:30:58 PM PDT 24
Peak memory 201916 kb
Host smart-f5eed005-3d15-4dc8-b429-693f42a68d49
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160943375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.4160943375
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.2883882202
Short name T597
Test name
Test status
Simulation time 596902269561 ps
CPU time 1325.74 seconds
Started Jul 10 06:16:38 PM PDT 24
Finished Jul 10 06:38:45 PM PDT 24
Peak memory 201880 kb
Host smart-159fd85a-754b-4dc0-81ce-3e316100896c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883882202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.2883882202
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.524017118
Short name T780
Test name
Test status
Simulation time 116581209836 ps
CPU time 551.88 seconds
Started Jul 10 06:16:40 PM PDT 24
Finished Jul 10 06:25:53 PM PDT 24
Peak memory 202200 kb
Host smart-4dcdb6b0-6bb8-411d-a98e-c5f7e1d4806e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524017118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.524017118
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3815868405
Short name T30
Test name
Test status
Simulation time 21767677355 ps
CPU time 14.51 seconds
Started Jul 10 06:16:39 PM PDT 24
Finished Jul 10 06:16:54 PM PDT 24
Peak memory 201712 kb
Host smart-0a82d4f2-f25a-4aaa-85e4-ab86e544899b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815868405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3815868405
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3574809379
Short name T160
Test name
Test status
Simulation time 4474717972 ps
CPU time 10.44 seconds
Started Jul 10 06:16:40 PM PDT 24
Finished Jul 10 06:16:51 PM PDT 24
Peak memory 201680 kb
Host smart-5cc2e573-44b0-4946-a4a1-0a448949c626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574809379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3574809379
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.577373016
Short name T647
Test name
Test status
Simulation time 6033387525 ps
CPU time 8.23 seconds
Started Jul 10 06:16:32 PM PDT 24
Finished Jul 10 06:16:41 PM PDT 24
Peak memory 201708 kb
Host smart-4769c826-69ba-43db-85fc-0895d3260bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577373016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.577373016
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.3762006040
Short name T533
Test name
Test status
Simulation time 179790935638 ps
CPU time 43.18 seconds
Started Jul 10 06:16:41 PM PDT 24
Finished Jul 10 06:17:25 PM PDT 24
Peak memory 201868 kb
Host smart-ff6e0872-f942-485f-b5d4-12c5bdae1562
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762006040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.3762006040
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.806839452
Short name T535
Test name
Test status
Simulation time 455311374 ps
CPU time 1.28 seconds
Started Jul 10 06:16:50 PM PDT 24
Finished Jul 10 06:16:53 PM PDT 24
Peak memory 201640 kb
Host smart-f5ebb209-417c-435c-b951-3a09ca9636ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806839452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.806839452
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1747246872
Short name T678
Test name
Test status
Simulation time 341227387885 ps
CPU time 603.09 seconds
Started Jul 10 06:16:42 PM PDT 24
Finished Jul 10 06:26:46 PM PDT 24
Peak memory 201788 kb
Host smart-d7f6eb43-b8ca-42f9-828c-51d7555cf3b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747246872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1747246872
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3980762800
Short name T670
Test name
Test status
Simulation time 498534151863 ps
CPU time 1106.94 seconds
Started Jul 10 06:16:45 PM PDT 24
Finished Jul 10 06:35:12 PM PDT 24
Peak memory 201964 kb
Host smart-6b1dd177-6bca-43b4-8429-e18a00d56bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980762800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3980762800
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.2598103247
Short name T181
Test name
Test status
Simulation time 488429849072 ps
CPU time 301.76 seconds
Started Jul 10 06:16:44 PM PDT 24
Finished Jul 10 06:21:46 PM PDT 24
Peak memory 201892 kb
Host smart-e9dfe1a8-72a8-447e-9f80-182a3e941be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598103247 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.2598103247
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.722025396
Short name T372
Test name
Test status
Simulation time 165655478432 ps
CPU time 340.77 seconds
Started Jul 10 06:16:46 PM PDT 24
Finished Jul 10 06:22:27 PM PDT 24
Peak memory 201932 kb
Host smart-45d45d53-cc25-43e8-80bb-3d99b2129367
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=722025396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrup
t_fixed.722025396
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3821928103
Short name T170
Test name
Test status
Simulation time 485494821858 ps
CPU time 119.59 seconds
Started Jul 10 06:16:42 PM PDT 24
Finished Jul 10 06:18:43 PM PDT 24
Peak memory 201960 kb
Host smart-bf6f1de7-4e1f-46d3-b953-906ee11227d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821928103 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3821928103
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.3174518659
Short name T541
Test name
Test status
Simulation time 329299120395 ps
CPU time 200.97 seconds
Started Jul 10 06:16:43 PM PDT 24
Finished Jul 10 06:20:05 PM PDT 24
Peak memory 201868 kb
Host smart-25dfb0a6-5584-4e87-b364-181a5fa7eb3c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174518659 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.3174518659
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.2923916837
Short name T167
Test name
Test status
Simulation time 558696889363 ps
CPU time 600.75 seconds
Started Jul 10 06:16:49 PM PDT 24
Finished Jul 10 06:26:51 PM PDT 24
Peak memory 201932 kb
Host smart-643691a5-b4c8-44c8-be8d-a2bae93c4ff9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923916837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.2923916837
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.1454370450
Short name T413
Test name
Test status
Simulation time 193771556595 ps
CPU time 71.41 seconds
Started Jul 10 06:16:43 PM PDT 24
Finished Jul 10 06:17:55 PM PDT 24
Peak memory 201924 kb
Host smart-a905a386-82bd-49de-a28a-23fc0a52bf5a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454370450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29
.adc_ctrl_filters_wakeup_fixed.1454370450
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.4180911217
Short name T465
Test name
Test status
Simulation time 36165053288 ps
CPU time 22.41 seconds
Started Jul 10 06:16:43 PM PDT 24
Finished Jul 10 06:17:06 PM PDT 24
Peak memory 201692 kb
Host smart-577c4de2-070f-4730-9369-8ae5006ea8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180911217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.4180911217
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.1076126652
Short name T547
Test name
Test status
Simulation time 4536975124 ps
CPU time 1.52 seconds
Started Jul 10 06:16:44 PM PDT 24
Finished Jul 10 06:16:46 PM PDT 24
Peak memory 201684 kb
Host smart-28c4087f-6c8a-4d69-bdd3-6bca23f9d72e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076126652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.1076126652
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.273096053
Short name T393
Test name
Test status
Simulation time 5767932553 ps
CPU time 3.2 seconds
Started Jul 10 06:16:43 PM PDT 24
Finished Jul 10 06:16:47 PM PDT 24
Peak memory 201692 kb
Host smart-e2a07b3f-a5eb-4d6f-878b-8c8d1bfdfd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273096053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.273096053
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3870299538
Short name T261
Test name
Test status
Simulation time 354200221722 ps
CPU time 160.62 seconds
Started Jul 10 06:16:43 PM PDT 24
Finished Jul 10 06:19:25 PM PDT 24
Peak memory 201888 kb
Host smart-a9bcecb5-83fd-4011-aa7f-9cfc9c5482ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870299538 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3870299538
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.2663627504
Short name T36
Test name
Test status
Simulation time 343953152938 ps
CPU time 55.49 seconds
Started Jul 10 06:16:44 PM PDT 24
Finished Jul 10 06:17:41 PM PDT 24
Peak memory 210276 kb
Host smart-cd7b4434-7c1d-41ec-b9a6-eaefaed10198
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663627504 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.2663627504
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.2045123496
Short name T439
Test name
Test status
Simulation time 512991678 ps
CPU time 1.02 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:15:32 PM PDT 24
Peak memory 201696 kb
Host smart-9df1069e-9fe2-4e02-b397-40560fcbd104
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045123496 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.2045123496
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.307155355
Short name T631
Test name
Test status
Simulation time 162945667708 ps
CPU time 8.98 seconds
Started Jul 10 06:15:28 PM PDT 24
Finished Jul 10 06:15:39 PM PDT 24
Peak memory 201904 kb
Host smart-fd9cfcb7-6594-4597-9c5e-ba8c978cb2c6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307155355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.307155355
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.2147733903
Short name T227
Test name
Test status
Simulation time 175897202461 ps
CPU time 103.37 seconds
Started Jul 10 06:15:35 PM PDT 24
Finished Jul 10 06:17:20 PM PDT 24
Peak memory 201936 kb
Host smart-8cae406b-0dfa-4f09-ad99-78beeb680f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147733903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.2147733903
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.3841815161
Short name T591
Test name
Test status
Simulation time 160991866665 ps
CPU time 202.33 seconds
Started Jul 10 06:15:26 PM PDT 24
Finished Jul 10 06:18:50 PM PDT 24
Peak memory 201940 kb
Host smart-9c72b85e-de99-451e-8c10-f620c161ebba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841815161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.3841815161
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.1222493005
Short name T428
Test name
Test status
Simulation time 168743544959 ps
CPU time 194.61 seconds
Started Jul 10 06:15:33 PM PDT 24
Finished Jul 10 06:18:49 PM PDT 24
Peak memory 201884 kb
Host smart-251c2c39-1568-414a-8544-3105f4d36fc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222493005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.1222493005
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.447674227
Short name T757
Test name
Test status
Simulation time 157500675160 ps
CPU time 96.36 seconds
Started Jul 10 06:15:34 PM PDT 24
Finished Jul 10 06:17:12 PM PDT 24
Peak memory 201904 kb
Host smart-4c236006-3c8b-4d8d-917a-a43ad9ff1ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447674227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.447674227
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.1259019182
Short name T388
Test name
Test status
Simulation time 163596935660 ps
CPU time 336.44 seconds
Started Jul 10 06:15:30 PM PDT 24
Finished Jul 10 06:21:08 PM PDT 24
Peak memory 201896 kb
Host smart-e2ef5b3b-279b-4a62-86f5-0d18fef3fcc4
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1259019182 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixe
d.1259019182
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.2324846078
Short name T764
Test name
Test status
Simulation time 655695865981 ps
CPU time 1455.01 seconds
Started Jul 10 06:15:30 PM PDT 24
Finished Jul 10 06:39:47 PM PDT 24
Peak memory 201952 kb
Host smart-2b81603c-9a56-49cb-9596-4728820e753d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324846078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_
wakeup.2324846078
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.1551975232
Short name T606
Test name
Test status
Simulation time 603617028743 ps
CPU time 736.27 seconds
Started Jul 10 06:15:18 PM PDT 24
Finished Jul 10 06:27:37 PM PDT 24
Peak memory 201872 kb
Host smart-7f934c55-3fdc-432d-9ef9-5f11bb5ca97c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551975232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.1551975232
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.1850899111
Short name T198
Test name
Test status
Simulation time 141274419150 ps
CPU time 505.38 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:24:09 PM PDT 24
Peak memory 202220 kb
Host smart-6790c0a3-ad03-4d3f-9227-5e57953ea441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850899111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.1850899111
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.3663607804
Short name T561
Test name
Test status
Simulation time 44644583162 ps
CPU time 25.96 seconds
Started Jul 10 06:15:31 PM PDT 24
Finished Jul 10 06:15:59 PM PDT 24
Peak memory 201692 kb
Host smart-176669e8-4383-4493-9079-8da38f6e92ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663607804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.3663607804
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1292088035
Short name T700
Test name
Test status
Simulation time 5144801470 ps
CPU time 3.32 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:15:34 PM PDT 24
Peak memory 201680 kb
Host smart-5c85cadf-c017-4fb4-aa64-054ba9300dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292088035 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1292088035
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.980895377
Short name T69
Test name
Test status
Simulation time 4081273973 ps
CPU time 10 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:15:41 PM PDT 24
Peak memory 217244 kb
Host smart-e7482eac-74f1-4e16-88cc-031a8748cc57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980895377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.980895377
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.2030374351
Short name T595
Test name
Test status
Simulation time 6133780664 ps
CPU time 7.27 seconds
Started Jul 10 06:15:22 PM PDT 24
Finished Jul 10 06:15:32 PM PDT 24
Peak memory 201700 kb
Host smart-f179ce12-0d2f-4745-8bd6-8f8afaf44429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030374351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.2030374351
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.2804705650
Short name T16
Test name
Test status
Simulation time 66971959678 ps
CPU time 153.54 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:18:05 PM PDT 24
Peak memory 211552 kb
Host smart-2aba6995-2a8b-41df-9a66-59b4ad77090a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804705650 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.2804705650
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.1453746339
Short name T410
Test name
Test status
Simulation time 335951536 ps
CPU time 1.38 seconds
Started Jul 10 06:16:54 PM PDT 24
Finished Jul 10 06:16:56 PM PDT 24
Peak memory 201640 kb
Host smart-7c3af0ab-15de-485b-bedb-42866c8f4cd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453746339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.1453746339
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.3718701877
Short name T286
Test name
Test status
Simulation time 530320149928 ps
CPU time 1046.54 seconds
Started Jul 10 06:16:48 PM PDT 24
Finished Jul 10 06:34:16 PM PDT 24
Peak memory 201860 kb
Host smart-75a3676d-85b0-4723-8103-3c50c0973bb1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718701877 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.3718701877
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.3804570308
Short name T578
Test name
Test status
Simulation time 492304352697 ps
CPU time 1060.69 seconds
Started Jul 10 06:16:48 PM PDT 24
Finished Jul 10 06:34:30 PM PDT 24
Peak memory 201952 kb
Host smart-8c283999-c70e-4e07-9821-a895549785d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804570308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.3804570308
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.3150426482
Short name T186
Test name
Test status
Simulation time 157515950773 ps
CPU time 91.87 seconds
Started Jul 10 06:16:48 PM PDT 24
Finished Jul 10 06:18:21 PM PDT 24
Peak memory 201904 kb
Host smart-bc2a516c-8f4d-42a7-aa70-55b69f3e3320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150426482 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.3150426482
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3000699958
Short name T638
Test name
Test status
Simulation time 164099691397 ps
CPU time 196.2 seconds
Started Jul 10 06:16:50 PM PDT 24
Finished Jul 10 06:20:07 PM PDT 24
Peak memory 201860 kb
Host smart-3663f327-b0f7-4624-b3f7-442413cb43ef
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000699958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3000699958
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.303717810
Short name T529
Test name
Test status
Simulation time 335026230806 ps
CPU time 735.96 seconds
Started Jul 10 06:16:50 PM PDT 24
Finished Jul 10 06:29:08 PM PDT 24
Peak memory 201892 kb
Host smart-d55d75d2-3689-4b62-b69d-2e677190de28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303717810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.303717810
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.3522690852
Short name T474
Test name
Test status
Simulation time 321012175673 ps
CPU time 191.68 seconds
Started Jul 10 06:16:49 PM PDT 24
Finished Jul 10 06:20:02 PM PDT 24
Peak memory 201848 kb
Host smart-39acb19c-672e-4d9c-8fd0-12515feec86f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522690852 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fix
ed.3522690852
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.2475183357
Short name T273
Test name
Test status
Simulation time 384282291380 ps
CPU time 223.43 seconds
Started Jul 10 06:16:48 PM PDT 24
Finished Jul 10 06:20:33 PM PDT 24
Peak memory 201960 kb
Host smart-6b009234-0c54-4653-baf5-4d278b82eb26
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475183357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.2475183357
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3936022375
Short name T636
Test name
Test status
Simulation time 397336165066 ps
CPU time 880.15 seconds
Started Jul 10 06:16:49 PM PDT 24
Finished Jul 10 06:31:31 PM PDT 24
Peak memory 201880 kb
Host smart-1925e7e7-add6-4724-847c-deb1e4ad71e8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936022375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3936022375
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3638662544
Short name T59
Test name
Test status
Simulation time 89062852707 ps
CPU time 337.67 seconds
Started Jul 10 06:16:53 PM PDT 24
Finished Jul 10 06:22:31 PM PDT 24
Peak memory 202268 kb
Host smart-4d5a5c08-fa1e-42a9-89c7-aba5ef5b2105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638662544 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3638662544
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2859913112
Short name T387
Test name
Test status
Simulation time 36864368931 ps
CPU time 23.27 seconds
Started Jul 10 06:16:48 PM PDT 24
Finished Jul 10 06:17:12 PM PDT 24
Peak memory 201644 kb
Host smart-c0566c5d-e871-4daf-96c4-987f098c00d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859913112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2859913112
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.3970369340
Short name T2
Test name
Test status
Simulation time 3503356944 ps
CPU time 7.78 seconds
Started Jul 10 06:16:49 PM PDT 24
Finished Jul 10 06:16:58 PM PDT 24
Peak memory 201692 kb
Host smart-5095703c-f035-4ac3-9a92-ce2050ff1a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970369340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.3970369340
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.662443196
Short name T384
Test name
Test status
Simulation time 6096017382 ps
CPU time 1.67 seconds
Started Jul 10 06:16:48 PM PDT 24
Finished Jul 10 06:16:50 PM PDT 24
Peak memory 201724 kb
Host smart-f0617683-22ec-45f0-b52d-bc5212e320b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662443196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.662443196
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3411744321
Short name T37
Test name
Test status
Simulation time 330437037067 ps
CPU time 87.72 seconds
Started Jul 10 06:16:56 PM PDT 24
Finished Jul 10 06:18:25 PM PDT 24
Peak memory 201888 kb
Host smart-2315e07a-4506-45f9-92d3-cb4c9f03b92e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411744321 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3411744321
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.2520474918
Short name T740
Test name
Test status
Simulation time 21113393697 ps
CPU time 80.1 seconds
Started Jul 10 06:16:54 PM PDT 24
Finished Jul 10 06:18:16 PM PDT 24
Peak memory 210564 kb
Host smart-d18992d6-bc13-4c8a-a11d-cbfaa8407612
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520474918 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.2520474918
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.4073242
Short name T483
Test name
Test status
Simulation time 522659574 ps
CPU time 0.94 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:17:04 PM PDT 24
Peak memory 201640 kb
Host smart-7338c4b4-1faa-4d6a-b78b-efc0085e730e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.4073242
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.1610275487
Short name T548
Test name
Test status
Simulation time 161376951457 ps
CPU time 141.27 seconds
Started Jul 10 06:16:55 PM PDT 24
Finished Jul 10 06:19:17 PM PDT 24
Peak memory 201880 kb
Host smart-e44683e8-c729-40ea-9cfe-2c758ec42cff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610275487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gat
ing.1610275487
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.3606222512
Short name T324
Test name
Test status
Simulation time 359639732176 ps
CPU time 388.89 seconds
Started Jul 10 06:16:56 PM PDT 24
Finished Jul 10 06:23:26 PM PDT 24
Peak memory 201984 kb
Host smart-97384769-b013-42c0-b1e1-dd4a6522bf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606222512 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.3606222512
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.481297958
Short name T221
Test name
Test status
Simulation time 490341129173 ps
CPU time 1195 seconds
Started Jul 10 06:16:53 PM PDT 24
Finished Jul 10 06:36:48 PM PDT 24
Peak memory 201900 kb
Host smart-163de741-96d7-4fe6-8cbb-61a4b465729d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481297958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.481297958
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.3367031806
Short name T619
Test name
Test status
Simulation time 336014335611 ps
CPU time 100.26 seconds
Started Jul 10 06:16:54 PM PDT 24
Finished Jul 10 06:18:34 PM PDT 24
Peak memory 201864 kb
Host smart-67601892-c132-41e8-935c-f5ae27ac0cc2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367031806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interru
pt_fixed.3367031806
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2718268756
Short name T658
Test name
Test status
Simulation time 327423424701 ps
CPU time 614.55 seconds
Started Jul 10 06:16:55 PM PDT 24
Finished Jul 10 06:27:11 PM PDT 24
Peak memory 201972 kb
Host smart-2cd4fb45-7468-46f2-9ba2-16fc8bfb27fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718268756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2718268756
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3915997457
Short name T618
Test name
Test status
Simulation time 487021060384 ps
CPU time 285 seconds
Started Jul 10 06:16:56 PM PDT 24
Finished Jul 10 06:21:42 PM PDT 24
Peak memory 201864 kb
Host smart-f26405bd-764f-4423-b918-b3cee4dd7b01
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915997457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3915997457
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.76885590
Short name T323
Test name
Test status
Simulation time 185591652727 ps
CPU time 80.63 seconds
Started Jul 10 06:16:53 PM PDT 24
Finished Jul 10 06:18:14 PM PDT 24
Peak memory 201980 kb
Host smart-f741983e-4efc-4454-9078-c7c871350c43
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76885590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_w
akeup.76885590
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.911039313
Short name T477
Test name
Test status
Simulation time 201177633730 ps
CPU time 118.88 seconds
Started Jul 10 06:16:54 PM PDT 24
Finished Jul 10 06:18:54 PM PDT 24
Peak memory 201884 kb
Host smart-e9552009-da24-4147-a8b7-7dec1043e3cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911039313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.911039313
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.2036483159
Short name T202
Test name
Test status
Simulation time 86994408896 ps
CPU time 265.38 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:21:28 PM PDT 24
Peak memory 202224 kb
Host smart-b5350d50-c132-4ea4-9606-d5da6a853444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036483159 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.2036483159
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.1255602846
Short name T532
Test name
Test status
Simulation time 27051662770 ps
CPU time 62.89 seconds
Started Jul 10 06:16:55 PM PDT 24
Finished Jul 10 06:17:59 PM PDT 24
Peak memory 201696 kb
Host smart-31a087c1-e87d-4c0d-97ae-4c67317da6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255602846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.1255602846
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.1354622056
Short name T507
Test name
Test status
Simulation time 3656777253 ps
CPU time 2.72 seconds
Started Jul 10 06:16:55 PM PDT 24
Finished Jul 10 06:16:58 PM PDT 24
Peak memory 201704 kb
Host smart-b2fb8d05-0e39-4db3-a388-db4cb5d15fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354622056 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.1354622056
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.2623746732
Short name T604
Test name
Test status
Simulation time 5671679503 ps
CPU time 12.69 seconds
Started Jul 10 06:16:54 PM PDT 24
Finished Jul 10 06:17:07 PM PDT 24
Peak memory 201668 kb
Host smart-e5f16b1d-70f1-49ce-a889-8c0a046a86a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623746732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.2623746732
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3627063502
Short name T414
Test name
Test status
Simulation time 38203144862 ps
CPU time 84.86 seconds
Started Jul 10 06:17:01 PM PDT 24
Finished Jul 10 06:18:27 PM PDT 24
Peak memory 201688 kb
Host smart-0414cc5d-e4a8-462f-8d0c-db7407174d73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627063502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3627063502
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.1035331275
Short name T211
Test name
Test status
Simulation time 348094602129 ps
CPU time 263.05 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:21:25 PM PDT 24
Peak memory 218668 kb
Host smart-c9fb4738-0aea-4f5e-9bf0-ccd5c2742e38
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035331275 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.1035331275
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.1462250366
Short name T38
Test name
Test status
Simulation time 460647505 ps
CPU time 0.89 seconds
Started Jul 10 06:17:09 PM PDT 24
Finished Jul 10 06:17:11 PM PDT 24
Peak memory 201640 kb
Host smart-be05028d-ab91-4fc1-bc3d-e68de365df65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462250366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.1462250366
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.444342558
Short name T318
Test name
Test status
Simulation time 164155922544 ps
CPU time 183.16 seconds
Started Jul 10 06:17:00 PM PDT 24
Finished Jul 10 06:20:04 PM PDT 24
Peak memory 201912 kb
Host smart-63f60c08-5d4e-476d-a0f4-264efcae4670
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444342558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.444342558
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.3579615157
Short name T719
Test name
Test status
Simulation time 501642858499 ps
CPU time 481.77 seconds
Started Jul 10 06:17:01 PM PDT 24
Finished Jul 10 06:25:04 PM PDT 24
Peak memory 201936 kb
Host smart-cdd49e1c-fd2f-4922-aa74-71b44f65e3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579615157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.3579615157
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.2092715408
Short name T695
Test name
Test status
Simulation time 488077836106 ps
CPU time 396.56 seconds
Started Jul 10 06:17:00 PM PDT 24
Finished Jul 10 06:23:38 PM PDT 24
Peak memory 201892 kb
Host smart-dc744f36-7c93-47dd-9d2e-2cd35a94fc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092715408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.2092715408
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.1131192745
Short name T97
Test name
Test status
Simulation time 322249310009 ps
CPU time 690.07 seconds
Started Jul 10 06:17:00 PM PDT 24
Finished Jul 10 06:28:30 PM PDT 24
Peak memory 201864 kb
Host smart-462d7652-b1a8-4c2e-b08e-f7b3b11bbc1f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131192745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interru
pt_fixed.1131192745
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.1697574508
Short name T81
Test name
Test status
Simulation time 494805262966 ps
CPU time 268.74 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:21:32 PM PDT 24
Peak memory 201896 kb
Host smart-bdb01489-9916-4452-8613-93b4e5038c50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697574508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.1697574508
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2516118168
Short name T49
Test name
Test status
Simulation time 328609090770 ps
CPU time 387.67 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:23:31 PM PDT 24
Peak memory 201932 kb
Host smart-5ff69a0e-fcc9-4dcf-9540-a335dbe74e61
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516118168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2516118168
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.1788266658
Short name T676
Test name
Test status
Simulation time 411201474792 ps
CPU time 853.73 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:31:17 PM PDT 24
Peak memory 201884 kb
Host smart-0b2344d4-9170-46a1-8308-c2448b730fb7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788266658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.1788266658
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.100228107
Short name T774
Test name
Test status
Simulation time 197249994677 ps
CPU time 54.95 seconds
Started Jul 10 06:17:01 PM PDT 24
Finished Jul 10 06:17:57 PM PDT 24
Peak memory 201884 kb
Host smart-89cddbed-2db4-4a51-bfca-a46574d6e3e1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100228107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.
adc_ctrl_filters_wakeup_fixed.100228107
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.2061085693
Short name T593
Test name
Test status
Simulation time 137447935600 ps
CPU time 463.05 seconds
Started Jul 10 06:17:01 PM PDT 24
Finished Jul 10 06:24:45 PM PDT 24
Peak memory 202316 kb
Host smart-10abe5d8-42ce-4185-9746-5e908b0a3a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061085693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.2061085693
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.4118235189
Short name T611
Test name
Test status
Simulation time 42906096237 ps
CPU time 47.16 seconds
Started Jul 10 06:17:03 PM PDT 24
Finished Jul 10 06:17:51 PM PDT 24
Peak memory 201696 kb
Host smart-02afb380-bec2-4387-8b44-118c8b82e40e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118235189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.4118235189
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.3773392269
Short name T353
Test name
Test status
Simulation time 3252729410 ps
CPU time 2.55 seconds
Started Jul 10 06:17:02 PM PDT 24
Finished Jul 10 06:17:06 PM PDT 24
Peak memory 201696 kb
Host smart-ce39c7af-3678-4514-99a6-c979965dcdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773392269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.3773392269
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.3529111825
Short name T28
Test name
Test status
Simulation time 5729458018 ps
CPU time 2.67 seconds
Started Jul 10 06:17:00 PM PDT 24
Finished Jul 10 06:17:04 PM PDT 24
Peak memory 201688 kb
Host smart-63778679-9cc2-4212-9781-399535a18881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529111825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.3529111825
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.710754826
Short name T599
Test name
Test status
Simulation time 186625022514 ps
CPU time 386.79 seconds
Started Jul 10 06:17:00 PM PDT 24
Finished Jul 10 06:23:28 PM PDT 24
Peak memory 201896 kb
Host smart-1b099a67-e106-41be-a434-ca33c6f3f660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710754826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all.
710754826
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.3723969361
Short name T96
Test name
Test status
Simulation time 414195242 ps
CPU time 1.57 seconds
Started Jul 10 06:17:15 PM PDT 24
Finished Jul 10 06:17:17 PM PDT 24
Peak memory 201640 kb
Host smart-35bc929c-344f-496e-89c2-5f71653295f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723969361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.3723969361
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.2689472700
Short name T331
Test name
Test status
Simulation time 162212288242 ps
CPU time 106.71 seconds
Started Jul 10 06:17:14 PM PDT 24
Finished Jul 10 06:19:01 PM PDT 24
Peak memory 201880 kb
Host smart-c6e244ac-2df4-416f-85d5-dd8634ad40b7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689472700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gat
ing.2689472700
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2978117021
Short name T193
Test name
Test status
Simulation time 161242863809 ps
CPU time 64.88 seconds
Started Jul 10 06:17:10 PM PDT 24
Finished Jul 10 06:18:15 PM PDT 24
Peak memory 201996 kb
Host smart-48637127-f403-4c02-9233-31b38652927e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978117021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2978117021
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.3365348420
Short name T662
Test name
Test status
Simulation time 492247266034 ps
CPU time 1150.83 seconds
Started Jul 10 06:17:15 PM PDT 24
Finished Jul 10 06:36:26 PM PDT 24
Peak memory 201864 kb
Host smart-58f2eed4-c653-4bc4-b638-24968cb5ebda
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365348420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interru
pt_fixed.3365348420
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.2013578019
Short name T446
Test name
Test status
Simulation time 485987129829 ps
CPU time 428.88 seconds
Started Jul 10 06:17:08 PM PDT 24
Finished Jul 10 06:24:18 PM PDT 24
Peak memory 201872 kb
Host smart-db3d9c7c-af39-4d38-8067-4488b94da7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013578019 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.2013578019
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2328605683
Short name T429
Test name
Test status
Simulation time 485016736381 ps
CPU time 517.35 seconds
Started Jul 10 06:17:08 PM PDT 24
Finished Jul 10 06:25:46 PM PDT 24
Peak memory 201876 kb
Host smart-663efb09-37a0-4a70-8022-74929e8df8db
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328605683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2328605683
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.943791285
Short name T172
Test name
Test status
Simulation time 419751446104 ps
CPU time 156.8 seconds
Started Jul 10 06:17:15 PM PDT 24
Finished Jul 10 06:19:52 PM PDT 24
Peak memory 201944 kb
Host smart-6e2ea474-59a6-4584-b4a6-08d61b23460e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943791285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_
wakeup.943791285
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.1107281890
Short name T717
Test name
Test status
Simulation time 604552754044 ps
CPU time 219.53 seconds
Started Jul 10 06:17:18 PM PDT 24
Finished Jul 10 06:20:58 PM PDT 24
Peak memory 201872 kb
Host smart-65145c6b-1733-4238-a2ad-16fa1574983e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107281890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33
.adc_ctrl_filters_wakeup_fixed.1107281890
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.2299026886
Short name T778
Test name
Test status
Simulation time 69865346327 ps
CPU time 418.08 seconds
Started Jul 10 06:17:17 PM PDT 24
Finished Jul 10 06:24:16 PM PDT 24
Peak memory 202208 kb
Host smart-d930b266-c989-43e7-a50a-a5cbd66d6da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299026886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.2299026886
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.3384596663
Short name T415
Test name
Test status
Simulation time 34095022076 ps
CPU time 43.12 seconds
Started Jul 10 06:17:18 PM PDT 24
Finished Jul 10 06:18:02 PM PDT 24
Peak memory 201692 kb
Host smart-926dff33-c8c1-44cf-8be2-47479b4f0609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384596663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.3384596663
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.3780616425
Short name T440
Test name
Test status
Simulation time 3284593419 ps
CPU time 2.79 seconds
Started Jul 10 06:17:14 PM PDT 24
Finished Jul 10 06:17:17 PM PDT 24
Peak memory 201696 kb
Host smart-fa4ee681-e964-4a92-afc1-3ac927584fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780616425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.3780616425
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2667408346
Short name T491
Test name
Test status
Simulation time 6074408396 ps
CPU time 7.85 seconds
Started Jul 10 06:17:08 PM PDT 24
Finished Jul 10 06:17:17 PM PDT 24
Peak memory 201916 kb
Host smart-da3d6092-3102-4306-bbf3-eff536dff576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667408346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2667408346
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.1583707242
Short name T260
Test name
Test status
Simulation time 496476304252 ps
CPU time 308.14 seconds
Started Jul 10 06:17:18 PM PDT 24
Finished Jul 10 06:22:27 PM PDT 24
Peak memory 201868 kb
Host smart-875b26a5-3357-4374-8b05-856d439ddfc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583707242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.1583707242
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.3661622451
Short name T107
Test name
Test status
Simulation time 303300223 ps
CPU time 1.03 seconds
Started Jul 10 06:17:25 PM PDT 24
Finished Jul 10 06:17:27 PM PDT 24
Peak memory 201628 kb
Host smart-d7f5a3c1-c6d7-494f-9db2-22474e424730
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661622451 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.3661622451
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.537363726
Short name T506
Test name
Test status
Simulation time 325210755650 ps
CPU time 703.95 seconds
Started Jul 10 06:17:19 PM PDT 24
Finished Jul 10 06:29:04 PM PDT 24
Peak memory 201888 kb
Host smart-e2ef95f3-d3bd-4049-8b43-7744638f0c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537363726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.537363726
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.3759005294
Short name T655
Test name
Test status
Simulation time 489063796058 ps
CPU time 1096.24 seconds
Started Jul 10 06:17:20 PM PDT 24
Finished Jul 10 06:35:37 PM PDT 24
Peak memory 201888 kb
Host smart-b136f161-fb80-48af-9e29-bef52d839cc7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759005294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.3759005294
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.181611552
Short name T41
Test name
Test status
Simulation time 483506931786 ps
CPU time 298.73 seconds
Started Jul 10 06:17:18 PM PDT 24
Finished Jul 10 06:22:18 PM PDT 24
Peak memory 201956 kb
Host smart-ec5a7627-9c8c-4e74-b81f-733cf6fa14e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181611552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.181611552
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.3661270926
Short name T376
Test name
Test status
Simulation time 490614897185 ps
CPU time 1026.05 seconds
Started Jul 10 06:17:19 PM PDT 24
Finished Jul 10 06:34:26 PM PDT 24
Peak memory 201972 kb
Host smart-a9684c75-de89-4f5a-a881-e5ffc855f0ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661270926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fix
ed.3661270926
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.2666700664
Short name T165
Test name
Test status
Simulation time 548504094265 ps
CPU time 205.83 seconds
Started Jul 10 06:17:19 PM PDT 24
Finished Jul 10 06:20:45 PM PDT 24
Peak memory 201896 kb
Host smart-fe5afab1-ec35-4bda-acef-c9a6982043c7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666700664 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters
_wakeup.2666700664
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.1571466231
Short name T721
Test name
Test status
Simulation time 383425226934 ps
CPU time 887.79 seconds
Started Jul 10 06:17:18 PM PDT 24
Finished Jul 10 06:32:07 PM PDT 24
Peak memory 201872 kb
Host smart-fe734302-0d2b-49ce-8eb8-1d87e12cbd41
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571466231 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.1571466231
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.944433988
Short name T755
Test name
Test status
Simulation time 112054157911 ps
CPU time 566.25 seconds
Started Jul 10 06:17:25 PM PDT 24
Finished Jul 10 06:26:52 PM PDT 24
Peak memory 202268 kb
Host smart-05e20612-1f18-4709-bc7b-586cfd6da275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944433988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.944433988
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.3737783484
Short name T397
Test name
Test status
Simulation time 31900920666 ps
CPU time 40.13 seconds
Started Jul 10 06:17:24 PM PDT 24
Finished Jul 10 06:18:05 PM PDT 24
Peak memory 201688 kb
Host smart-29cac21b-d90f-4536-bd44-c51451a80986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737783484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.3737783484
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.886533590
Short name T351
Test name
Test status
Simulation time 3212626014 ps
CPU time 7.7 seconds
Started Jul 10 06:17:31 PM PDT 24
Finished Jul 10 06:17:39 PM PDT 24
Peak memory 201708 kb
Host smart-3532d6cd-8707-47da-a604-6220b953ad5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886533590 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.886533590
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2553415
Short name T587
Test name
Test status
Simulation time 5873558785 ps
CPU time 14.2 seconds
Started Jul 10 06:17:21 PM PDT 24
Finished Jul 10 06:17:36 PM PDT 24
Peak memory 201684 kb
Host smart-790455f3-077b-450a-96a5-04830fcfa7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2553415
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.968031680
Short name T793
Test name
Test status
Simulation time 12046643504 ps
CPU time 24.91 seconds
Started Jul 10 06:17:29 PM PDT 24
Finished Jul 10 06:17:55 PM PDT 24
Peak memory 201956 kb
Host smart-88e6e1cf-e08e-4acf-8412-78aec1eafc6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968031680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all.
968031680
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.4257633505
Short name T31
Test name
Test status
Simulation time 453252737 ps
CPU time 0.74 seconds
Started Jul 10 06:17:35 PM PDT 24
Finished Jul 10 06:17:36 PM PDT 24
Peak memory 201564 kb
Host smart-acfd9d7b-0819-466c-9e7c-2474e0979a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257633505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.4257633505
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.2230402699
Short name T694
Test name
Test status
Simulation time 177760120326 ps
CPU time 98.12 seconds
Started Jul 10 06:17:26 PM PDT 24
Finished Jul 10 06:19:05 PM PDT 24
Peak memory 201880 kb
Host smart-15de616f-26c3-4849-9ed2-9e3f331902d5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230402699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.2230402699
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.2447658676
Short name T241
Test name
Test status
Simulation time 170528831243 ps
CPU time 104.27 seconds
Started Jul 10 06:17:30 PM PDT 24
Finished Jul 10 06:19:15 PM PDT 24
Peak memory 201932 kb
Host smart-45c25cfc-e1a9-4dba-b1b7-0da9e05565b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447658676 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.2447658676
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.3795931751
Short name T185
Test name
Test status
Simulation time 161405094232 ps
CPU time 76.35 seconds
Started Jul 10 06:17:24 PM PDT 24
Finished Jul 10 06:18:41 PM PDT 24
Peak memory 201932 kb
Host smart-ddf80ee9-325d-485e-b1e6-636e0e1c2403
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795931751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.3795931751
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.2514755116
Short name T630
Test name
Test status
Simulation time 487670073507 ps
CPU time 283.36 seconds
Started Jul 10 06:17:30 PM PDT 24
Finished Jul 10 06:22:14 PM PDT 24
Peak memory 201880 kb
Host smart-812af3cc-abdf-4e4f-b783-a9e5ace73e2a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514755116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.2514755116
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.2237863357
Short name T245
Test name
Test status
Simulation time 180582106169 ps
CPU time 95.93 seconds
Started Jul 10 06:17:26 PM PDT 24
Finished Jul 10 06:19:02 PM PDT 24
Peak memory 201980 kb
Host smart-0ab7a166-485d-4378-a73e-23b36744b608
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237863357 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.2237863357
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.23328179
Short name T409
Test name
Test status
Simulation time 201332478625 ps
CPU time 473.89 seconds
Started Jul 10 06:17:26 PM PDT 24
Finished Jul 10 06:25:20 PM PDT 24
Peak memory 201872 kb
Host smart-391a611b-345d-4d71-9467-c0e73bb0f700
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23328179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.a
dc_ctrl_filters_wakeup_fixed.23328179
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2860936694
Short name T340
Test name
Test status
Simulation time 86883770094 ps
CPU time 298.44 seconds
Started Jul 10 06:17:35 PM PDT 24
Finished Jul 10 06:22:34 PM PDT 24
Peak memory 202204 kb
Host smart-513da53c-c11c-4a9f-a62b-6739741f85b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860936694 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2860936694
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.848036353
Short name T754
Test name
Test status
Simulation time 41640306836 ps
CPU time 47.57 seconds
Started Jul 10 06:17:29 PM PDT 24
Finished Jul 10 06:18:18 PM PDT 24
Peak memory 201680 kb
Host smart-6271ed8d-18c6-4cfd-87cc-f57ad896bf3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848036353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.848036353
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.975670552
Short name T562
Test name
Test status
Simulation time 4201905754 ps
CPU time 10.02 seconds
Started Jul 10 06:17:30 PM PDT 24
Finished Jul 10 06:17:41 PM PDT 24
Peak memory 201716 kb
Host smart-c88f6f9b-4ae8-40e6-b303-a51c3cae9ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975670552 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.975670552
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.2185260917
Short name T516
Test name
Test status
Simulation time 5778611169 ps
CPU time 5.1 seconds
Started Jul 10 06:17:30 PM PDT 24
Finished Jul 10 06:17:36 PM PDT 24
Peak memory 201688 kb
Host smart-160d9352-d290-45a3-8b70-3d834bfe5014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185260917 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.2185260917
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.1755489781
Short name T745
Test name
Test status
Simulation time 280614827549 ps
CPU time 843.31 seconds
Started Jul 10 06:17:31 PM PDT 24
Finished Jul 10 06:31:35 PM PDT 24
Peak memory 210400 kb
Host smart-7bfd5f19-03b3-4b1f-b2ea-446082d01ad4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755489781 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.1755489781
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.3417342372
Short name T779
Test name
Test status
Simulation time 54382352838 ps
CPU time 101.95 seconds
Started Jul 10 06:17:30 PM PDT 24
Finished Jul 10 06:19:13 PM PDT 24
Peak memory 210524 kb
Host smart-778bb1a8-4a0f-4266-bea3-74f73a8654ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417342372 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.3417342372
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.3922347299
Short name T430
Test name
Test status
Simulation time 543751991 ps
CPU time 0.87 seconds
Started Jul 10 06:17:45 PM PDT 24
Finished Jul 10 06:17:46 PM PDT 24
Peak memory 201640 kb
Host smart-faa43abf-006e-4c27-82a0-7b6f9756652d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922347299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.3922347299
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.4245008009
Short name T651
Test name
Test status
Simulation time 163567877584 ps
CPU time 143.73 seconds
Started Jul 10 06:17:33 PM PDT 24
Finished Jul 10 06:19:57 PM PDT 24
Peak memory 201948 kb
Host smart-34f8a5d9-7c12-46c6-b036-6d68eaf56dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245008009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.4245008009
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.3301116765
Short name T526
Test name
Test status
Simulation time 487154848309 ps
CPU time 1098.09 seconds
Started Jul 10 06:17:37 PM PDT 24
Finished Jul 10 06:35:56 PM PDT 24
Peak memory 201896 kb
Host smart-0bbdc87d-22e9-4a02-81ad-6f6ee57b5767
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301116765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.3301116765
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.3145252248
Short name T519
Test name
Test status
Simulation time 494656664279 ps
CPU time 1193.9 seconds
Started Jul 10 06:17:35 PM PDT 24
Finished Jul 10 06:37:30 PM PDT 24
Peak memory 201936 kb
Host smart-e2366195-9d15-4223-8f4d-77e823803e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145252248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.3145252248
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.985754857
Short name T374
Test name
Test status
Simulation time 328567492290 ps
CPU time 74.29 seconds
Started Jul 10 06:17:35 PM PDT 24
Finished Jul 10 06:18:50 PM PDT 24
Peak memory 201884 kb
Host smart-0e8d0feb-4b10-400c-a470-1b4baf1c369c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=985754857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fixe
d.985754857
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.3478449390
Short name T228
Test name
Test status
Simulation time 170780448390 ps
CPU time 389.44 seconds
Started Jul 10 06:17:36 PM PDT 24
Finished Jul 10 06:24:06 PM PDT 24
Peak memory 201960 kb
Host smart-4c37cdda-9926-4b6c-9be1-df76a795acb3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478449390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters
_wakeup.3478449390
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.709276764
Short name T743
Test name
Test status
Simulation time 589430616483 ps
CPU time 1252.78 seconds
Started Jul 10 06:17:36 PM PDT 24
Finished Jul 10 06:38:30 PM PDT 24
Peak memory 201864 kb
Host smart-e0aec27d-55fc-428a-ae60-561a0900f4f6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709276764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.
adc_ctrl_filters_wakeup_fixed.709276764
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1670910107
Short name T196
Test name
Test status
Simulation time 139078044374 ps
CPU time 490.23 seconds
Started Jul 10 06:17:42 PM PDT 24
Finished Jul 10 06:25:53 PM PDT 24
Peak memory 202224 kb
Host smart-78f3ad3e-b771-475d-a1d8-366000dcb09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670910107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1670910107
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2675901954
Short name T497
Test name
Test status
Simulation time 36828950464 ps
CPU time 5.65 seconds
Started Jul 10 06:17:41 PM PDT 24
Finished Jul 10 06:17:47 PM PDT 24
Peak memory 201692 kb
Host smart-e9d5cbf8-cf66-4d5b-b9f8-8fe23af53c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675901954 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2675901954
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.2456030806
Short name T744
Test name
Test status
Simulation time 4091254896 ps
CPU time 2.09 seconds
Started Jul 10 06:17:35 PM PDT 24
Finished Jul 10 06:17:39 PM PDT 24
Peak memory 201728 kb
Host smart-a17fccbd-b2c4-4b39-8881-f3f97f453e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456030806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.2456030806
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.1462847826
Short name T749
Test name
Test status
Simulation time 5921788358 ps
CPU time 2.47 seconds
Started Jul 10 06:17:35 PM PDT 24
Finished Jul 10 06:17:38 PM PDT 24
Peak memory 201688 kb
Host smart-c2374109-0240-470c-8b50-17401b0603bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462847826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.1462847826
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.2680953630
Short name T102
Test name
Test status
Simulation time 281324101136 ps
CPU time 261.42 seconds
Started Jul 10 06:17:45 PM PDT 24
Finished Jul 10 06:22:06 PM PDT 24
Peak memory 210532 kb
Host smart-29669e6e-0134-42a7-a2b2-94427fe52c96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680953630 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.2680953630
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.3763108049
Short name T710
Test name
Test status
Simulation time 450994922 ps
CPU time 1.46 seconds
Started Jul 10 06:17:48 PM PDT 24
Finished Jul 10 06:17:50 PM PDT 24
Peak memory 201628 kb
Host smart-fb91e0e9-4f25-4b60-bad9-19546ebd9e41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3763108049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.3763108049
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1950508509
Short name T40
Test name
Test status
Simulation time 199756174609 ps
CPU time 395.43 seconds
Started Jul 10 06:17:47 PM PDT 24
Finished Jul 10 06:24:23 PM PDT 24
Peak memory 201888 kb
Host smart-2e2d6219-f0bd-451f-a321-e87859757e20
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950508509 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1950508509
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1696502536
Short name T175
Test name
Test status
Simulation time 226096734809 ps
CPU time 474.43 seconds
Started Jul 10 06:17:46 PM PDT 24
Finished Jul 10 06:25:41 PM PDT 24
Peak memory 201904 kb
Host smart-0f6ca764-08f3-44d2-9411-58a5d51b1556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696502536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1696502536
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.1555901740
Short name T308
Test name
Test status
Simulation time 160622991759 ps
CPU time 96.32 seconds
Started Jul 10 06:17:44 PM PDT 24
Finished Jul 10 06:19:21 PM PDT 24
Peak memory 201900 kb
Host smart-6e78f226-9c6f-46b2-bfcd-9627e7fc27fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555901740 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.1555901740
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2850714706
Short name T375
Test name
Test status
Simulation time 321162299439 ps
CPU time 195.81 seconds
Started Jul 10 06:17:41 PM PDT 24
Finished Jul 10 06:20:57 PM PDT 24
Peak memory 201852 kb
Host smart-fe08492e-3f40-48a3-a53b-3cbe41753532
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850714706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2850714706
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.2924107174
Short name T187
Test name
Test status
Simulation time 318949935942 ps
CPU time 526.15 seconds
Started Jul 10 06:17:42 PM PDT 24
Finished Jul 10 06:26:28 PM PDT 24
Peak memory 201884 kb
Host smart-d57ea926-1524-4ae3-905d-842b9b052947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924107174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.2924107174
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.277059368
Short name T602
Test name
Test status
Simulation time 160888544893 ps
CPU time 78.48 seconds
Started Jul 10 06:17:46 PM PDT 24
Finished Jul 10 06:19:05 PM PDT 24
Peak memory 201796 kb
Host smart-4aaaa215-f368-41ca-9ad9-8b70bb09d3b8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=277059368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fixe
d.277059368
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3689914985
Short name T253
Test name
Test status
Simulation time 350633900913 ps
CPU time 364.92 seconds
Started Jul 10 06:17:49 PM PDT 24
Finished Jul 10 06:23:55 PM PDT 24
Peak memory 201872 kb
Host smart-6cf76223-34f0-498c-91f1-423914018463
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689914985 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3689914985
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.2883502309
Short name T671
Test name
Test status
Simulation time 205630468073 ps
CPU time 220.09 seconds
Started Jul 10 06:17:47 PM PDT 24
Finished Jul 10 06:21:28 PM PDT 24
Peak memory 201924 kb
Host smart-e198321e-c867-49ea-b7ae-27e1ce552838
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883502309 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37
.adc_ctrl_filters_wakeup_fixed.2883502309
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.2319616007
Short name T553
Test name
Test status
Simulation time 99798045921 ps
CPU time 541.11 seconds
Started Jul 10 06:17:48 PM PDT 24
Finished Jul 10 06:26:50 PM PDT 24
Peak memory 202280 kb
Host smart-8e0dc1eb-c852-4c28-869c-84251319715a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319616007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.2319616007
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.783294003
Short name T354
Test name
Test status
Simulation time 33404392186 ps
CPU time 7.19 seconds
Started Jul 10 06:17:47 PM PDT 24
Finished Jul 10 06:17:55 PM PDT 24
Peak memory 201672 kb
Host smart-d59cd2d8-b174-4839-badb-ce3778c10962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783294003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.783294003
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.3165193218
Short name T427
Test name
Test status
Simulation time 3452847293 ps
CPU time 3.3 seconds
Started Jul 10 06:17:49 PM PDT 24
Finished Jul 10 06:17:53 PM PDT 24
Peak memory 201716 kb
Host smart-d48dad32-920e-4e33-ba31-c3683fa5502b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165193218 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.3165193218
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.1834898024
Short name T632
Test name
Test status
Simulation time 5754112395 ps
CPU time 1.57 seconds
Started Jul 10 06:17:45 PM PDT 24
Finished Jul 10 06:17:47 PM PDT 24
Peak memory 201640 kb
Host smart-01f9b8e9-30d8-408a-95b9-e03397426f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834898024 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.1834898024
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.708557303
Short name T769
Test name
Test status
Simulation time 144159565740 ps
CPU time 124.44 seconds
Started Jul 10 06:17:48 PM PDT 24
Finished Jul 10 06:19:53 PM PDT 24
Peak memory 217932 kb
Host smart-3be4486f-bc70-4f82-96d3-8d64e7cd9317
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708557303 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.708557303
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.677743197
Short name T369
Test name
Test status
Simulation time 351274511 ps
CPU time 1.31 seconds
Started Jul 10 06:18:05 PM PDT 24
Finished Jul 10 06:18:07 PM PDT 24
Peak memory 201704 kb
Host smart-6a76bb7e-fc59-451e-bf17-abe2eb25cc74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677743197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.677743197
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.356772066
Short name T136
Test name
Test status
Simulation time 324759797706 ps
CPU time 750.67 seconds
Started Jul 10 06:18:01 PM PDT 24
Finished Jul 10 06:30:33 PM PDT 24
Peak memory 201828 kb
Host smart-6effe21c-ead2-4f77-a139-f225989fc564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356772066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.356772066
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.434849373
Short name T687
Test name
Test status
Simulation time 162952079986 ps
CPU time 81.75 seconds
Started Jul 10 06:17:54 PM PDT 24
Finished Jul 10 06:19:16 PM PDT 24
Peak memory 201868 kb
Host smart-bb43dca9-409f-4898-9a04-4fcbd3d0abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434849373 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.434849373
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.1820618811
Short name T54
Test name
Test status
Simulation time 322190116748 ps
CPU time 761.94 seconds
Started Jul 10 06:17:53 PM PDT 24
Finished Jul 10 06:30:35 PM PDT 24
Peak memory 201848 kb
Host smart-4b5b053c-3bd2-412b-92bb-89a79becfbf5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1820618811 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interru
pt_fixed.1820618811
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.3549147609
Short name T424
Test name
Test status
Simulation time 162165129455 ps
CPU time 359 seconds
Started Jul 10 06:17:52 PM PDT 24
Finished Jul 10 06:23:52 PM PDT 24
Peak memory 201912 kb
Host smart-f40be870-9c6e-46c7-8ef7-488416c9cf00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549147609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.3549147609
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1310464165
Short name T568
Test name
Test status
Simulation time 321167644272 ps
CPU time 674.35 seconds
Started Jul 10 06:17:54 PM PDT 24
Finished Jul 10 06:29:09 PM PDT 24
Peak memory 201868 kb
Host smart-ef1f5ab3-48e0-4bc0-b279-18ac211f532f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310464165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1310464165
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.1835962334
Short name T274
Test name
Test status
Simulation time 361866815280 ps
CPU time 122.87 seconds
Started Jul 10 06:17:54 PM PDT 24
Finished Jul 10 06:19:57 PM PDT 24
Peak memory 201912 kb
Host smart-54671545-6e19-4645-8b56-4a38e74676ea
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835962334 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.1835962334
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.2823843188
Short name T761
Test name
Test status
Simulation time 612138416384 ps
CPU time 1310.72 seconds
Started Jul 10 06:17:52 PM PDT 24
Finished Jul 10 06:39:43 PM PDT 24
Peak memory 201928 kb
Host smart-25313132-0359-45ac-aa21-5486ba09e6bc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823843188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.2823843188
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1238067830
Short name T15
Test name
Test status
Simulation time 74212243364 ps
CPU time 395.6 seconds
Started Jul 10 06:17:58 PM PDT 24
Finished Jul 10 06:24:34 PM PDT 24
Peak memory 202272 kb
Host smart-d596fee1-9319-41b7-9bc0-0b9bc95d3ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238067830 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1238067830
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.4281681731
Short name T567
Test name
Test status
Simulation time 27626381383 ps
CPU time 6.54 seconds
Started Jul 10 06:18:02 PM PDT 24
Finished Jul 10 06:18:09 PM PDT 24
Peak memory 201596 kb
Host smart-aa7736c4-e582-443f-9728-cfafcbcda299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281681731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.4281681731
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.865641269
Short name T617
Test name
Test status
Simulation time 4113823877 ps
CPU time 10.82 seconds
Started Jul 10 06:17:59 PM PDT 24
Finished Jul 10 06:18:11 PM PDT 24
Peak memory 201688 kb
Host smart-0731bd9b-24b7-4910-80e9-047cefc5bc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865641269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.865641269
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.1660012945
Short name T522
Test name
Test status
Simulation time 5728469208 ps
CPU time 14.62 seconds
Started Jul 10 06:17:49 PM PDT 24
Finished Jul 10 06:18:04 PM PDT 24
Peak memory 201612 kb
Host smart-5573d536-20cd-46d9-bb91-3107bdf05822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660012945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.1660012945
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.1770230629
Short name T564
Test name
Test status
Simulation time 420213992011 ps
CPU time 781.29 seconds
Started Jul 10 06:18:01 PM PDT 24
Finished Jul 10 06:31:03 PM PDT 24
Peak memory 213192 kb
Host smart-daa18809-ed81-42b8-b2ce-21b02065c72f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770230629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.1770230629
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.559459309
Short name T24
Test name
Test status
Simulation time 292757288592 ps
CPU time 169.13 seconds
Started Jul 10 06:18:01 PM PDT 24
Finished Jul 10 06:20:50 PM PDT 24
Peak memory 210180 kb
Host smart-f5678c5b-fe13-4b3d-9a20-288794de0c8f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559459309 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.559459309
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2589198663
Short name T99
Test name
Test status
Simulation time 284117968 ps
CPU time 1.28 seconds
Started Jul 10 06:18:16 PM PDT 24
Finished Jul 10 06:18:18 PM PDT 24
Peak memory 201652 kb
Host smart-3343c359-5f1b-4092-a5b5-7f926beca22a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589198663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2589198663
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1427443974
Short name T147
Test name
Test status
Simulation time 495245986351 ps
CPU time 1102.25 seconds
Started Jul 10 06:18:04 PM PDT 24
Finished Jul 10 06:36:27 PM PDT 24
Peak memory 201880 kb
Host smart-b057b740-fa38-43f7-8725-21c1e107b0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427443974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1427443974
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.3602746558
Short name T453
Test name
Test status
Simulation time 158929635526 ps
CPU time 369.89 seconds
Started Jul 10 06:18:11 PM PDT 24
Finished Jul 10 06:24:21 PM PDT 24
Peak memory 201860 kb
Host smart-223386fe-f530-4863-9a4d-84833eea0796
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602746558 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interru
pt_fixed.3602746558
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.2062163487
Short name T437
Test name
Test status
Simulation time 492510478629 ps
CPU time 1101.03 seconds
Started Jul 10 06:18:05 PM PDT 24
Finished Jul 10 06:36:26 PM PDT 24
Peak memory 201900 kb
Host smart-1b736d33-147b-43a3-ab96-d8d8698d766f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062163487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.2062163487
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.3981652524
Short name T357
Test name
Test status
Simulation time 160714709212 ps
CPU time 362.8 seconds
Started Jul 10 06:18:05 PM PDT 24
Finished Jul 10 06:24:08 PM PDT 24
Peak memory 201860 kb
Host smart-4a9b2705-3f27-4356-bd3d-3bc0c651cc99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981652524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.3981652524
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.20049958
Short name T259
Test name
Test status
Simulation time 210690792862 ps
CPU time 491.53 seconds
Started Jul 10 06:18:11 PM PDT 24
Finished Jul 10 06:26:23 PM PDT 24
Peak memory 201964 kb
Host smart-e790620e-2c9c-4c5f-80f3-49a12477ca66
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049958 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_w
akeup.20049958
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1355274737
Short name T555
Test name
Test status
Simulation time 198258148849 ps
CPU time 240.78 seconds
Started Jul 10 06:18:10 PM PDT 24
Finished Jul 10 06:22:12 PM PDT 24
Peak memory 201880 kb
Host smart-e2570a33-e419-4f48-b2b7-149448edf226
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355274737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1355274737
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.4173574956
Short name T584
Test name
Test status
Simulation time 31221168376 ps
CPU time 72.92 seconds
Started Jul 10 06:18:19 PM PDT 24
Finished Jul 10 06:19:32 PM PDT 24
Peak memory 201688 kb
Host smart-eb5e8e90-8bb3-4389-a21f-5b46ad4412cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173574956 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.4173574956
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.3881043728
Short name T560
Test name
Test status
Simulation time 2933249680 ps
CPU time 6.87 seconds
Started Jul 10 06:18:17 PM PDT 24
Finished Jul 10 06:18:24 PM PDT 24
Peak memory 201692 kb
Host smart-252357dc-3190-4f0d-9d23-dabf13c50531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881043728 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.3881043728
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.2171138939
Short name T650
Test name
Test status
Simulation time 5877842181 ps
CPU time 3.94 seconds
Started Jul 10 06:18:04 PM PDT 24
Finished Jul 10 06:18:09 PM PDT 24
Peak memory 201688 kb
Host smart-c1a4771e-8e7d-4a6e-a445-62479c3cd06b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171138939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.2171138939
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.1386253043
Short name T551
Test name
Test status
Simulation time 256977059723 ps
CPU time 401.7 seconds
Started Jul 10 06:18:16 PM PDT 24
Finished Jul 10 06:24:58 PM PDT 24
Peak memory 218616 kb
Host smart-73a97bad-0bf3-457f-ac38-52ea034679c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386253043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.1386253043
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.929565644
Short name T329
Test name
Test status
Simulation time 124453775821 ps
CPU time 51.89 seconds
Started Jul 10 06:18:17 PM PDT 24
Finished Jul 10 06:19:10 PM PDT 24
Peak memory 202024 kb
Host smart-667a98d6-7188-4196-a130-70ace5dff13f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929565644 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.929565644
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.1977046129
Short name T405
Test name
Test status
Simulation time 329096038 ps
CPU time 1.02 seconds
Started Jul 10 06:15:33 PM PDT 24
Finished Jul 10 06:15:35 PM PDT 24
Peak memory 201616 kb
Host smart-ee0d2a3e-5423-4b34-aeb3-24142df153cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977046129 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.1977046129
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.3637707935
Short name T223
Test name
Test status
Simulation time 334189972375 ps
CPU time 166.89 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:18:17 PM PDT 24
Peak memory 201880 kb
Host smart-f4b6e9b4-976c-4587-b937-e3e5929f0bd1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637707935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.3637707935
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.1733660545
Short name T708
Test name
Test status
Simulation time 163511315438 ps
CPU time 186.62 seconds
Started Jul 10 06:15:34 PM PDT 24
Finished Jul 10 06:18:42 PM PDT 24
Peak memory 201952 kb
Host smart-d0c8ed85-3a37-4db0-985a-8afe0118d701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733660545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.1733660545
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.649588078
Short name T432
Test name
Test status
Simulation time 164358394157 ps
CPU time 101.62 seconds
Started Jul 10 06:15:21 PM PDT 24
Finished Jul 10 06:17:05 PM PDT 24
Peak memory 201936 kb
Host smart-8986d5a7-670e-48aa-be6e-75973b52bee7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=649588078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt
_fixed.649588078
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3670850148
Short name T625
Test name
Test status
Simulation time 157681950437 ps
CPU time 345.12 seconds
Started Jul 10 06:15:38 PM PDT 24
Finished Jul 10 06:21:24 PM PDT 24
Peak memory 201900 kb
Host smart-e8a4d894-b20c-4e47-a794-3da34da4e138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670850148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3670850148
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.306198185
Short name T735
Test name
Test status
Simulation time 334920403302 ps
CPU time 184.38 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:18:56 PM PDT 24
Peak memory 201928 kb
Host smart-6459951e-2ab8-4550-9844-ba18dcc796e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=306198185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.306198185
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.3636001245
Short name T232
Test name
Test status
Simulation time 417405887843 ps
CPU time 880.63 seconds
Started Jul 10 06:15:28 PM PDT 24
Finished Jul 10 06:30:11 PM PDT 24
Peak memory 201872 kb
Host smart-3ea74bac-7067-4f93-b2aa-4284271d52dd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636001245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.3636001245
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.3646625349
Short name T98
Test name
Test status
Simulation time 94129713356 ps
CPU time 409.37 seconds
Started Jul 10 06:15:35 PM PDT 24
Finished Jul 10 06:22:26 PM PDT 24
Peak memory 202196 kb
Host smart-a63fb305-6e11-4292-b7a8-197aa9e0f9b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646625349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.3646625349
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.1696658417
Short name T385
Test name
Test status
Simulation time 33673352997 ps
CPU time 74.28 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:17:01 PM PDT 24
Peak memory 201696 kb
Host smart-e5d2612b-4207-4743-a7ff-6f18c5b14b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696658417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.1696658417
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3637576518
Short name T104
Test name
Test status
Simulation time 5332753947 ps
CPU time 11.48 seconds
Started Jul 10 06:15:29 PM PDT 24
Finished Jul 10 06:15:42 PM PDT 24
Peak memory 201716 kb
Host smart-fcc325cb-8ed6-4dea-ab0e-042cdd9b55e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637576518 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3637576518
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.3978914611
Short name T70
Test name
Test status
Simulation time 4269806749 ps
CPU time 10.1 seconds
Started Jul 10 06:15:35 PM PDT 24
Finished Jul 10 06:15:47 PM PDT 24
Peak memory 217184 kb
Host smart-579f24a0-c7e6-4f0a-becc-657af3f789f0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978914611 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.3978914611
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.1559555951
Short name T355
Test name
Test status
Simulation time 5780265989 ps
CPU time 14.3 seconds
Started Jul 10 06:15:28 PM PDT 24
Finished Jul 10 06:15:44 PM PDT 24
Peak memory 201688 kb
Host smart-91b280c4-90fa-463f-a8cf-520f0d6889ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559555951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.1559555951
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.895769380
Short name T307
Test name
Test status
Simulation time 191787558812 ps
CPU time 204.48 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:19:10 PM PDT 24
Peak memory 201884 kb
Host smart-615078ac-b662-48f2-8ad7-8529b81aded0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895769380 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.895769380
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.3324699071
Short name T380
Test name
Test status
Simulation time 468941503 ps
CPU time 1.17 seconds
Started Jul 10 06:18:33 PM PDT 24
Finished Jul 10 06:18:35 PM PDT 24
Peak memory 201660 kb
Host smart-87813fdc-7a24-4867-bb54-20ce6b04dc08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324699071 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.3324699071
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.508744617
Short name T699
Test name
Test status
Simulation time 198608281739 ps
CPU time 418.48 seconds
Started Jul 10 06:18:27 PM PDT 24
Finished Jul 10 06:25:26 PM PDT 24
Peak memory 201936 kb
Host smart-364b90cd-0bed-4f8b-a835-431e9b590530
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508744617 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gati
ng.508744617
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.984726833
Short name T239
Test name
Test status
Simulation time 167125366227 ps
CPU time 206.95 seconds
Started Jul 10 06:18:22 PM PDT 24
Finished Jul 10 06:21:49 PM PDT 24
Peak memory 201908 kb
Host smart-11c0923c-446a-4645-924e-6a8d1d7d7912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984726833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.984726833
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.2925289107
Short name T679
Test name
Test status
Simulation time 161826349684 ps
CPU time 381.08 seconds
Started Jul 10 06:18:22 PM PDT 24
Finished Jul 10 06:24:44 PM PDT 24
Peak memory 201868 kb
Host smart-aa63fb61-6525-4b19-95e7-e70ce643f743
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925289107 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.2925289107
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.1206933075
Short name T472
Test name
Test status
Simulation time 328147371620 ps
CPU time 750.92 seconds
Started Jul 10 06:18:17 PM PDT 24
Finished Jul 10 06:30:49 PM PDT 24
Peak memory 201960 kb
Host smart-73a8e3be-daa5-4fdb-82d0-51cec9b42faf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206933075 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.1206933075
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.1718495660
Short name T464
Test name
Test status
Simulation time 162092251777 ps
CPU time 95.22 seconds
Started Jul 10 06:18:21 PM PDT 24
Finished Jul 10 06:19:57 PM PDT 24
Peak memory 201864 kb
Host smart-713c4900-345c-43a2-9adb-7c4a9a14778b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718495660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.1718495660
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.2054279054
Short name T787
Test name
Test status
Simulation time 199572481408 ps
CPU time 61.96 seconds
Started Jul 10 06:18:27 PM PDT 24
Finished Jul 10 06:19:30 PM PDT 24
Peak memory 201880 kb
Host smart-8ea9ae18-72ca-4773-a39d-173990a2f741
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054279054 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.2054279054
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.4272586169
Short name T195
Test name
Test status
Simulation time 100456436245 ps
CPU time 544.38 seconds
Started Jul 10 06:18:33 PM PDT 24
Finished Jul 10 06:27:38 PM PDT 24
Peak memory 202208 kb
Host smart-5af8c392-cc6a-4a3e-8df1-8cf6c54d6b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272586169 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.4272586169
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.3354163157
Short name T752
Test name
Test status
Simulation time 25239184742 ps
CPU time 26.6 seconds
Started Jul 10 06:18:28 PM PDT 24
Finished Jul 10 06:18:56 PM PDT 24
Peak memory 201692 kb
Host smart-85936ecd-191e-40b4-9844-322c2a0e87e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354163157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.3354163157
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.1021258588
Short name T395
Test name
Test status
Simulation time 2882214193 ps
CPU time 2.37 seconds
Started Jul 10 06:18:27 PM PDT 24
Finished Jul 10 06:18:30 PM PDT 24
Peak memory 201676 kb
Host smart-d517ac35-c5c8-4dd4-b928-f970056d7b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021258588 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.1021258588
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.4256608537
Short name T496
Test name
Test status
Simulation time 5566215054 ps
CPU time 6.83 seconds
Started Jul 10 06:18:18 PM PDT 24
Finished Jul 10 06:18:26 PM PDT 24
Peak memory 201720 kb
Host smart-01bbcd0e-02dd-41c6-a68b-aadeebd77288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256608537 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.4256608537
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3511360407
Short name T344
Test name
Test status
Simulation time 302001324032 ps
CPU time 704.38 seconds
Started Jul 10 06:18:35 PM PDT 24
Finished Jul 10 06:30:20 PM PDT 24
Peak memory 202188 kb
Host smart-f7a6cc40-c15b-453d-b882-55d289e090ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511360407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3511360407
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2183660696
Short name T317
Test name
Test status
Simulation time 314060879044 ps
CPU time 174.91 seconds
Started Jul 10 06:18:33 PM PDT 24
Finished Jul 10 06:21:28 PM PDT 24
Peak memory 210536 kb
Host smart-b7b43cd3-d550-4528-892c-bdc269ecc20e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183660696 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2183660696
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.137765799
Short name T627
Test name
Test status
Simulation time 460796757 ps
CPU time 1.58 seconds
Started Jul 10 06:18:40 PM PDT 24
Finished Jul 10 06:18:42 PM PDT 24
Peak memory 201640 kb
Host smart-4fa7c052-fcbb-4dc7-b1eb-d401895ea347
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137765799 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.137765799
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1524941404
Short name T169
Test name
Test status
Simulation time 518515833561 ps
CPU time 116.89 seconds
Started Jul 10 06:18:40 PM PDT 24
Finished Jul 10 06:20:37 PM PDT 24
Peak memory 201856 kb
Host smart-be11c1fa-610d-4456-9655-f1e80e841b12
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524941404 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1524941404
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.539478245
Short name T686
Test name
Test status
Simulation time 163460907026 ps
CPU time 81.44 seconds
Started Jul 10 06:18:37 PM PDT 24
Finished Jul 10 06:19:59 PM PDT 24
Peak memory 201856 kb
Host smart-2ea87c9a-aea0-4347-b228-d7714cdbc6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539478245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.539478245
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.609156128
Short name T248
Test name
Test status
Simulation time 495365496764 ps
CPU time 1082.7 seconds
Started Jul 10 06:18:38 PM PDT 24
Finished Jul 10 06:36:42 PM PDT 24
Peak memory 202000 kb
Host smart-02aa76ec-fa6a-4ca2-b196-ec3d82483655
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609156128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.609156128
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.1617176850
Short name T733
Test name
Test status
Simulation time 329175175448 ps
CPU time 732.69 seconds
Started Jul 10 06:18:39 PM PDT 24
Finished Jul 10 06:30:52 PM PDT 24
Peak memory 201936 kb
Host smart-6f07bfab-03c9-4024-a90e-fb77f4c0c1f6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617176850 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.1617176850
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.1670136906
Short name T44
Test name
Test status
Simulation time 330047565114 ps
CPU time 719.9 seconds
Started Jul 10 06:18:35 PM PDT 24
Finished Jul 10 06:30:35 PM PDT 24
Peak memory 201896 kb
Host smart-5e477757-02bf-478f-a64b-e84e5ab9a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670136906 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.1670136906
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.3615919969
Short name T530
Test name
Test status
Simulation time 487493674223 ps
CPU time 294.66 seconds
Started Jul 10 06:18:38 PM PDT 24
Finished Jul 10 06:23:33 PM PDT 24
Peak memory 201864 kb
Host smart-d7cda549-bac3-4639-997a-e3b88a8cca43
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615919969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.3615919969
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2465171246
Short name T289
Test name
Test status
Simulation time 369652824024 ps
CPU time 431.41 seconds
Started Jul 10 06:18:39 PM PDT 24
Finished Jul 10 06:25:51 PM PDT 24
Peak memory 201960 kb
Host smart-9fa952a6-4cf8-430f-bbb7-5916ab71e85a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465171246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2465171246
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.207064068
Short name T704
Test name
Test status
Simulation time 211292298556 ps
CPU time 461.97 seconds
Started Jul 10 06:18:39 PM PDT 24
Finished Jul 10 06:26:22 PM PDT 24
Peak memory 201880 kb
Host smart-12530fb9-9131-4625-ba9e-bac3e9f1734b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207064068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.
adc_ctrl_filters_wakeup_fixed.207064068
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.2625038376
Short name T201
Test name
Test status
Simulation time 101883830227 ps
CPU time 357 seconds
Started Jul 10 06:18:38 PM PDT 24
Finished Jul 10 06:24:36 PM PDT 24
Peak memory 202280 kb
Host smart-f4206d4e-12b5-409b-b97e-4007f589abe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625038376 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.2625038376
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.3544528742
Short name T347
Test name
Test status
Simulation time 43126430943 ps
CPU time 24.05 seconds
Started Jul 10 06:18:38 PM PDT 24
Finished Jul 10 06:19:03 PM PDT 24
Peak memory 201708 kb
Host smart-37585ab6-8b33-4cb0-9d3c-1206697eba73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544528742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.3544528742
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1264371264
Short name T113
Test name
Test status
Simulation time 3089602807 ps
CPU time 7.53 seconds
Started Jul 10 06:18:39 PM PDT 24
Finished Jul 10 06:18:47 PM PDT 24
Peak memory 201708 kb
Host smart-0335372b-46b6-4194-8865-59995d595a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264371264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1264371264
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.3918174764
Short name T407
Test name
Test status
Simulation time 5872366438 ps
CPU time 13.01 seconds
Started Jul 10 06:18:34 PM PDT 24
Finished Jul 10 06:18:47 PM PDT 24
Peak memory 201704 kb
Host smart-1c0211bf-aee7-4a59-b149-39005723d434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918174764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.3918174764
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.3112152619
Short name T283
Test name
Test status
Simulation time 65603445871 ps
CPU time 18.61 seconds
Started Jul 10 06:18:38 PM PDT 24
Finished Jul 10 06:18:58 PM PDT 24
Peak memory 210288 kb
Host smart-a2218768-7afe-47cf-b633-625334696998
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112152619 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.3112152619
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.4023841846
Short name T461
Test name
Test status
Simulation time 542364829 ps
CPU time 1 seconds
Started Jul 10 06:18:49 PM PDT 24
Finished Jul 10 06:18:51 PM PDT 24
Peak memory 201640 kb
Host smart-1899aebd-8716-4762-8e8e-a20934d7337a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023841846 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.4023841846
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.4161987139
Short name T668
Test name
Test status
Simulation time 534418452634 ps
CPU time 434.39 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:26:00 PM PDT 24
Peak memory 201920 kb
Host smart-d886d243-a4ea-4168-bc50-0704fdf338b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161987139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.4161987139
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3156993876
Short name T665
Test name
Test status
Simulation time 374097332792 ps
CPU time 461.45 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:26:27 PM PDT 24
Peak memory 201900 kb
Host smart-b1d865b7-72ef-427b-b026-9a67e83b99b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156993876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3156993876
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.3568599419
Short name T659
Test name
Test status
Simulation time 159706224670 ps
CPU time 334.9 seconds
Started Jul 10 06:18:42 PM PDT 24
Finished Jul 10 06:24:18 PM PDT 24
Peak memory 201816 kb
Host smart-ecda936a-a50f-4ac1-924d-3768b8fbb033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568599419 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.3568599419
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.1960968242
Short name T420
Test name
Test status
Simulation time 337062397122 ps
CPU time 559.66 seconds
Started Jul 10 06:18:45 PM PDT 24
Finished Jul 10 06:28:05 PM PDT 24
Peak memory 201876 kb
Host smart-56cd4178-25cb-4724-a867-68f2b5e8af54
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960968242 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.1960968242
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2932547272
Short name T188
Test name
Test status
Simulation time 491656326269 ps
CPU time 376.66 seconds
Started Jul 10 06:18:37 PM PDT 24
Finished Jul 10 06:24:54 PM PDT 24
Peak memory 201896 kb
Host smart-8e0f8ee9-3d56-405d-ba5e-01aaa98f6a45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932547272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2932547272
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.1079056290
Short name T452
Test name
Test status
Simulation time 487237079365 ps
CPU time 303.08 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:23:48 PM PDT 24
Peak memory 201860 kb
Host smart-e5328dfd-4d4b-4e54-8bd3-a90a57c1fef1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1079056290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fix
ed.1079056290
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.4160458777
Short name T312
Test name
Test status
Simulation time 167040023045 ps
CPU time 397.28 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:25:22 PM PDT 24
Peak memory 201896 kb
Host smart-13f6277e-9bce-48f4-9bd0-92a1014a0ccb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160458777 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters
_wakeup.4160458777
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3152437272
Short name T408
Test name
Test status
Simulation time 199705277137 ps
CPU time 215.73 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:22:21 PM PDT 24
Peak memory 201872 kb
Host smart-f710da96-d390-4550-a6c3-a15af0295ac6
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152437272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3152437272
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.3826475527
Short name T435
Test name
Test status
Simulation time 24557450915 ps
CPU time 14.12 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:18:59 PM PDT 24
Peak memory 201696 kb
Host smart-93ff5595-4c2f-4127-aa44-f0c4ba9932ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826475527 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.3826475527
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.2433804837
Short name T538
Test name
Test status
Simulation time 4726831947 ps
CPU time 11.51 seconds
Started Jul 10 06:18:44 PM PDT 24
Finished Jul 10 06:18:57 PM PDT 24
Peak memory 201596 kb
Host smart-5500a82a-0e21-4628-aced-e0dd10dda1de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433804837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.2433804837
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.442541802
Short name T657
Test name
Test status
Simulation time 5789009598 ps
CPU time 4.04 seconds
Started Jul 10 06:18:39 PM PDT 24
Finished Jul 10 06:18:44 PM PDT 24
Peak memory 201692 kb
Host smart-844dc978-d446-4fbb-98d1-80aeaf113662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442541802 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.442541802
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.1524366597
Short name T763
Test name
Test status
Simulation time 339557766530 ps
CPU time 110.95 seconds
Started Jul 10 06:18:51 PM PDT 24
Finished Jul 10 06:20:42 PM PDT 24
Peak memory 201880 kb
Host smart-0f6c9572-dd39-42d0-ab45-c76b8e7d1b68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524366597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.1524366597
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.665320149
Short name T634
Test name
Test status
Simulation time 505286457 ps
CPU time 1.76 seconds
Started Jul 10 06:18:59 PM PDT 24
Finished Jul 10 06:19:02 PM PDT 24
Peak memory 201640 kb
Host smart-a12c7d24-ec86-4d3b-90ca-66ed37cb77c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665320149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.665320149
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3850817768
Short name T494
Test name
Test status
Simulation time 339648522015 ps
CPU time 799.84 seconds
Started Jul 10 06:18:56 PM PDT 24
Finished Jul 10 06:32:16 PM PDT 24
Peak memory 201964 kb
Host smart-8f131b35-7864-4bf7-9879-0240b9401dee
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850817768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3850817768
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.1855404486
Short name T242
Test name
Test status
Simulation time 167215963011 ps
CPU time 106.48 seconds
Started Jul 10 06:18:54 PM PDT 24
Finished Jul 10 06:20:41 PM PDT 24
Peak memory 202004 kb
Host smart-aaca6f9a-1d4e-4fd1-9b1a-d52943cf2cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855404486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.1855404486
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.394557382
Short name T210
Test name
Test status
Simulation time 336514125607 ps
CPU time 219.9 seconds
Started Jul 10 06:18:58 PM PDT 24
Finished Jul 10 06:22:38 PM PDT 24
Peak memory 201792 kb
Host smart-9372b570-3a33-43c2-a1ea-1a90f4797e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394557382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.394557382
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.2616529511
Short name T615
Test name
Test status
Simulation time 162881042793 ps
CPU time 353.33 seconds
Started Jul 10 06:18:55 PM PDT 24
Finished Jul 10 06:24:49 PM PDT 24
Peak memory 201852 kb
Host smart-a4d527a2-cc5d-4bcb-b0fb-e8d633dfae4c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616529511 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.2616529511
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.1918804717
Short name T314
Test name
Test status
Simulation time 480293501454 ps
CPU time 1108.73 seconds
Started Jul 10 06:18:49 PM PDT 24
Finished Jul 10 06:37:19 PM PDT 24
Peak memory 201912 kb
Host smart-957022b3-68d6-4e91-99f5-b29ea3a1e6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918804717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.1918804717
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.1420621969
Short name T684
Test name
Test status
Simulation time 495385997309 ps
CPU time 1131.74 seconds
Started Jul 10 06:18:49 PM PDT 24
Finished Jul 10 06:37:42 PM PDT 24
Peak memory 201884 kb
Host smart-484dc1c8-0eb6-43cd-afa4-d9f9245748d0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420621969 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fix
ed.1420621969
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.938365670
Short name T580
Test name
Test status
Simulation time 518102388191 ps
CPU time 227.45 seconds
Started Jul 10 06:18:56 PM PDT 24
Finished Jul 10 06:22:44 PM PDT 24
Peak memory 201980 kb
Host smart-9553cb66-52bf-4635-97d4-f4043a0acd22
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938365670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_
wakeup.938365670
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.2030120918
Short name T520
Test name
Test status
Simulation time 410362960483 ps
CPU time 954.65 seconds
Started Jul 10 06:18:56 PM PDT 24
Finished Jul 10 06:34:52 PM PDT 24
Peak memory 201980 kb
Host smart-a8629f67-fddf-4e8d-b7ef-eee55ba29dd1
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030120918 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43
.adc_ctrl_filters_wakeup_fixed.2030120918
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.150353414
Short name T448
Test name
Test status
Simulation time 126035298897 ps
CPU time 386.3 seconds
Started Jul 10 06:19:03 PM PDT 24
Finished Jul 10 06:25:31 PM PDT 24
Peak memory 202268 kb
Host smart-0d21fb95-0c8e-483b-88db-6c1019bfe6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150353414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.150353414
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.4161143310
Short name T524
Test name
Test status
Simulation time 37278592396 ps
CPU time 21.76 seconds
Started Jul 10 06:19:03 PM PDT 24
Finished Jul 10 06:19:26 PM PDT 24
Peak memory 201696 kb
Host smart-d940743f-1f0f-4289-8988-9d71b8494cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161143310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.4161143310
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.572526285
Short name T111
Test name
Test status
Simulation time 4196604986 ps
CPU time 5.56 seconds
Started Jul 10 06:19:01 PM PDT 24
Finished Jul 10 06:19:07 PM PDT 24
Peak memory 201696 kb
Host smart-bd303522-1586-4012-a5b7-30a736db2aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572526285 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.572526285
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.3153361884
Short name T574
Test name
Test status
Simulation time 5735484788 ps
CPU time 12.62 seconds
Started Jul 10 06:18:49 PM PDT 24
Finished Jul 10 06:19:03 PM PDT 24
Peak memory 201688 kb
Host smart-6694735b-7578-42ae-8a89-25b6dad10185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153361884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.3153361884
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.937327533
Short name T23
Test name
Test status
Simulation time 16667231549 ps
CPU time 39.12 seconds
Started Jul 10 06:19:00 PM PDT 24
Finished Jul 10 06:19:40 PM PDT 24
Peak memory 210584 kb
Host smart-a9594f21-5967-4d64-b59d-08890d9c6ec7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937327533 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.937327533
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.3637796364
Short name T613
Test name
Test status
Simulation time 460350082 ps
CPU time 1.57 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:19:22 PM PDT 24
Peak memory 201652 kb
Host smart-bc923403-932d-4a3b-96a2-938305c30bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637796364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.3637796364
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.3295788424
Short name T216
Test name
Test status
Simulation time 327810096673 ps
CPU time 463.56 seconds
Started Jul 10 06:19:06 PM PDT 24
Finished Jul 10 06:26:51 PM PDT 24
Peak memory 201876 kb
Host smart-9f919b9f-ac9d-4545-bd78-eee2a9a8739c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295788424 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.3295788424
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.3466522396
Short name T762
Test name
Test status
Simulation time 325986232407 ps
CPU time 195.84 seconds
Started Jul 10 06:19:08 PM PDT 24
Finished Jul 10 06:22:25 PM PDT 24
Peak memory 201864 kb
Host smart-4cb8c936-7078-4bc3-96ab-c5dd30c4a369
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466522396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interru
pt_fixed.3466522396
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.3447853097
Short name T51
Test name
Test status
Simulation time 326596831371 ps
CPU time 345.9 seconds
Started Jul 10 06:19:00 PM PDT 24
Finished Jul 10 06:24:47 PM PDT 24
Peak memory 201872 kb
Host smart-30b48cd9-b50a-4d1c-9762-597955c33934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447853097 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.3447853097
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2114195101
Short name T109
Test name
Test status
Simulation time 498361618518 ps
CPU time 123.92 seconds
Started Jul 10 06:19:03 PM PDT 24
Finished Jul 10 06:21:08 PM PDT 24
Peak memory 201876 kb
Host smart-128c6e0f-7a92-4573-931b-b93d494ecbaa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114195101 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2114195101
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.504986823
Short name T316
Test name
Test status
Simulation time 511235192868 ps
CPU time 615.68 seconds
Started Jul 10 06:19:06 PM PDT 24
Finished Jul 10 06:29:23 PM PDT 24
Peak memory 201908 kb
Host smart-600f79c0-8e79-4b82-933b-847b893cb950
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504986823 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_
wakeup.504986823
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.342591007
Short name T509
Test name
Test status
Simulation time 199778252595 ps
CPU time 291.39 seconds
Started Jul 10 06:19:07 PM PDT 24
Finished Jul 10 06:24:00 PM PDT 24
Peak memory 201864 kb
Host smart-75bfc3a8-8a01-40b3-9f37-e6cf58b04876
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342591007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.
adc_ctrl_filters_wakeup_fixed.342591007
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.1252528143
Short name T493
Test name
Test status
Simulation time 94872906587 ps
CPU time 499.74 seconds
Started Jul 10 06:19:15 PM PDT 24
Finished Jul 10 06:27:35 PM PDT 24
Peak memory 202232 kb
Host smart-21f8f570-77cd-49b6-96bb-7e5101b70dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252528143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.1252528143
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.3219187696
Short name T499
Test name
Test status
Simulation time 30792658663 ps
CPU time 18.86 seconds
Started Jul 10 06:19:14 PM PDT 24
Finished Jul 10 06:19:33 PM PDT 24
Peak memory 201672 kb
Host smart-f6b0d342-7550-4609-ac8c-36ca37fb73fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219187696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.3219187696
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.2953060093
Short name T758
Test name
Test status
Simulation time 4690248866 ps
CPU time 11.84 seconds
Started Jul 10 06:19:13 PM PDT 24
Finished Jul 10 06:19:26 PM PDT 24
Peak memory 201708 kb
Host smart-101ebfbd-065c-49db-8daa-e347b643ca2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953060093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.2953060093
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2299323813
Short name T517
Test name
Test status
Simulation time 5872695948 ps
CPU time 2.33 seconds
Started Jul 10 06:19:03 PM PDT 24
Finished Jul 10 06:19:06 PM PDT 24
Peak memory 201692 kb
Host smart-72a412be-7b24-464a-8646-90822940368b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299323813 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2299323813
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1032157937
Short name T199
Test name
Test status
Simulation time 660362723125 ps
CPU time 439.64 seconds
Started Jul 10 06:19:23 PM PDT 24
Finished Jul 10 06:26:43 PM PDT 24
Peak memory 202256 kb
Host smart-cc429e0e-41c6-468f-8294-eff9a48dcd38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032157937 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1032157937
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.4003892350
Short name T25
Test name
Test status
Simulation time 23347890238 ps
CPU time 48.89 seconds
Started Jul 10 06:19:14 PM PDT 24
Finished Jul 10 06:20:04 PM PDT 24
Peak memory 202028 kb
Host smart-eb4295a4-7876-4724-8aac-d8785109a3f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003892350 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.4003892350
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.2723834727
Short name T50
Test name
Test status
Simulation time 525456461 ps
CPU time 1.72 seconds
Started Jul 10 06:19:28 PM PDT 24
Finished Jul 10 06:19:30 PM PDT 24
Peak memory 201628 kb
Host smart-a3555ce8-7edc-49c2-856e-b901aa599e62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723834727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.2723834727
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2063754670
Short name T333
Test name
Test status
Simulation time 177091309121 ps
CPU time 378.54 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:25:39 PM PDT 24
Peak memory 201940 kb
Host smart-64a9fa6d-954b-4b16-8aea-35d8932c18c8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063754670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2063754670
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.3283333540
Short name T731
Test name
Test status
Simulation time 335444531947 ps
CPU time 789.95 seconds
Started Jul 10 06:19:25 PM PDT 24
Finished Jul 10 06:32:36 PM PDT 24
Peak memory 201804 kb
Host smart-6fd8e261-9ea2-46e3-9cab-87318c93b041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283333540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.3283333540
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.660425202
Short name T238
Test name
Test status
Simulation time 487390830281 ps
CPU time 552.04 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:28:33 PM PDT 24
Peak memory 201896 kb
Host smart-42d623c6-baf9-44b2-8f83-2573207bef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660425202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.660425202
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.1177513066
Short name T545
Test name
Test status
Simulation time 325786611827 ps
CPU time 172.5 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:22:13 PM PDT 24
Peak memory 201920 kb
Host smart-a789bc17-cd09-4970-8ddb-065ae593f6c9
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177513066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.1177513066
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1037378853
Short name T525
Test name
Test status
Simulation time 488269784164 ps
CPU time 571.92 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:28:52 PM PDT 24
Peak memory 201952 kb
Host smart-2e1f58b8-9a8c-43b9-a19e-8d57ba8ca93a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037378853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1037378853
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.144795853
Short name T766
Test name
Test status
Simulation time 481949223196 ps
CPU time 1090.42 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:37:32 PM PDT 24
Peak memory 201896 kb
Host smart-339ab7d8-e98b-4ca5-a1d9-5f452359c260
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=144795853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fixe
d.144795853
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.4252647631
Short name T279
Test name
Test status
Simulation time 593240009453 ps
CPU time 351.07 seconds
Started Jul 10 06:19:21 PM PDT 24
Finished Jul 10 06:25:12 PM PDT 24
Peak memory 201968 kb
Host smart-71a27494-875f-4ab6-be8e-7394fde83310
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252647631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.4252647631
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.2126072550
Short name T386
Test name
Test status
Simulation time 597954058856 ps
CPU time 332 seconds
Started Jul 10 06:19:19 PM PDT 24
Finished Jul 10 06:24:52 PM PDT 24
Peak memory 201872 kb
Host smart-673780bc-c191-4e92-badd-b17066ea4dfc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126072550 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.2126072550
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.2371790167
Short name T691
Test name
Test status
Simulation time 72159160458 ps
CPU time 372.84 seconds
Started Jul 10 06:19:26 PM PDT 24
Finished Jul 10 06:25:39 PM PDT 24
Peak memory 202276 kb
Host smart-4d98b022-9951-41cb-a86e-27d6b21301b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371790167 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.2371790167
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.983765423
Short name T706
Test name
Test status
Simulation time 28691109480 ps
CPU time 14.93 seconds
Started Jul 10 06:19:26 PM PDT 24
Finished Jul 10 06:19:41 PM PDT 24
Peak memory 201704 kb
Host smart-1156d3c5-db79-4bd3-8904-e09c0560c141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983765423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.983765423
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.650136768
Short name T444
Test name
Test status
Simulation time 5578114087 ps
CPU time 3.76 seconds
Started Jul 10 06:19:25 PM PDT 24
Finished Jul 10 06:19:29 PM PDT 24
Peak memory 201600 kb
Host smart-5e3a3989-c617-4772-97ee-f63511b04d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650136768 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.650136768
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.2681507587
Short name T441
Test name
Test status
Simulation time 6120084778 ps
CPU time 13.82 seconds
Started Jul 10 06:19:20 PM PDT 24
Finished Jul 10 06:19:35 PM PDT 24
Peak memory 201688 kb
Host smart-930d8ed9-864c-4f84-ab85-0fd9b131391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681507587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.2681507587
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.2020190106
Short name T302
Test name
Test status
Simulation time 553818859950 ps
CPU time 960.71 seconds
Started Jul 10 06:19:29 PM PDT 24
Finished Jul 10 06:35:30 PM PDT 24
Peak memory 201924 kb
Host smart-c3e4eecc-19cc-4887-b268-253cfab877ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020190106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.2020190106
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.1057580375
Short name T521
Test name
Test status
Simulation time 150818552668 ps
CPU time 133.51 seconds
Started Jul 10 06:19:23 PM PDT 24
Finished Jul 10 06:21:37 PM PDT 24
Peak memory 210580 kb
Host smart-fea0e07f-4e48-41c4-83ac-3c6b33e0b91c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057580375 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.1057580375
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1860286722
Short name T644
Test name
Test status
Simulation time 326472422 ps
CPU time 1.01 seconds
Started Jul 10 06:19:36 PM PDT 24
Finished Jul 10 06:19:38 PM PDT 24
Peak memory 201660 kb
Host smart-00b6ae21-615b-47a6-af80-81b9f32f1c2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860286722 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1860286722
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1056311148
Short name T180
Test name
Test status
Simulation time 369658862248 ps
CPU time 69.02 seconds
Started Jul 10 06:19:30 PM PDT 24
Finished Jul 10 06:20:40 PM PDT 24
Peak memory 201880 kb
Host smart-5be01259-95bb-437b-84af-76cfadc134a3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056311148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1056311148
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.3354614597
Short name T791
Test name
Test status
Simulation time 327359362419 ps
CPU time 199.6 seconds
Started Jul 10 06:19:33 PM PDT 24
Finished Jul 10 06:22:53 PM PDT 24
Peak memory 201880 kb
Host smart-13244cfb-3366-48df-82d6-39d10d6052bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354614597 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.3354614597
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.3048439833
Short name T366
Test name
Test status
Simulation time 498198331100 ps
CPU time 557.99 seconds
Started Jul 10 06:19:31 PM PDT 24
Finished Jul 10 06:28:50 PM PDT 24
Peak memory 201864 kb
Host smart-34df3724-c73f-4649-934d-9e9772c7274e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048439833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.3048439833
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.2077701583
Short name T620
Test name
Test status
Simulation time 483781016695 ps
CPU time 505.83 seconds
Started Jul 10 06:19:25 PM PDT 24
Finished Jul 10 06:27:51 PM PDT 24
Peak memory 201908 kb
Host smart-f847e2fc-8c9b-4055-bbb3-2e25cf7c7af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077701583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.2077701583
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.3984262862
Short name T720
Test name
Test status
Simulation time 490499373429 ps
CPU time 1126.8 seconds
Started Jul 10 06:19:31 PM PDT 24
Finished Jul 10 06:38:18 PM PDT 24
Peak memory 201932 kb
Host smart-dbaf48a4-0202-4a26-a060-3b5c90b14499
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984262862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.3984262862
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3345163688
Short name T143
Test name
Test status
Simulation time 350963825029 ps
CPU time 356.5 seconds
Started Jul 10 06:19:30 PM PDT 24
Finished Jul 10 06:25:27 PM PDT 24
Peak memory 201948 kb
Host smart-35dbe34a-d298-4c72-a17b-8dff028d6602
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345163688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3345163688
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.3833595364
Short name T417
Test name
Test status
Simulation time 406444357640 ps
CPU time 162.92 seconds
Started Jul 10 06:19:31 PM PDT 24
Finished Jul 10 06:22:14 PM PDT 24
Peak memory 201872 kb
Host smart-0f1800f7-c6d0-439f-90fe-4bc65ba5ac8e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833595364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46
.adc_ctrl_filters_wakeup_fixed.3833595364
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.262146012
Short name T543
Test name
Test status
Simulation time 61985856996 ps
CPU time 244.95 seconds
Started Jul 10 06:19:30 PM PDT 24
Finished Jul 10 06:23:36 PM PDT 24
Peak memory 202216 kb
Host smart-b56186d6-7680-4ec7-9b8d-04261edbeb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262146012 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.262146012
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.2070353225
Short name T573
Test name
Test status
Simulation time 30023057081 ps
CPU time 13.01 seconds
Started Jul 10 06:19:31 PM PDT 24
Finished Jul 10 06:19:45 PM PDT 24
Peak memory 201692 kb
Host smart-e13caac1-4697-434e-bfd7-e6e582fb76ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070353225 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.2070353225
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2624927914
Short name T742
Test name
Test status
Simulation time 4624940236 ps
CPU time 10.99 seconds
Started Jul 10 06:19:31 PM PDT 24
Finished Jul 10 06:19:43 PM PDT 24
Peak memory 201692 kb
Host smart-35d06472-c2db-4280-8073-a3db2644410b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624927914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2624927914
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.2402600094
Short name T135
Test name
Test status
Simulation time 5792579261 ps
CPU time 1.58 seconds
Started Jul 10 06:19:29 PM PDT 24
Finished Jul 10 06:19:31 PM PDT 24
Peak memory 201676 kb
Host smart-ef483385-2d02-4aaa-b602-2d8011a007ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402600094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.2402600094
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.835170449
Short name T680
Test name
Test status
Simulation time 36354034328 ps
CPU time 22.2 seconds
Started Jul 10 06:19:39 PM PDT 24
Finished Jul 10 06:20:01 PM PDT 24
Peak memory 201688 kb
Host smart-c2e8f073-73f1-473b-8d5b-fd8f276c4b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835170449 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all.
835170449
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all_with_rand_reset.868784741
Short name T698
Test name
Test status
Simulation time 263178667683 ps
CPU time 206.19 seconds
Started Jul 10 06:19:30 PM PDT 24
Finished Jul 10 06:22:57 PM PDT 24
Peak memory 210788 kb
Host smart-825478f6-1de0-4629-8e5f-2e68316651e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868784741 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all_with_rand_reset.868784741
Directory /workspace/46.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.701277479
Short name T379
Test name
Test status
Simulation time 320090945 ps
CPU time 0.79 seconds
Started Jul 10 06:19:41 PM PDT 24
Finished Jul 10 06:19:42 PM PDT 24
Peak memory 201704 kb
Host smart-5b49c8ca-3269-49ab-99b1-6ae94ef5d62f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701277479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.701277479
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.3622007290
Short name T652
Test name
Test status
Simulation time 535755001049 ps
CPU time 620.78 seconds
Started Jul 10 06:19:41 PM PDT 24
Finished Jul 10 06:30:02 PM PDT 24
Peak memory 201900 kb
Host smart-203c8d38-084f-4527-a99f-760f794152c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622007290 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.3622007290
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.4277614961
Short name T263
Test name
Test status
Simulation time 337561876338 ps
CPU time 745.79 seconds
Started Jul 10 06:19:35 PM PDT 24
Finished Jul 10 06:32:02 PM PDT 24
Peak memory 201912 kb
Host smart-fc8bfd38-09e6-4b2b-99bf-9120072aa688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277614961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.4277614961
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.1125125174
Short name T586
Test name
Test status
Simulation time 328976924611 ps
CPU time 759.18 seconds
Started Jul 10 06:19:36 PM PDT 24
Finished Jul 10 06:32:16 PM PDT 24
Peak memory 201876 kb
Host smart-55457108-caff-4822-80c2-067d0929313c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125125174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.1125125174
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.551374452
Short name T540
Test name
Test status
Simulation time 165751917854 ps
CPU time 317.78 seconds
Started Jul 10 06:19:37 PM PDT 24
Finished Jul 10 06:24:56 PM PDT 24
Peak memory 201976 kb
Host smart-df2189b0-bb17-48b9-a57c-366a6c70c67a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551374452 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.551374452
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.1810518440
Short name T616
Test name
Test status
Simulation time 331806874198 ps
CPU time 811.26 seconds
Started Jul 10 06:19:35 PM PDT 24
Finished Jul 10 06:33:07 PM PDT 24
Peak memory 201872 kb
Host smart-6446fba4-e0b3-4d95-94a9-b05158829659
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810518440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.1810518440
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.2935730508
Short name T716
Test name
Test status
Simulation time 261282300316 ps
CPU time 530.31 seconds
Started Jul 10 06:19:38 PM PDT 24
Finished Jul 10 06:28:29 PM PDT 24
Peak memory 201960 kb
Host smart-d3b318b6-9946-4675-b00f-d29c8d61ddbb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935730508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.2935730508
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.453548359
Short name T392
Test name
Test status
Simulation time 407204397451 ps
CPU time 423.27 seconds
Started Jul 10 06:19:41 PM PDT 24
Finished Jul 10 06:26:45 PM PDT 24
Peak memory 201892 kb
Host smart-90f40af6-1ac9-4e3a-9f2b-1db56231dbb4
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453548359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.
adc_ctrl_filters_wakeup_fixed.453548359
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.2405546831
Short name T783
Test name
Test status
Simulation time 85792394228 ps
CPU time 497.23 seconds
Started Jul 10 06:19:42 PM PDT 24
Finished Jul 10 06:28:00 PM PDT 24
Peak memory 202168 kb
Host smart-f69c7577-8ca9-4fca-8edc-923663301303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405546831 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.2405546831
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.3260411693
Short name T776
Test name
Test status
Simulation time 27923163097 ps
CPU time 64.86 seconds
Started Jul 10 06:19:41 PM PDT 24
Finished Jul 10 06:20:46 PM PDT 24
Peak memory 201692 kb
Host smart-e9a46a44-fae9-4a44-83a0-b21d0a701a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260411693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.3260411693
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.535663346
Short name T726
Test name
Test status
Simulation time 4655462735 ps
CPU time 11.53 seconds
Started Jul 10 06:19:40 PM PDT 24
Finished Jul 10 06:19:52 PM PDT 24
Peak memory 201704 kb
Host smart-260a9a35-4127-4dae-9e79-245774ed3080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535663346 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.535663346
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.554026541
Short name T501
Test name
Test status
Simulation time 5706584629 ps
CPU time 2.51 seconds
Started Jul 10 06:19:36 PM PDT 24
Finished Jul 10 06:19:39 PM PDT 24
Peak memory 201704 kb
Host smart-48e10b6f-7a02-4718-ae78-e3072e81e659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554026541 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.554026541
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.2172815797
Short name T46
Test name
Test status
Simulation time 495622335512 ps
CPU time 307.59 seconds
Started Jul 10 06:19:41 PM PDT 24
Finished Jul 10 06:24:50 PM PDT 24
Peak memory 201876 kb
Host smart-9882b86a-cb70-489f-a4aa-400be3ac6460
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172815797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all
.2172815797
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.966804804
Short name T280
Test name
Test status
Simulation time 59497123566 ps
CPU time 82.67 seconds
Started Jul 10 06:19:42 PM PDT 24
Finished Jul 10 06:21:05 PM PDT 24
Peak memory 210296 kb
Host smart-1d610f63-e29c-40aa-9ca0-e57187030ce7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966804804 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.966804804
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.943758194
Short name T349
Test name
Test status
Simulation time 317663379 ps
CPU time 0.97 seconds
Started Jul 10 06:19:51 PM PDT 24
Finished Jul 10 06:19:53 PM PDT 24
Peak memory 201640 kb
Host smart-3b1d0807-49f8-4f90-9144-849b2b91c71d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943758194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.943758194
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.3936858646
Short name T674
Test name
Test status
Simulation time 169710809483 ps
CPU time 57.96 seconds
Started Jul 10 06:19:54 PM PDT 24
Finished Jul 10 06:20:53 PM PDT 24
Peak memory 201956 kb
Host smart-a8aa72f3-d849-4dbd-ab8b-464efb74d1ff
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936858646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.3936858646
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.4116511890
Short name T753
Test name
Test status
Simulation time 189255325027 ps
CPU time 56.32 seconds
Started Jul 10 06:19:50 PM PDT 24
Finished Jul 10 06:20:47 PM PDT 24
Peak memory 201900 kb
Host smart-18174f8d-c65a-446c-b7bd-23f91d960a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116511890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.4116511890
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3047961883
Short name T218
Test name
Test status
Simulation time 489701115880 ps
CPU time 296.58 seconds
Started Jul 10 06:19:47 PM PDT 24
Finished Jul 10 06:24:45 PM PDT 24
Peak memory 201900 kb
Host smart-a8334f15-0da7-4c24-a9df-b1e9f03bb630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047961883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3047961883
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.1524439698
Short name T557
Test name
Test status
Simulation time 486834526856 ps
CPU time 556.53 seconds
Started Jul 10 06:19:46 PM PDT 24
Finished Jul 10 06:29:03 PM PDT 24
Peak memory 201876 kb
Host smart-839f6e60-5a44-4957-b1cb-d4d3cbc85b97
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524439698 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interru
pt_fixed.1524439698
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.1200219775
Short name T705
Test name
Test status
Simulation time 484855681434 ps
CPU time 1170.33 seconds
Started Jul 10 06:19:47 PM PDT 24
Finished Jul 10 06:39:18 PM PDT 24
Peak memory 201864 kb
Host smart-951cf59e-a941-4adf-bf21-31e6d55c3169
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200219775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fix
ed.1200219775
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.2504370717
Short name T759
Test name
Test status
Simulation time 525178167034 ps
CPU time 1130.49 seconds
Started Jul 10 06:19:45 PM PDT 24
Finished Jul 10 06:38:36 PM PDT 24
Peak memory 201876 kb
Host smart-295e37ec-2e76-4a05-8ae6-d4de11dde7a7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504370717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.2504370717
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.445483848
Short name T365
Test name
Test status
Simulation time 207480232319 ps
CPU time 309.83 seconds
Started Jul 10 06:19:48 PM PDT 24
Finished Jul 10 06:24:58 PM PDT 24
Peak memory 201956 kb
Host smart-6cc1f54d-0490-4976-a032-52e6fd5589ac
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445483848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.
adc_ctrl_filters_wakeup_fixed.445483848
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.3005361549
Short name T734
Test name
Test status
Simulation time 92921850764 ps
CPU time 525.36 seconds
Started Jul 10 06:19:54 PM PDT 24
Finished Jul 10 06:28:40 PM PDT 24
Peak memory 202228 kb
Host smart-4e7715c8-4568-4f00-9c04-dec258579acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005361549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.3005361549
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.2019814329
Short name T398
Test name
Test status
Simulation time 22229529901 ps
CPU time 16.72 seconds
Started Jul 10 06:19:53 PM PDT 24
Finished Jul 10 06:20:10 PM PDT 24
Peak memory 201696 kb
Host smart-45c98200-964f-45e1-a148-3cf2fb2a16ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019814329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.2019814329
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.1473276154
Short name T610
Test name
Test status
Simulation time 4173328062 ps
CPU time 5.38 seconds
Started Jul 10 06:19:51 PM PDT 24
Finished Jul 10 06:19:57 PM PDT 24
Peak memory 201688 kb
Host smart-3b7b4244-1e6b-4a08-b670-96706fd25f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473276154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.1473276154
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3047312514
Short name T559
Test name
Test status
Simulation time 5977203380 ps
CPU time 4.16 seconds
Started Jul 10 06:19:46 PM PDT 24
Finished Jul 10 06:19:50 PM PDT 24
Peak memory 201688 kb
Host smart-c636f476-e688-4bd8-8a4a-18d7b1ac138a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047312514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3047312514
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.3147619507
Short name T342
Test name
Test status
Simulation time 145956273210 ps
CPU time 535.13 seconds
Started Jul 10 06:19:52 PM PDT 24
Finished Jul 10 06:28:47 PM PDT 24
Peak memory 210404 kb
Host smart-432a21dc-e6f3-4259-959a-a03186f04157
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3147619507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.3147619507
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.2747322633
Short name T588
Test name
Test status
Simulation time 299016404 ps
CPU time 0.99 seconds
Started Jul 10 06:20:06 PM PDT 24
Finished Jul 10 06:20:08 PM PDT 24
Peak memory 201640 kb
Host smart-220775b8-64ad-4dd5-be17-f3eb7f5b9a6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747322633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.2747322633
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2855427372
Short name T728
Test name
Test status
Simulation time 162900138772 ps
CPU time 187.99 seconds
Started Jul 10 06:20:05 PM PDT 24
Finished Jul 10 06:23:14 PM PDT 24
Peak memory 201936 kb
Host smart-9d376446-1227-4f44-af6c-474829f56c77
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855427372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2855427372
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.3501427554
Short name T332
Test name
Test status
Simulation time 332027844576 ps
CPU time 296.69 seconds
Started Jul 10 06:20:02 PM PDT 24
Finished Jul 10 06:24:59 PM PDT 24
Peak memory 201892 kb
Host smart-4c841ee9-8fc5-481a-b313-61aeeab022c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501427554 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.3501427554
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.260856302
Short name T552
Test name
Test status
Simulation time 495682106399 ps
CPU time 854.66 seconds
Started Jul 10 06:20:00 PM PDT 24
Finished Jul 10 06:34:15 PM PDT 24
Peak memory 201888 kb
Host smart-b9001347-c548-4bf8-8566-ec3d49e07ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260856302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.260856302
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.68453871
Short name T101
Test name
Test status
Simulation time 161602901306 ps
CPU time 339.02 seconds
Started Jul 10 06:19:58 PM PDT 24
Finished Jul 10 06:25:38 PM PDT 24
Peak memory 201864 kb
Host smart-a51a98c5-9443-4185-9039-35afe7ec212f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=68453871 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt
_fixed.68453871
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.1278219390
Short name T626
Test name
Test status
Simulation time 163493916357 ps
CPU time 86.01 seconds
Started Jul 10 06:20:01 PM PDT 24
Finished Jul 10 06:21:28 PM PDT 24
Peak memory 201884 kb
Host smart-97979b01-9d93-4bb0-8411-2769672479bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278219390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.1278219390
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3542609681
Short name T177
Test name
Test status
Simulation time 160136539729 ps
CPU time 47.55 seconds
Started Jul 10 06:20:00 PM PDT 24
Finished Jul 10 06:20:48 PM PDT 24
Peak memory 201888 kb
Host smart-a4b799f8-6511-4425-a296-dc110a406ebc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542609681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3542609681
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.3790438876
Short name T252
Test name
Test status
Simulation time 553597266306 ps
CPU time 1189.03 seconds
Started Jul 10 06:20:04 PM PDT 24
Finished Jul 10 06:39:54 PM PDT 24
Peak memory 201980 kb
Host smart-a8666730-1e60-4819-81dd-9ed247d5c99a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790438876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.3790438876
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.2140502736
Short name T792
Test name
Test status
Simulation time 197606137292 ps
CPU time 234.87 seconds
Started Jul 10 06:20:05 PM PDT 24
Finished Jul 10 06:24:01 PM PDT 24
Peak memory 201916 kb
Host smart-5a3a46dc-d337-4d31-b1d0-1f38ec29098b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140502736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49
.adc_ctrl_filters_wakeup_fixed.2140502736
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.2970987393
Short name T675
Test name
Test status
Simulation time 64033007452 ps
CPU time 250.28 seconds
Started Jul 10 06:20:05 PM PDT 24
Finished Jul 10 06:24:17 PM PDT 24
Peak memory 202244 kb
Host smart-1fa1b593-3e29-4c2c-bd55-619e0ef4a3dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970987393 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.2970987393
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.1222876413
Short name T403
Test name
Test status
Simulation time 29772570549 ps
CPU time 17.33 seconds
Started Jul 10 06:20:04 PM PDT 24
Finished Jul 10 06:20:23 PM PDT 24
Peak memory 201688 kb
Host smart-b654ce3b-0cee-420b-a963-3489421c3263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222876413 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.1222876413
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.370302761
Short name T576
Test name
Test status
Simulation time 5203141126 ps
CPU time 6.62 seconds
Started Jul 10 06:20:06 PM PDT 24
Finished Jul 10 06:20:13 PM PDT 24
Peak memory 201696 kb
Host smart-7b82d17d-e20f-4f5d-8e1f-275b1c34f11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370302761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.370302761
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.2660705894
Short name T637
Test name
Test status
Simulation time 6077020643 ps
CPU time 2.11 seconds
Started Jul 10 06:20:00 PM PDT 24
Finished Jul 10 06:20:03 PM PDT 24
Peak memory 201700 kb
Host smart-8baaa8e7-1fb4-46cc-89f6-e0646b9b9a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660705894 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.2660705894
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.1071155930
Short name T629
Test name
Test status
Simulation time 189669209841 ps
CPU time 517.07 seconds
Started Jul 10 06:20:04 PM PDT 24
Finished Jul 10 06:28:42 PM PDT 24
Peak memory 211660 kb
Host smart-7855a90d-8f4e-4259-8f4f-cf1358dd81da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071155930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.1071155930
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.3739893817
Short name T285
Test name
Test status
Simulation time 110447298161 ps
CPU time 57.78 seconds
Started Jul 10 06:20:04 PM PDT 24
Finished Jul 10 06:21:03 PM PDT 24
Peak memory 213280 kb
Host smart-8d4711c9-6af7-488c-9b7c-6195f75ff0a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739893817 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.3739893817
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.692860142
Short name T431
Test name
Test status
Simulation time 408179049 ps
CPU time 1.14 seconds
Started Jul 10 06:15:34 PM PDT 24
Finished Jul 10 06:15:36 PM PDT 24
Peak memory 201640 kb
Host smart-36924805-a621-480e-b0a5-05c058c947e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692860142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.692860142
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.3387349427
Short name T145
Test name
Test status
Simulation time 162643215558 ps
CPU time 20.98 seconds
Started Jul 10 06:15:40 PM PDT 24
Finished Jul 10 06:16:03 PM PDT 24
Peak memory 201952 kb
Host smart-326d8f28-bdc3-4173-a1f5-accb9a1d3f1c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387349427 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.3387349427
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.3776647547
Short name T141
Test name
Test status
Simulation time 398136798479 ps
CPU time 248.08 seconds
Started Jul 10 06:15:35 PM PDT 24
Finished Jul 10 06:19:44 PM PDT 24
Peak memory 201956 kb
Host smart-bfd6beb8-7770-461b-8dd8-e76d24a80d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776647547 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.3776647547
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1050178932
Short name T249
Test name
Test status
Simulation time 327527802626 ps
CPU time 693.99 seconds
Started Jul 10 06:15:36 PM PDT 24
Finished Jul 10 06:27:11 PM PDT 24
Peak memory 201900 kb
Host smart-55a28b20-b105-4c1e-933a-dd22dc360d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050178932 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1050178932
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.1866831914
Short name T653
Test name
Test status
Simulation time 493280568662 ps
CPU time 1210.44 seconds
Started Jul 10 06:15:33 PM PDT 24
Finished Jul 10 06:35:45 PM PDT 24
Peak memory 201872 kb
Host smart-833dfd6e-b441-4650-9d3a-12b84887a85f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866831914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.1866831914
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2690153223
Short name T257
Test name
Test status
Simulation time 329257995480 ps
CPU time 371.54 seconds
Started Jul 10 06:15:37 PM PDT 24
Finished Jul 10 06:21:49 PM PDT 24
Peak memory 201900 kb
Host smart-d5a1eeb1-f2a6-4396-901d-2d5a161dd617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690153223 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2690153223
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.501323626
Short name T696
Test name
Test status
Simulation time 327073732296 ps
CPU time 374.04 seconds
Started Jul 10 06:15:37 PM PDT 24
Finished Jul 10 06:21:53 PM PDT 24
Peak memory 201944 kb
Host smart-38f285e0-d75c-4c0b-a68f-8a7db93f2021
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=501323626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixed
.501323626
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1690213881
Short name T709
Test name
Test status
Simulation time 184832781473 ps
CPU time 106.87 seconds
Started Jul 10 06:15:35 PM PDT 24
Finished Jul 10 06:17:23 PM PDT 24
Peak memory 201800 kb
Host smart-db633897-8100-4203-8976-41bc2d029324
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690213881 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1690213881
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.2715769599
Short name T190
Test name
Test status
Simulation time 410425417975 ps
CPU time 67.57 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:17:00 PM PDT 24
Peak memory 201860 kb
Host smart-6c100b9b-e6d1-43c5-8064-852817b9a9a5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715769599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.2715769599
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.2239154750
Short name T204
Test name
Test status
Simulation time 136941562525 ps
CPU time 515.65 seconds
Started Jul 10 06:15:28 PM PDT 24
Finished Jul 10 06:24:06 PM PDT 24
Peak memory 202216 kb
Host smart-03592c11-aa05-411d-961f-f94445112c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239154750 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.2239154750
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1925819806
Short name T500
Test name
Test status
Simulation time 42344134173 ps
CPU time 98.18 seconds
Started Jul 10 06:15:31 PM PDT 24
Finished Jul 10 06:17:10 PM PDT 24
Peak memory 201704 kb
Host smart-fa66dfab-dd00-424d-be7f-d33df8439331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925819806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1925819806
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.4032772696
Short name T760
Test name
Test status
Simulation time 3357605494 ps
CPU time 8.18 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:15:52 PM PDT 24
Peak memory 201676 kb
Host smart-2aeee6e8-8634-48b2-b6d7-90081a0d38cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032772696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.4032772696
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.3097521332
Short name T39
Test name
Test status
Simulation time 5752134567 ps
CPU time 2.48 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:15:45 PM PDT 24
Peak memory 201616 kb
Host smart-69c073ab-af0d-4877-8ba1-f5e5c3bcb298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097521332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.3097521332
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.1642743897
Short name T315
Test name
Test status
Simulation time 266332016944 ps
CPU time 516.03 seconds
Started Jul 10 06:15:37 PM PDT 24
Finished Jul 10 06:24:14 PM PDT 24
Peak memory 202248 kb
Host smart-f304dbea-10fa-4ba6-b698-e6fe22bcb451
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642743897 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
1642743897
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.1759971405
Short name T205
Test name
Test status
Simulation time 299316228531 ps
CPU time 450.01 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:23:19 PM PDT 24
Peak memory 218444 kb
Host smart-19f18953-be55-431c-846f-665295deb03f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1759971405 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.1759971405
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.3872903080
Short name T57
Test name
Test status
Simulation time 434579134 ps
CPU time 0.9 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:15:49 PM PDT 24
Peak memory 201636 kb
Host smart-53d5cdbe-e39d-4eff-a8a4-df51b4391415
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872903080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.3872903080
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.3323016795
Short name T736
Test name
Test status
Simulation time 191993024373 ps
CPU time 121.6 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:17:50 PM PDT 24
Peak memory 201944 kb
Host smart-b375e4b7-a8ca-4eb6-ac35-8e57fa0cfeac
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323016795 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.3323016795
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.2311590797
Short name T222
Test name
Test status
Simulation time 161684923018 ps
CPU time 341.57 seconds
Started Jul 10 06:15:37 PM PDT 24
Finished Jul 10 06:21:20 PM PDT 24
Peak memory 201900 kb
Host smart-b7fc7e57-172a-4772-ae96-ea4b74dd8d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311590797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.2311590797
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.2952880468
Short name T182
Test name
Test status
Simulation time 482955059191 ps
CPU time 279.62 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:20:28 PM PDT 24
Peak memory 201872 kb
Host smart-3a0e8eb1-41b1-401d-9263-64fefff6f95d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952880468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.2952880468
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.2375669862
Short name T108
Test name
Test status
Simulation time 163849579305 ps
CPU time 283.86 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:20:28 PM PDT 24
Peak memory 201896 kb
Host smart-dcf1c7bf-5728-4911-806e-bd508e586356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375669862 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.2375669862
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.1315343875
Short name T87
Test name
Test status
Simulation time 160176346693 ps
CPU time 203.58 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:19:13 PM PDT 24
Peak memory 201896 kb
Host smart-2763fe62-d938-40a1-9c2d-abfb4b9755a3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1315343875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixe
d.1315343875
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1724076657
Short name T594
Test name
Test status
Simulation time 173274138615 ps
CPU time 393.92 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:22:19 PM PDT 24
Peak memory 201960 kb
Host smart-c5ac2867-5838-4ff2-b017-3fabfedd9c9a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724076657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1724076657
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.3046999021
Short name T361
Test name
Test status
Simulation time 198416551941 ps
CPU time 211.55 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:19:17 PM PDT 24
Peak memory 201868 kb
Host smart-76e28dab-486b-4266-8c9e-d3b4fb803f93
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046999021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.3046999021
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.230854889
Short name T785
Test name
Test status
Simulation time 115181621488 ps
CPU time 564.44 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:25:09 PM PDT 24
Peak memory 202204 kb
Host smart-a7e666fe-8a96-4b74-ae1c-ef48a6b8868f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230854889 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.230854889
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.2809675456
Short name T396
Test name
Test status
Simulation time 28467094952 ps
CPU time 31 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:16:17 PM PDT 24
Peak memory 201696 kb
Host smart-d8689799-ec32-496c-b5ff-62377ce23900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809675456 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.2809675456
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.3102329136
Short name T370
Test name
Test status
Simulation time 2968956890 ps
CPU time 2.37 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:15:52 PM PDT 24
Peak memory 201712 kb
Host smart-df10ffaf-fa0e-4dba-a1fc-72c5f860477b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102329136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.3102329136
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1958818742
Short name T183
Test name
Test status
Simulation time 5858681383 ps
CPU time 7.75 seconds
Started Jul 10 06:15:37 PM PDT 24
Finished Jul 10 06:15:47 PM PDT 24
Peak memory 201688 kb
Host smart-cd7f2ecd-1ef3-4e38-b088-c2c7a9ef8fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958818742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1958818742
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2245496842
Short name T622
Test name
Test status
Simulation time 174201438295 ps
CPU time 390.48 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:22:21 PM PDT 24
Peak memory 201872 kb
Host smart-fc5a0624-69a1-49a3-a87b-dab1387e02b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245496842 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2245496842
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.243675418
Short name T563
Test name
Test status
Simulation time 44336913936 ps
CPU time 94.14 seconds
Started Jul 10 06:15:38 PM PDT 24
Finished Jul 10 06:17:13 PM PDT 24
Peak memory 210536 kb
Host smart-f4381b20-83c7-430e-9932-9378fdc9be7b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243675418 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.243675418
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3543756295
Short name T423
Test name
Test status
Simulation time 438631855 ps
CPU time 0.83 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:15:50 PM PDT 24
Peak memory 201624 kb
Host smart-82c2b965-326a-49c8-afc1-9950e0b81117
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543756295 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3543756295
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.1290287984
Short name T240
Test name
Test status
Simulation time 340585291639 ps
CPU time 723.66 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:27:50 PM PDT 24
Peak memory 201868 kb
Host smart-01074714-1655-4d1b-b097-bfba63ca1814
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290287984 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gati
ng.1290287984
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.1502869581
Short name T178
Test name
Test status
Simulation time 576231353801 ps
CPU time 148.99 seconds
Started Jul 10 06:15:39 PM PDT 24
Finished Jul 10 06:18:11 PM PDT 24
Peak memory 201892 kb
Host smart-9abbee61-b17a-4228-aeb7-c354e67f614d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502869581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.1502869581
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.1735787298
Short name T546
Test name
Test status
Simulation time 160830150567 ps
CPU time 287.33 seconds
Started Jul 10 06:15:40 PM PDT 24
Finished Jul 10 06:20:30 PM PDT 24
Peak memory 201920 kb
Host smart-e7502436-593e-4baa-9cbd-aded037092b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735787298 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.1735787298
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.1954340490
Short name T775
Test name
Test status
Simulation time 162908666217 ps
CPU time 60.97 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:16:46 PM PDT 24
Peak memory 201844 kb
Host smart-6fac9adf-85d4-43ac-931c-a23b5ea40c99
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954340490 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.1954340490
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.1061858495
Short name T623
Test name
Test status
Simulation time 167483492280 ps
CPU time 193.51 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:19:00 PM PDT 24
Peak memory 201872 kb
Host smart-73322875-19a5-498d-a7ad-cacdbddb0d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061858495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.1061858495
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.77362003
Short name T782
Test name
Test status
Simulation time 161648610775 ps
CPU time 179.06 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:18:55 PM PDT 24
Peak memory 201928 kb
Host smart-724d9cb5-fae6-4307-ac62-9d728a227db0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=77362003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixed.77362003
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.141657726
Short name T412
Test name
Test status
Simulation time 607055665273 ps
CPU time 99.44 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:17:31 PM PDT 24
Peak memory 201868 kb
Host smart-22defbcb-53e7-48cf-a1b1-d1e3908ecffa
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141657726 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.a
dc_ctrl_filters_wakeup_fixed.141657726
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1923050806
Short name T510
Test name
Test status
Simulation time 79490883665 ps
CPU time 396.21 seconds
Started Jul 10 06:15:42 PM PDT 24
Finished Jul 10 06:22:20 PM PDT 24
Peak memory 202224 kb
Host smart-055fd307-b1b4-4c87-872a-dfd5a2715cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923050806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1923050806
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.2924425468
Short name T418
Test name
Test status
Simulation time 29965897784 ps
CPU time 66.58 seconds
Started Jul 10 06:15:35 PM PDT 24
Finished Jul 10 06:16:48 PM PDT 24
Peak memory 201696 kb
Host smart-63eb804f-42a4-496a-a0e0-7a206ecc07a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924425468 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.2924425468
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.944619417
Short name T416
Test name
Test status
Simulation time 4296212580 ps
CPU time 5.83 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:15:54 PM PDT 24
Peak memory 201708 kb
Host smart-48d625d2-e347-4680-8fcb-6d864a51b421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944619417 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.944619417
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.4214522644
Short name T487
Test name
Test status
Simulation time 5946456320 ps
CPU time 7.64 seconds
Started Jul 10 06:15:38 PM PDT 24
Finished Jul 10 06:15:48 PM PDT 24
Peak memory 201704 kb
Host smart-cf0cac57-9075-460d-affa-fac53b32dc0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214522644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.4214522644
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3225914065
Short name T592
Test name
Test status
Simulation time 356876324985 ps
CPU time 190.28 seconds
Started Jul 10 06:15:42 PM PDT 24
Finished Jul 10 06:18:54 PM PDT 24
Peak memory 201884 kb
Host smart-c6c81a31-0fdd-496f-b7f6-4872a7f75fca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225914065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3225914065
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.2590779485
Short name T4
Test name
Test status
Simulation time 439334017 ps
CPU time 1.19 seconds
Started Jul 10 06:15:40 PM PDT 24
Finished Jul 10 06:15:43 PM PDT 24
Peak memory 201648 kb
Host smart-5c32cf97-dd36-4063-8a42-9a92a07f7b89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590779485 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.2590779485
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.1095887345
Short name T288
Test name
Test status
Simulation time 164613857893 ps
CPU time 100.43 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:17:27 PM PDT 24
Peak memory 201880 kb
Host smart-f4bc5398-6f6f-473d-b99e-f73422a31077
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095887345 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.1095887345
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.538552648
Short name T294
Test name
Test status
Simulation time 164924886769 ps
CPU time 396.6 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:22:26 PM PDT 24
Peak memory 201916 kb
Host smart-0f0d7b3e-3a95-411b-8f6e-8b313aecbd90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538552648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.538552648
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.4232720386
Short name T154
Test name
Test status
Simulation time 495394577747 ps
CPU time 113.04 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:17:39 PM PDT 24
Peak memory 202196 kb
Host smart-c26c0ede-56ca-4df3-9142-fae1750eaedd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232720386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.4232720386
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.2993153484
Short name T373
Test name
Test status
Simulation time 170374064497 ps
CPU time 190.26 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:18:55 PM PDT 24
Peak memory 201892 kb
Host smart-7c6bcd32-6fc0-49d2-ad43-02fc0658e828
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993153484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.2993153484
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.2393854197
Short name T433
Test name
Test status
Simulation time 163184804170 ps
CPU time 31.08 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:16:14 PM PDT 24
Peak memory 201900 kb
Host smart-4ea6c426-fd0a-49f9-8f49-878e9c1e93ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393854197 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.2393854197
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.2485122268
Short name T795
Test name
Test status
Simulation time 332330854144 ps
CPU time 181.68 seconds
Started Jul 10 06:15:41 PM PDT 24
Finished Jul 10 06:18:45 PM PDT 24
Peak memory 201872 kb
Host smart-77b7ecfb-b491-4d62-8889-a247d6228a00
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485122268 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.2485122268
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.3176210479
Short name T233
Test name
Test status
Simulation time 351205427856 ps
CPU time 206.7 seconds
Started Jul 10 06:15:42 PM PDT 24
Finished Jul 10 06:19:11 PM PDT 24
Peak memory 201896 kb
Host smart-e2f8ef84-bda6-4e9e-9d1c-a06f1a67b778
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176210479 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.3176210479
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.1844294993
Short name T422
Test name
Test status
Simulation time 602056201007 ps
CPU time 1277.29 seconds
Started Jul 10 06:15:44 PM PDT 24
Finished Jul 10 06:37:04 PM PDT 24
Peak memory 202104 kb
Host smart-5aff79ba-11b0-4da5-b628-624fb594617f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844294993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.1844294993
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.2490096079
Short name T338
Test name
Test status
Simulation time 116687124503 ps
CPU time 561.09 seconds
Started Jul 10 06:15:50 PM PDT 24
Finished Jul 10 06:25:14 PM PDT 24
Peak memory 202420 kb
Host smart-463d7c81-472d-4440-b249-da0b789f8871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490096079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.2490096079
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3865446198
Short name T404
Test name
Test status
Simulation time 45982198238 ps
CPU time 108.73 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:17:38 PM PDT 24
Peak memory 201716 kb
Host smart-5a02e63b-bcdc-4b60-93a9-13d7642b0e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865446198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3865446198
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1987684069
Short name T356
Test name
Test status
Simulation time 4732390441 ps
CPU time 5.94 seconds
Started Jul 10 06:15:57 PM PDT 24
Finished Jul 10 06:16:05 PM PDT 24
Peak memory 201692 kb
Host smart-b1a3283c-ca94-4095-bcea-a80f485bca41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987684069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1987684069
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.664484859
Short name T469
Test name
Test status
Simulation time 5792409804 ps
CPU time 15.14 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:16:04 PM PDT 24
Peak memory 201676 kb
Host smart-ac6dc5ff-95cd-4dec-b82e-3f39e8b6530a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664484859 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.664484859
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1714818896
Short name T264
Test name
Test status
Simulation time 170210279439 ps
CPU time 353.88 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:21:45 PM PDT 24
Peak memory 201892 kb
Host smart-837681ff-3c17-4a7c-9eb0-4167bdd165e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714818896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1714818896
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.261274501
Short name T20
Test name
Test status
Simulation time 29205582190 ps
CPU time 58.52 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:16:59 PM PDT 24
Peak memory 210252 kb
Host smart-7fc56023-2b38-4df7-96a7-26248035474b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261274501 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.261274501
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.2605431488
Short name T84
Test name
Test status
Simulation time 438424852 ps
CPU time 0.78 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:15:49 PM PDT 24
Peak memory 201636 kb
Host smart-af9507a2-9250-4822-95dd-113762c18181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605431488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.2605431488
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.856004961
Short name T607
Test name
Test status
Simulation time 162273177701 ps
CPU time 337.39 seconds
Started Jul 10 06:15:45 PM PDT 24
Finished Jul 10 06:21:26 PM PDT 24
Peak memory 201940 kb
Host smart-1710a882-63da-483c-a645-b5edafdfa099
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856004961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gatin
g.856004961
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.2793460693
Short name T243
Test name
Test status
Simulation time 529654115143 ps
CPU time 300.49 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:20:46 PM PDT 24
Peak memory 202020 kb
Host smart-1d66c17b-8b69-4ea1-84f9-22bf697be925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793460693 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.2793460693
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.1805498175
Short name T475
Test name
Test status
Simulation time 161651788120 ps
CPU time 390.89 seconds
Started Jul 10 06:15:38 PM PDT 24
Finished Jul 10 06:22:11 PM PDT 24
Peak memory 201876 kb
Host smart-5c7c7124-3e3b-4a89-bbad-b2ee48d374a7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805498175 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrup
t_fixed.1805498175
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.3405816149
Short name T693
Test name
Test status
Simulation time 161913660902 ps
CPU time 364.94 seconds
Started Jul 10 06:15:59 PM PDT 24
Finished Jul 10 06:22:06 PM PDT 24
Peak memory 202116 kb
Host smart-616082f7-9347-4794-8b4a-f2e688d18464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405816149 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.3405816149
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.280054201
Short name T612
Test name
Test status
Simulation time 327783863059 ps
CPU time 725.57 seconds
Started Jul 10 06:15:42 PM PDT 24
Finished Jul 10 06:27:49 PM PDT 24
Peak memory 201936 kb
Host smart-420b962b-2528-4128-a18e-914cad86873a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=280054201 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixed
.280054201
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.1358041294
Short name T325
Test name
Test status
Simulation time 242472097785 ps
CPU time 513.36 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:24:23 PM PDT 24
Peak memory 201892 kb
Host smart-84ed1738-c320-4d8d-a1f3-e311fa0d25e9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358041294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.1358041294
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1794812220
Short name T747
Test name
Test status
Simulation time 586128081012 ps
CPU time 321.47 seconds
Started Jul 10 06:15:39 PM PDT 24
Finished Jul 10 06:21:03 PM PDT 24
Peak memory 201892 kb
Host smart-c18877a2-8a09-46a2-8885-9ce9c69ae497
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794812220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1794812220
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1462046127
Short name T343
Test name
Test status
Simulation time 103007284279 ps
CPU time 382.36 seconds
Started Jul 10 06:15:53 PM PDT 24
Finished Jul 10 06:22:18 PM PDT 24
Peak memory 202220 kb
Host smart-0d44034a-1b4f-45f4-90d5-87813f0947c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462046127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1462046127
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4140685891
Short name T641
Test name
Test status
Simulation time 30618126606 ps
CPU time 37.04 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:16:26 PM PDT 24
Peak memory 201924 kb
Host smart-a5f8bad9-feab-485e-bb26-bd441cb13bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140685891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4140685891
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.1787596832
Short name T689
Test name
Test status
Simulation time 3920256648 ps
CPU time 3.12 seconds
Started Jul 10 06:15:47 PM PDT 24
Finished Jul 10 06:15:53 PM PDT 24
Peak memory 201692 kb
Host smart-282f5872-f9cc-4ac0-8c6e-de08525ac82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787596832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.1787596832
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.3163443508
Short name T504
Test name
Test status
Simulation time 5861779180 ps
CPU time 7.63 seconds
Started Jul 10 06:15:43 PM PDT 24
Finished Jul 10 06:15:53 PM PDT 24
Peak memory 201704 kb
Host smart-d80d1836-e4b1-4be8-a110-3caa75b37f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163443508 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.3163443508
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.2760325589
Short name T727
Test name
Test status
Simulation time 335241509055 ps
CPU time 746.49 seconds
Started Jul 10 06:15:49 PM PDT 24
Finished Jul 10 06:28:18 PM PDT 24
Peak memory 210392 kb
Host smart-2967129b-e0e0-42d8-8be9-c495bc242e7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760325589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
2760325589
Directory /workspace/9.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.3004023097
Short name T103
Test name
Test status
Simulation time 96684146963 ps
CPU time 130.94 seconds
Started Jul 10 06:15:46 PM PDT 24
Finished Jul 10 06:18:00 PM PDT 24
Peak memory 218728 kb
Host smart-e5737780-1ebd-4a05-a8f2-82d28bff493f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004023097 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.3004023097
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest
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