Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv



Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
testmode_cp 12 0 12 100.00 100 1 1 0


Summary for Variable testmode_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 12 0 12 100.00


User Defined Bins for testmode_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
testmodes[AdcCtrlTestmodeOneShot] 6891 1 T3 20 T5 20 T6 59
testmodes[AdcCtrlTestmodeNormal] 5429 1 T1 1 T6 45 T7 43
testmodes[AdcCtrlTestmodeLowpower] 5627 1 T2 1 T4 1 T6 33
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot] 3675 1 T3 19 T5 19 T6 35
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal] 1715 1 T6 17 T7 13 T10 2
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower] 1387 1 T6 7 T7 19 T37 19
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot] 1724 1 T6 16 T7 16 T10 1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal] 2012 1 T6 20 T7 13 T9 1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower] 1360 1 T6 8 T7 14 T9 1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot] 1382 1 T6 8 T7 16 T37 14
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal] 1349 1 T6 7 T7 16 T10 1
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower] 2643 1 T6 18 T7 12 T8 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%