Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22531

1

T2

7

T3

20

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3562

1

T1

1

T8

13

T9

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19950

1

T3

20

T5

20

T6

135

auto[1]

6143

1

T1

1

T2

7

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	46	1			T154	8		T260	38		-	-
values[0]	76	1			T261	20		T43	1		T262	8
values[1]	849	1			T9	23		T10	1		T11	1
values[2]	791	1			T45	22		T158	1		T139	23
values[3]	701	1			T9	15		T38	1		T49	10
values[4]	563	1			T2	7		T9	15		T263	16
values[5]	2838	1			T1	1		T4	16		T8	16
values[6]	673	1			T8	13		T11	8		T47	11
values[7]	568	1			T8	5		T49	12		T147	7
values[8]	787	1			T48	12		T166	9		T140	30
values[9]	1237	1			T6	3		T45	24		T49	7
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1119	1			T9	23		T10	1		T11	1
values[1]	684	1			T38	1		T45	22		T180	22
values[2]	834	1			T9	15		T49	10		T147	15
values[3]	2687	1			T2	7		T4	16		T9	15
values[4]	703	1			T1	1		T8	16		T10	20
values[5]	574	1			T8	13		T47	11		T147	7
values[6]	708	1			T8	5		T49	12		T158	1
values[7]	733	1			T48	12		T166	9		T141	18
values[8]	952	1			T6	3		T45	24		T49	7
values[9]	112	1			T60	13		T210	1		T264	12
minimum	16987	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T148	13		T263	3		T261	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T9	12		T10	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T139	14		T154	1		T265	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T38	1		T45	19		T180	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T49	10		T143	6		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T9	4		T147	15		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1498	1			T2	7		T4	16		T9	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T160	19		T146	14		T32	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T8	16		T11	1		T48	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	1		T10	10		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T151	12		T155	11		T208	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T8	13		T47	11		T147	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	5		T49	12		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T158	1		T148	10		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T48	12		T166	9		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T140	14		T150	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T6	2		T49	7		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T45	12		T154	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T60	5		T267	1		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T210	1		T264	1		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16864	1			T3	20		T5	20		T6	135
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T148	11		T261	16		T35	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	11		T149	14		T152	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T139	9		T154	11		T265	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T45	3		T180	10		T269	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T143	6		T35	3		T145	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T9	11		T263	15		T61	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	898	1			T9	10		T12	15		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T160	14		T146	13		T187	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T11	7		T60	18		T270	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T10	10		T46	11		T271	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T155	9		T208	9		T146	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T182	10		T183	5		T35	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T272	12		T273	12		T271	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T148	7		T151	15		T144	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T141	7		T16	2		T250	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T140	16		T154	16		T151	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	1		T146	10		T29	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T45	12		T154	7		T144	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T60	8		T267	3		T213	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T264	11		T274	21		T275	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T60	1		T74	1		T247	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T154	1		T260	16		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T261	10		T276	15		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T43	1		T262	1		T277	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T148	13		T263	3		T261	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T9	12		T10	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T139	14		T154	1		T265	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T45	19		T158	1		T61	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T49	10		T35	6		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T9	4		T38	1		T147	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T2	7		T9	5		T143	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T263	1		T142	12		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1573	1			T4	16		T8	16		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	1		T10	10		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	1		T60	11		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	13		T47	11		T159	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	5		T49	12		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T147	7		T158	1		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	12		T166	9		T193	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T140	14		T154	1		T151	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T6	2		T49	7		T60	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	427	1			T45	12		T181	1		T151	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T154	7		T260	22		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T261	10		T276	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T262	7		T277	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T148	11		T261	6		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	11		T149	14		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T139	9		T154	11		T265	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T45	3		T61	13		T269	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T35	3		T145	11		T278	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T9	11		T180	10		T152	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	10		T143	6		T187	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T263	15		T279	1		T278	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	923	1			T12	15		T173	4		T280	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T10	10		T46	11		T160	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T11	7		T60	18		T181	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T183	4		T35	1		T281	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T141	7		T155	9		T272	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T148	7		T182	10		T183	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T282	14		T283	2		T271	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T140	16		T154	16		T151	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T6	1		T60	8		T146	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T45	12		T151	13		T144	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	366	1			T148	12		T263	1		T261	18
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	12		T10	1		T11	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T139	10		T154	12		T265	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	1		T45	4		T180	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T49	1		T143	7		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	12		T147	1		T263	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1213	1			T2	1		T4	1		T9	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T160	15		T146	14		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	1		T11	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T1	1		T10	11		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T151	1		T155	10		T208	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T8	1		T47	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T8	1		T49	1		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T158	1		T148	8		T150	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T48	1		T166	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T140	17		T150	1		T154	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T6	3		T49	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T45	13		T154	8		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T60	9		T267	4		T268	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T210	1		T264	12		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16980	1			T3	20		T5	20		T6	135
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T148	12		T263	2		T261	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	11		T48	10		T149	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T139	13		T265	10		T157	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T45	18		T180	11		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T49	9		T143	5		T35	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T9	3		T147	14		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T2	6		T4	15		T9	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T160	18		T146	13		T32	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T8	15		T48	12		T60	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T10	9		T46	11		T284	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T151	11		T155	10		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T8	12		T47	10		T147	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T8	4		T49	11		T273	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	9		T151	12		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T48	11		T166	8		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T140	13		T151	14		T144	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T49	6		T167	16		T183	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T45	11		T144	15		T208	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T60	4		T213	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T274	5		T275	7		T285	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T286	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T154	8		T260	23		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T261	11		T276	11		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T43	1		T262	8		T277	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T148	12		T263	1		T261	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T9	12		T10	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T139	10		T154	12		T265	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T45	4		T158	1		T61	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T49	1		T35	6		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T9	12		T38	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T2	1		T9	11		T143	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T263	16		T142	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1251	1			T4	1		T8	1		T12	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T1	1		T10	11		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T11	8		T60	20		T181	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T8	1		T47	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	1		T49	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T147	1		T158	1		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T48	1		T166	1		T193	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T140	17		T154	17		T151	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	3		T49	1		T60	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	419	1			T45	13		T181	1		T151	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T260	15		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T261	9		T276	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T277	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T148	12		T263	2		T261	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T9	11		T48	10		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T139	13		T265	10		T157	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T45	18		T61	3		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T49	9		T35	3		T278	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T9	3		T147	14		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T2	6		T9	4		T143	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T142	11		T278	6		T32	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T4	15		T8	15		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T10	9		T46	11		T160	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T60	9		T151	11		T193	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T8	12		T47	10		T159	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	4		T49	11		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T147	6		T148	9		T182	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T48	11		T166	8		T193	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T140	13		T151	12		T144	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	6		T60	4		T167	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T45	11		T151	14		T144	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20334

1

T1

1

T2

7

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

5759

1

T4

16

T6

3

T8

16

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20463

1

T1

1

T2

7

T3

20

auto[1]

5630

1

T4

16

T8

16

T9

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	2	1			T287	1		T288	1		-	-
values[0]	41	1			T156	1		T24	1		T289	9
values[1]	674	1			T9	15		T45	24		T158	1
values[2]	784	1			T9	15		T11	8		T49	7
values[3]	837	1			T60	34		T263	19		T142	4
values[4]	680	1			T47	11		T142	12		T152	7
values[5]	631	1			T10	1		T48	13		T147	15
values[6]	746	1			T1	1		T8	5		T166	9
values[7]	600	1			T2	7		T11	1		T46	23
values[8]	556	1			T8	13		T10	20		T49	12
values[9]	3578	1			T4	16		T6	3		T8	16
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	973	1			T9	15		T49	7		T158	2
values[1]	2962	1			T4	16		T9	15		T11	8
values[2]	854	1			T60	21		T263	19		T142	16
values[3]	650	1			T47	11		T147	15		T152	7
values[4]	679	1			T1	1		T8	5		T10	1
values[5]	561	1			T148	17		T141	18		T139	23
values[6]	652	1			T2	7		T11	1		T46	23
values[7]	570	1			T8	13		T48	23		T158	1
values[8]	1023	1			T6	3		T8	16		T9	23
values[9]	187	1			T38	1		T60	8		T191	1
minimum	16982	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T9	5		T158	2		T61	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T49	7		T149	16		T270	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T11	1		T150	1		T151	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1569	1			T4	16		T9	4		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T263	1		T142	16		T159	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T60	10		T263	3		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	5		T159	3		T183	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T47	11		T147	15		T143	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	1		T8	5		T166	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T10	1		T48	13		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T273	3		T290	3		T291	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T148	10		T141	11		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T2	7		T46	12		T139	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	1		T49	12		T147	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T8	13		T48	11		T158	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	12		T181	1		T155	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T9	12		T10	10		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T6	2		T8	16		T45	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T38	1		T60	1		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T191	1		T250	1		T194	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16857	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T292	7		T293	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T9	10		T61	13		T140	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T149	14		T270	8		T154	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	7		T208	9		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	945	1			T9	11		T12	15		T45	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T263	15		T183	1		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T60	11		T154	16		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T152	2		T35	13		T281	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T143	11		T265	3		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T144	23		T265	9		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T36	1		T294	1		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T273	10		T290	3		T295	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T148	7		T141	7		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T46	11		T160	1		T271	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T180	10		T154	11		T272	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T282	11		T185	11		T239	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T181	9		T155	9		T296	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T9	11		T10	10		T261	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T6	1		T45	3		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T60	7		T145	11		T297	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T194	5		T298	4		T198	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T292	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T287	1		T288	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T289	8		T268	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T156	1		T24	1		T289	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T9	5		T158	1		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T45	12		T149	16		T270	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T11	1		T158	1		T61	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T9	4		T49	7		T144	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T263	1		T142	4		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T60	15		T263	3		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T142	12		T152	5		T159	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T47	11		T265	11		T35	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T181	1		T265	11		T35	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T10	1		T48	13		T147	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	1		T8	5		T166	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	10		T139	14		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T2	7		T46	12		T193	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T11	1		T147	7		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T8	13		T10	10		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	12		T180	12		T155	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	351	1			T9	12		T38	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1827	1			T4	16		T6	2		T8	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T17	1		T276	7		T292	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T9	10		T152	11		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T45	12		T149	14		T270	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T11	7		T61	13		T140	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T9	11		T144	3		T278	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T263	15		T208	9		T183	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T60	19		T154	16		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T152	2		T156	2		T14	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T265	3		T35	3		T299	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T265	9		T35	13		T281	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T143	11		T146	10		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T144	23		T271	7		T290	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T148	7		T139	9		T269	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T46	11		T160	1		T273	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T141	7		T154	11		T181	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T10	10		T185	11		T300	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T180	10		T155	9		T272	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T9	11		T60	7		T261	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1122	1			T6	1		T12	15		T45	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1