Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22550

1

T2

7

T3

20

T4

16

auto[ADC_CTRL_FILTER_COND_OUT]

3543

1

T1

1

T8

13

T9

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19970

1

T3

20

T5

20

T6

135

auto[1]

6123

1

T1

1

T2

7

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	151	1			T191	1		T146	24		T29	6
values[0]	24	1			T355	24		-	-		-	-
values[1]	903	1			T9	23		T10	1		T11	1
values[2]	800	1			T45	22		T158	1		T139	23
values[3]	734	1			T9	15		T38	1		T49	10
values[4]	500	1			T2	7		T9	15		T142	12
values[5]	2857	1			T1	1		T4	16		T8	16
values[6]	653	1			T8	13		T11	8		T47	11
values[7]	545	1			T8	5		T49	12		T158	1
values[8]	876	1			T48	12		T166	9		T141	18
values[9]	1086	1			T6	3		T45	24		T49	7
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	817	1			T11	1		T148	24		T149	30
values[1]	688	1			T38	1		T45	22		T180	22
values[2]	799	1			T9	15		T49	10		T147	15
values[3]	2643	1			T2	7		T4	16		T9	15
values[4]	732	1			T1	1		T8	16		T10	20
values[5]	585	1			T8	13		T47	11		T147	7
values[6]	650	1			T8	5		T49	12		T158	1
values[7]	807	1			T48	12		T166	9		T141	18
values[8]	930	1			T6	3		T45	24		T49	7
values[9]	128	1			T60	13		T210	1		T298	10
minimum	17314	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T148	13		T261	8		T35	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T11	1		T149	16		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T139	14		T154	1		T265	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T38	1		T45	19		T180	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T49	10		T143	6		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T9	4		T147	15		T263	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1495	1			T2	7		T4	16		T9	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T160	19		T278	7		T32	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	16		T11	1		T48	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	1		T10	10		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T151	12		T155	11		T208	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	13		T47	11		T147	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T8	5		T49	12		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T158	1		T148	10		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T48	12		T166	9		T141	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T140	14		T150	1		T154	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T6	2		T49	7		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T45	12		T154	1		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T60	5		T268	1		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T210	1		T298	6		T264	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16958	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T9	12		T10	1		T48	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T148	11		T261	6		T35	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T149	14		T152	11		T143	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T139	9		T154	11		T265	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T45	3		T180	10		T269	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T143	6		T35	3		T278	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T9	11		T263	15		T61	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	889	1			T9	10		T12	15		T173	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T160	14		T278	1		T40	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T11	7		T60	18		T270	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T10	10		T46	11		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T155	9		T208	9		T183	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T182	10		T35	1		T209	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T272	12		T273	12		T271	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T148	7		T151	15		T144	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T141	7		T282	14		T283	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T140	16		T154	16		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	1		T146	10		T29	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T45	12		T154	7		T151	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T60	8		T213	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T298	4		T264	11		T274	21
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T9	11		T155	8		T39	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T191	1		T146	14		T29	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T299	6		T16	1		T356	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T355	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T148	13		T263	3		T261	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T9	12		T10	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	294	1			T139	14		T154	1		T265	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T45	19		T158	1		T61	4
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T49	10		T35	6		T145	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T9	4		T38	1		T147	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T2	7		T9	5		T143	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T142	12		T191	1		T315	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1589	1			T4	16		T8	16		T12	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T1	1		T10	10		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	1		T60	1		T181	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T8	13		T47	11		T147	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T8	5		T49	12		T266	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T158	1		T148	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	12		T166	9		T141	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T140	14		T150	1		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T6	2		T49	7		T60	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	390	1			T45	12		T154	1		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T146	10		T29	2		T326	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T299	7		T298	4		T275	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T355	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T148	11		T261	16		T35	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	11		T149	14		T143	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T139	9		T154	11		T265	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T45	3		T61	13		T269	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T35	3		T145	11		T278	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T9	11		T180	10		T263	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T9	10		T143	6		T187	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T279	1		T278	1		T40	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	941	1			T12	15		T60	11		T173	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T10	10		T46	11		T160	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T11	7		T60	7		T181	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T35	1		T209	13		T281	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T272	12		T273	12		T237	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T148	7		T182	10		T183	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T141	7		T282	14		T283	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T140	16		T154	16		T151	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	1		T60	8		T238	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	332	1			T45	12		T154	7		T151	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T148	12		T261	7		T35	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T11	1		T149	15		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T139	10		T154	12		T265	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T38	1		T45	4		T180	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T49	1		T143	7		T35	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T9	12		T147	1		T263	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1201	1			T2	1		T4	1		T9	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T160	15		T278	2		T32	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	1		T11	8		T48	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T1	1		T10	11		T46	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T151	1		T155	10		T208	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T8	1		T47	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T8	1		T49	1		T266	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T158	1		T148	8		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	1		T166	1		T141	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T140	17		T150	1		T154	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	3		T49	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T45	13		T154	8		T181	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T60	9		T268	1		T213	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T210	1		T298	8		T264	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17069	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T9	12		T10	1		T48	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T148	12		T261	7		T157	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T149	15		T152	2		T143	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T139	13		T265	10		T242	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T45	18		T180	11		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	9		T143	5		T35	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	3		T147	14		T142	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1183	1			T2	6		T4	15		T9	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T160	18		T278	6		T32	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T8	15		T48	12		T60	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T10	9		T46	11		T146	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T151	11		T155	10		T208	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T8	12		T47	10		T147	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T8	4		T49	11		T273	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T148	9		T151	12		T144	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T48	11		T166	8		T141	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T140	13		T144	13		T301	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T49	6		T167	16		T146	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T45	11		T151	14		T144	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T60	4		T213	9		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T298	2		T274	5		T275	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T263	2		T261	9		T294	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T9	11		T48	10		T155	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T191	1		T146	11		T29	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T299	8		T16	1		T356	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T355	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T148	12		T263	1		T261	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T9	12		T10	1		T11	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T139	10		T154	12		T265	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T45	4		T158	1		T61	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T49	1		T35	6		T145	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T9	12		T38	1		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T2	1		T9	11		T143	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T142	1		T191	1		T315	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T4	1		T8	1		T12	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T1	1		T10	11		T46	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	8		T60	8		T181	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T8	1		T47	1		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T8	1		T49	1		T266	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T158	1		T148	8		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T48	1		T166	1		T141	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	287	1			T140	17		T150	1		T154	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	3		T49	1		T60	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	402	1			T45	13		T154	8		T181	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T146	13		T29	2		T357	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T299	5		T298	2		T275	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T355	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T148	12		T263	2		T261	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T9	11		T48	10		T149	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T139	13		T265	10		T157	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T45	18		T61	3		T152	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T49	9		T35	3		T278	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T9	3		T147	14		T180	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T2	6		T9	4		T143	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T142	11		T278	6		T32	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1266	1			T4	15		T8	15		T48	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T10	9		T46	11		T160	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T151	11		T193	11		T155	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T8	12		T47	10		T147	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T8	4		T49	11		T273	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T148	9		T182	12		T308	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T48	11		T166	8		T141	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T140	13		T151	12		T144	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T49	6		T60	4		T167	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T45	11		T151	14		T144	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31