Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22502

1

T1

1

T2

7

T3

20

auto[ADC_CTRL_FILTER_COND_OUT]

3591

1

T8

34

T9

23

T10

21

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20096

1

T2

7

T3

20

T5

20

auto[1]

5997

1

T1

1

T4

16

T9

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	28	1			T35	14		T212	9		T341	5
values[0]	59	1			T166	9		T188	1		T211	7
values[1]	772	1			T6	3		T9	30		T10	20
values[2]	599	1			T8	29		T46	23		T154	12
values[3]	671	1			T8	5		T11	1		T47	11
values[4]	618	1			T48	13		T261	20		T150	1
values[5]	3042	1			T1	1		T2	7		T4	16
values[6]	635	1			T9	23		T11	8		T60	21
values[7]	870	1			T48	11		T60	8		T147	7
values[8]	584	1			T49	7		T142	12		T139	1
values[9]	1251	1			T45	46		T48	12		T49	22
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1021	1			T9	30		T10	20		T38	1
values[1]	523	1			T8	29		T11	1		T47	11
values[2]	728	1			T8	5		T46	23		T158	1
values[3]	2944	1			T4	16		T10	1		T12	17
values[4]	643	1			T1	1		T9	23		T60	13
values[5]	814	1			T2	7		T11	8		T60	21
values[6]	592	1			T48	11		T60	8		T269	9
values[7]	709	1			T48	12		T49	17		T158	1
values[8]	962	1			T45	46		T49	12		T142	4
values[9]	172	1			T160	2		T28	5		T162	1
minimum	16985	1			T3	20		T5	20		T6	138

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T9	9		T148	10		T154	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T10	10		T38	1		T166	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T150	1		T152	5		T155	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	29		T11	1		T47	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T158	1		T261	10		T143	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T8	5		T46	12		T151	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1549	1			T4	16		T12	2		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	284	1			T10	1		T48	13		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	1		T263	4		T183	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	12		T60	5		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T2	7		T159	8		T160	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T11	1		T60	10		T147	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T269	1		T208	8		T44	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T48	11		T60	1		T261	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T49	10		T158	1		T181	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	12		T49	7		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	358	1			T45	31		T49	12		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T142	4		T61	4		T154	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T160	1		T28	4		T339	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T162	1		T110	2		T345	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16858	1			T3	20		T5	20		T6	137
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T366	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T9	21		T148	7		T154	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T10	10		T141	7		T208	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T152	2		T155	8		T281	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T194	16		T367	9		T368	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T261	10		T143	11		T144	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T46	11		T145	11		T40	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	939	1			T12	15		T173	4		T280	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T143	6		T265	3		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T263	15		T283	2		T223	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	11		T60	8		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T160	14		T146	13		T290	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T11	7		T60	11		T180	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T269	8		T208	7		T251	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T60	7		T261	6		T185	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T181	9		T187	16		T317	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T144	11		T273	12		T271	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T45	15		T140	16		T265	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T61	13		T154	7		T35	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T160	1		T28	1		T339	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T110	1		T345	4		T369	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T6	1		T60	1		T74	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T366	8		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T212	4		T341	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T35	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T166	9		T188	1		T211	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T6	2		T9	9		T148	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T10	10		T38	1		T147	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T154	1		T315	1		T39	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T8	29		T46	12		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T158	1		T150	1		T152	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T8	5		T11	1		T47	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T261	10		T151	15		T156	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T48	13		T150	1		T151	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1558	1			T1	1		T2	7		T4	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T10	1		T60	5		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T263	3		T183	3		T317	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T9	12		T11	1		T60	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T269	1		T193	12		T159	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T48	11		T60	1		T147	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T181	1		T191	2		T167	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T49	7		T142	12		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	465	1			T45	31		T49	22		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T48	12		T142	4		T61	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T212	5		T341	4		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T35	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T302	12		T370	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	1		T9	21		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T10	10		T141	7		T208	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T154	11		T39	2		T281	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T46	11		T183	1		T278	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T152	2		T143	11		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T145	11		T317	12		T90	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T261	10		T151	13		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T152	11		T143	6		T146	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T12	15		T173	4		T263	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T60	8		T139	9		T154	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T317	12		T242	11		T262	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	11		T11	7		T60	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T269	8		T160	14		T146	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T60	7		T180	10		T149	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T181	9		T208	7		T317	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T273	12		T185	11		T92	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T45	15		T140	16		T265	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T61	13		T154	7		T144	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T9	23		T148	8		T154	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T10	11		T38	1		T166	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T150	1		T152	3		T155	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T8	2		T11	1		T47	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T158	1		T261	11		T143	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T8	1		T46	12		T151	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1264	1			T4	1		T12	17		T153	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T10	1		T48	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T263	17		T183	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T9	12		T60	9		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T2	1		T159	1		T160	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T11	8		T60	12		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T269	9		T208	8		T44	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	1		T60	8		T261	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T49	1		T158	1		T181	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T48	1		T49	1		T142	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	329	1			T45	17		T49	1		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T142	1		T61	14		T154	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T160	2		T28	4		T339	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T162	1		T110	2		T345	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16967	1			T3	20		T5	20		T6	138
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T366	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T9	7		T148	9		T182	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T10	9		T166	8		T147	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T152	4		T155	10		T281	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T8	27		T47	10		T211	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T261	9		T143	14		T144	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T8	4		T46	11		T151	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1224	1			T4	15		T314	14		T151	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T48	12		T143	5		T193	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T263	2		T183	2		T289	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T9	11		T60	4		T139	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T2	6		T159	7		T160	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T60	9		T147	6		T180	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T208	7		T251	4		T242	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	10		T261	7		T185	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T49	9		T193	11		T167	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T48	11		T49	6		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T45	29		T49	11		T140	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T142	3		T61	3		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T28	1		T339	11		T343	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T110	1		T345	7		T369	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T366	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T212	6		T341	5		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T35	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T166	1		T188	1		T211	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T6	3		T9	23		T148	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T10	11		T38	1		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T154	12		T315	1		T39	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T8	2		T46	12		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T158	1		T150	1		T152	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	1		T11	1		T47	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T261	11		T151	14		T156	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	1		T150	1		T151	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T1	1		T2	1		T4	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T10	1		T60	9		T158	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T263	1		T183	1		T317	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T9	12		T11	8		T60	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T269	9		T193	1		T159	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T48	1		T60	8		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T181	10		T191	2		T167	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T49	1		T142	1		T139	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	414	1			T45	17		T49	2		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T48	1		T142	1		T61	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T212	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T166	8		T211	6		T337	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T9	7		T148	9		T182	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T10	9		T147	14		T141	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T39	1		T281	8		T346	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T8	27		T46	11		T278	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T152	4		T143	14		T144	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T8	4		T47	10		T317	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T261	9		T151	14		T156	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	12		T151	11		T152	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1230	1			T2	6		T4	15		T314	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T60	4		T139	13		T193	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T263	2		T183	2		T317	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T9	11		T60	9		T148	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T193	11		T159	7		T160	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T48	10		T147	6		T180	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T167	4		T208	7		T317	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T49	6		T142	11		T273	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	361	1			T45	29		T49	20		T140	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T48	11		T142	3		T61	3

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31