Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20307

1

T1

1

T3

20

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

5786

1

T2

7

T4

16

T6

3

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20505

1

T1

1

T2

7

T3

20

auto[1]

5588

1

T4

16

T8

16

T9

38

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	354	1			T6	3		T38	1		T49	10
values[0]	35	1			T156	1		T238	2		T289	8
values[1]	647	1			T9	15		T158	1		T149	30
values[2]	854	1			T9	15		T11	8		T45	24
values[3]	824	1			T60	34		T263	19		T142	4
values[4]	614	1			T47	11		T142	12		T152	7
values[5]	723	1			T1	1		T10	1		T48	13
values[6]	675	1			T8	5		T148	17		T139	23
values[7]	624	1			T2	7		T11	1		T46	23
values[8]	544	1			T8	13		T180	22		T158	1
values[9]	3235	1			T4	16		T8	16		T9	23
minimum	16964	1			T3	20		T5	20		T6	135

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	752	1			T9	15		T49	7		T158	1
values[1]	2961	1			T4	16		T9	15		T11	8
values[2]	858	1			T60	34		T263	19		T142	16
values[3]	661	1			T47	11		T147	15		T152	7
values[4]	639	1			T1	1		T8	5		T10	1
values[5]	601	1			T148	17		T141	18		T139	23
values[6]	631	1			T2	7		T8	13		T11	1
values[7]	536	1			T48	11		T158	1		T139	1
values[8]	1118	1			T6	3		T8	16		T9	23
values[9]	137	1			T38	1		T60	8		T261	20
minimum	17199	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T9	5		T158	1		T61	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T49	7		T151	13		T272	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	277	1			T11	1		T158	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1564	1			T4	16		T9	4		T12	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T263	1		T142	16		T159	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T60	15		T263	3		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T152	5		T159	3		T183	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T47	11		T147	15		T143	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T1	1		T8	5		T166	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T10	1		T48	13		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T273	3		T290	3		T291	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T148	10		T141	11		T139	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T8	13		T46	12		T193	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T2	7		T11	1		T49	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T48	11		T158	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T261	8		T155	11		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T9	12		T10	10		T49	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	377	1			T6	2		T8	16		T45	19
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T38	1		T60	1		T261	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T194	5		T371	1		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16890	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T149	16		T270	10		T154	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T9	10		T61	13		T140	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T151	15		T278	10		T246	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T11	7		T208	9		T160	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	937	1			T9	11		T12	15		T45	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T263	15		T183	1		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T60	19		T154	16		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T152	2		T35	13		T281	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T143	11		T265	3		T146	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T144	23		T265	9		T169	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T36	1		T294	1		T28	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T273	10		T290	3		T295	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T148	7		T141	7		T139	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T46	11		T160	1		T271	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T180	10		T181	9		T272	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T282	11		T185	11		T300	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T261	6		T155	9		T296	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T9	11		T10	10		T155	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T6	1		T45	3		T148	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T60	7		T261	10		T145	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T194	5		T371	12		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T60	1		T74	1		T247	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T149	14		T270	8		T154	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T38	1		T49	10		T261	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T6	2		T191	1		T90	21
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T289	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T156	1		T238	1		T276	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T9	5		T158	1		T152	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T149	16		T270	10		T154	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T11	1		T158	1		T61	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T9	4		T45	12		T49	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T263	1		T142	4		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T60	15		T263	3		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T142	12		T152	5		T159	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T47	11		T265	11		T35	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T1	1		T166	9		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T10	1		T48	13		T147	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T8	5		T144	14		T271	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T148	10		T139	14		T269	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T46	12		T193	9		T160	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T2	7		T11	1		T49	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T8	13		T158	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T180	12		T155	11		T157	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T9	12		T10	10		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1737	1			T4	16		T8	16		T12	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16856	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T261	10		T155	8		T209	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T6	1		T90	12		T362	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T238	1		T276	7		T292	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T9	10		T152	11		T182	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T149	14		T270	8		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	7		T61	13		T140	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T9	11		T45	12		T144	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T263	15		T183	1		T160	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T60	19		T154	16		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T152	2		T14	2		T168	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T265	3		T35	3		T319	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T144	11		T265	9		T35	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T143	11		T146	10		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T144	12		T271	7		T290	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T148	7		T139	9		T269	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T46	11		T160	1		T273	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T141	7		T154	11		T181	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T185	11		T300	9		T170	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T180	10		T155	9		T296	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T9	11		T10	10		T60	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1039	1			T12	15		T45	3		T173	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	11		T158	1		T61	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T49	1		T151	16		T272	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	8		T158	1		T150	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1261	1			T4	1		T9	12		T12	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T263	16		T142	2		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T60	21		T263	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T152	3		T159	1		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T47	1		T147	1		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	1		T8	1		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T10	1		T48	1		T191	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T273	11		T290	4		T291	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T148	8		T141	8		T139	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T8	1		T46	12		T193	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T2	1		T11	1		T49	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T48	1		T158	1		T139	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T261	7		T155	10		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T9	12		T10	11		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T6	3		T8	1		T45	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T38	1		T60	8		T261	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T194	6		T371	13		-	-
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17018	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T149	15		T270	9		T154	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T9	4		T61	3		T140	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T49	6		T151	12		T278	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T151	11		T208	10		T160	18
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1240	1			T4	15		T9	3		T45	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T142	14		T159	7		T156	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T60	13		T263	2		T35	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T152	4		T159	2		T183	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T47	10		T147	14		T143	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T8	4		T166	8		T144	28
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T48	12		T167	4		T36	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T273	2		T290	2		T295	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T148	9		T141	10		T139	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T8	12		T46	11		T193	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T2	6		T49	11		T147	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T48	10		T282	9		T185	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T261	7		T155	10		T296	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T9	11		T10	9		T49	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T8	15		T45	18		T48	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T261	9		T301	2		T372	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T194	4		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T289	7		T313	17		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T149	15		T270	9		T143	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T38	1		T49	1		T261	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T6	3		T191	1		T90	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T289	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T156	1		T238	2		T276	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T9	11		T158	1		T152	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T149	15		T270	9		T154	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T11	8		T158	1		T61	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	12		T45	13		T49	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T263	16		T142	1		T150	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T60	21		T263	1		T150	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T142	1		T152	3		T159	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T47	1		T265	4		T35	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	1		T166	1		T181	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T10	1		T48	1		T147	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T8	1		T144	13		T271	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T148	8		T139	10		T269	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T46	12		T193	1		T160	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T2	1		T11	1		T49	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T8	1		T158	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T180	11		T155	10		T157	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T9	12		T10	11		T48	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1385	1			T4	1		T8	1		T12	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16964	1			T3	20		T5	20		T6	135
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T49	9		T261	9		T155	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T90	20		T351	16		T298	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T289	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T276	7		T292	6		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T9	4		T152	2		T182	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T149	15		T270	9		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T61	3		T140	13		T151	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T9	3		T45	11		T49	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T142	3		T160	18		T156	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T60	13		T263	2		T151	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T142	11		T152	4		T159	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T47	10		T265	10		T35	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T166	8		T144	15		T265	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T48	12		T147	14		T143	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T8	4		T144	13		T290	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T148	9		T139	13		T183	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T46	11		T193	8		T273	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T2	6		T49	11		T147	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T8	12		T185	13		T170	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T180	11		T155	10		T157	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T9	11		T10	9		T48	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1391	1			T4	15		T8	15		T45	18

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31