Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26093

1

T1

1

T2

7

T3

20

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22701

1

T3

20

T4

16

T5

20

auto[ADC_CTRL_FILTER_COND_OUT]

3392

1

T1

1

T2

7

T9

38

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19938

1

T3

20

T5

20

T6

130

auto[1]

6155

1

T1

1

T2

7

T4

16

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22090

1

T1

1

T2

7

T3

20

auto[1]

4003

1

T6

1

T9

32

T10

10

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	417	1			T6	5		T7	4		T37	1
values[0]	61	1			T144	9		T239	15		T170	11
values[1]	603	1			T8	5		T180	22		T139	24
values[2]	2888	1			T1	1		T4	16		T11	1
values[3]	820	1			T6	3		T49	12		T149	30
values[4]	699	1			T8	13		T46	23		T48	12
values[5]	754	1			T2	7		T9	15		T11	8
values[6]	850	1			T8	16		T10	1		T60	13
values[7]	805	1			T38	1		T45	24		T47	11
values[8]	611	1			T10	20		T61	17		T154	17
values[9]	1005	1			T9	38		T147	7		T158	1
minimum	16580	1			T3	20		T5	20		T6	130

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	768	1			T1	1		T8	5		T11	1
values[1]	2917	1			T4	16		T6	3		T12	17
values[2]	824	1			T46	23		T49	12		T149	30
values[3]	661	1			T8	13		T48	12		T60	29
values[4]	832	1			T8	16		T9	15		T10	1
values[5]	674	1			T2	7		T45	24		T60	13
values[6]	864	1			T38	1		T48	11		T158	1
values[7]	595	1			T10	20		T47	11		T158	1
values[8]	801	1			T9	15		T147	7		T148	17
values[9]	126	1			T9	23		T188	1		T251	7
minimum	17031	1			T3	20		T5	20		T6	135

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

4143

1

T2

6

T4

15

T8

31

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T8	5		T139	15		T152	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	1		T11	1		T147	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1604	1			T4	16		T6	2		T12	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T263	1		T144	14		T265	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T49	12		T149	16		T150	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T46	12		T208	11		T183	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T8	13		T60	1		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	12		T60	10		T166	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T8	16		T11	1		T49	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T9	4		T10	1		T261	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	12		T142	4		T140	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T2	7		T60	5		T142	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T48	11		T263	3		T154	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T38	1		T158	1		T61	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T47	11		T158	1		T183	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T10	10		T167	5		T159	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T9	5		T147	7		T148	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T193	9		T282	10		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T251	5		T373	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T9	12		T188	1		T171	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16868	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T366	10		T368	1		T267	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T139	9		T152	2		T143	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T290	14		T239	14		T339	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	958	1			T6	1		T12	15		T45	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T263	15		T144	12		T265	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T149	14		T151	15		T146	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	11		T208	9		T183	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T60	7		T148	11		T181	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T60	11		T35	13		T145	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	7		T141	7		T151	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T9	11		T261	6		T154	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T45	12		T140	16		T270	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T60	8		T273	12		T28	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T154	16		T278	10		T317	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T61	13		T269	8		T144	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T183	4		T39	2		T209	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T10	10		T271	7		T303	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	10		T148	7		T154	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T282	14		T238	1		T317	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T251	2		T304	2		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T9	11		T171	5		T258	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T60	1		T180	10		T74	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T366	8		T368	8		T267	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	388	1			T6	5		T7	4		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T282	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T144	6		T170	8		T246	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T239	1		T366	10		T353	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T8	5		T180	12		T139	15
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	100	1			T191	1		T315	1		T290	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1548	1			T4	16		T12	2		T45	19
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	1		T11	1		T147	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T6	2		T49	12		T149	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T144	14		T183	1		T35	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T8	13		T60	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T46	12		T48	12		T166	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T11	1		T49	7		T148	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T2	7		T9	4		T60	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T8	16		T141	11		T142	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T10	1		T60	5		T142	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T45	12		T47	11		T48	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T38	1		T158	1		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T154	1		T156	1		T39	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T10	10		T61	4		T159	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T9	5		T147	7		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T9	12		T193	9		T167	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16472	1			T3	20		T5	20		T6	130
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T304	2		T374	3		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T282	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T144	3		T170	3		T246	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T239	14		T366	8		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T180	10		T139	9		T152	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T290	14		T44	4		T168	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	931	1			T12	15		T45	3		T173	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T263	15		T265	9		T160	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	1		T149	14		T151	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T144	12		T183	1		T35	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T60	7		T181	9		T155	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T46	11		T208	9		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	7		T148	11		T151	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T9	11		T60	11		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T141	7		T140	16		T270	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T60	8		T261	6		T155	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	12		T143	11		T29	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T269	8		T144	11		T279	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T154	16		T39	2		T209	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T10	10		T61	13		T271	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T9	10		T148	7		T154	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	11		T238	1		T317	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T60	1		T74	1		T247	1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T8	1		T139	11		T152	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T1	1		T11	1		T147	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1287	1			T4	1		T6	3		T12	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T263	16		T144	13		T265	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T49	1		T149	15		T150	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T46	12		T208	10		T183	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T8	1		T60	8		T158	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T48	1		T60	12		T166	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T8	1		T11	8		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T9	12		T10	1		T261	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T45	13		T142	1		T140	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T2	1		T60	9		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T48	1		T263	1		T154	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T38	1		T158	1		T61	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T47	1		T158	1		T183	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T10	11		T167	1		T159	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T9	11		T147	1		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T193	1		T282	15		T162	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T251	3		T373	1		T172	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T9	12		T188	1		T171	6
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16975	1			T3	20		T5	20		T6	135
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T366	9		T368	9		T267	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T8	4		T139	13		T152	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T147	14		T290	14		T339	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T4	15		T45	18		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	13		T265	10		T160	18
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T49	11		T149	15		T151	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T46	11		T208	10		T89	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T8	12		T148	12		T155	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T48	11		T60	9		T166	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T8	15		T49	6		T141	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	3		T261	7		T182	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T45	11		T142	3		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T2	6		T60	4		T142	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	10		T263	2		T278	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T61	3		T144	15		T183	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T47	10		T183	12		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T10	9		T167	4		T159	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	4		T147	6		T148	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T193	8		T282	9		T317	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T251	4		T330	17		T233	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T9	11		T171	5		T343	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T180	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T366	9		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	393	1			T6	5		T7	4		T37	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T282	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T144	4		T170	4		T246	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T239	15		T366	9		T353	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T8	1		T180	11		T139	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T191	1		T315	1		T290	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1257	1			T4	1		T12	17		T45	4
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	1		T11	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T6	3		T49	1		T149	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T144	13		T183	2		T35	24
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T8	1		T60	8		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T46	12		T48	1		T166	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	8		T49	1		T148	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T2	1		T9	12		T60	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T8	1		T141	8		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T10	1		T60	9		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T45	13		T47	1		T48	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T38	1		T158	1		T266	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T154	17		T156	1		T39	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T10	11		T61	14		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T9	11		T147	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T9	12		T193	1		T167	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16580	1			T3	20		T5	20		T6	130
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T282	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T144	5		T170	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T366	9		T353	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T8	4		T180	11		T139	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T290	14		T168	10		T110	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1222	1			T4	15		T45	18		T48	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T147	14		T265	10		T160	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T49	11		T149	15		T151	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T144	13		T35	4		T250	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T8	12		T155	10		T208	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T46	11		T48	11		T166	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T49	6		T148	12		T151	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T2	6		T9	3		T60	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T8	15		T141	10		T142	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T60	4		T142	11		T261	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T45	11		T47	10		T48	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T144	15		T183	2		T279	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T39	1		T313	5		T325	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T10	9		T61	3		T159	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T9	4		T147	6		T148	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T9	11		T193	8		T167	4

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

21950

1

T1

1

T2

1

T3

20

auto[1]

auto[0]

4143

1

T2

6

T4

15

T8

31